Abstract: A semiconductor structure providing a precision resistive element and method of fabrication is disclosed. Polysilicon is embedded in a silicon substrate. The polysilicon may be doped to control the resistance. Embodiments may include resistors, eFuses, and silicon-on-insulator structures. Some embodiments may include non-rectangular cross sections.

Abstract: A module includes a semiconductor chip having at least a first terminal contact surface and a second terminal contact surface. A first bond element made of a material on the basis of Cu is attached to the first terminal contact surface, and a second bond element is attached to the second terminal contact surface. The second bond element is made of a material different from the material of the first bond element or is made of a type of bond element different from the type of the first bond element.

Abstract: The use of doped silicon nanoparticle inks and other liquid dopant sources can provide suitable dopant sources for driving dopant elements into a crystalline silicon substrate using a thermal process if a suitable cap is provided. Suitable caps include, for example, a capping slab, a cover that may or may not rest on the surface of the substrate and a cover layer. Desirable dopant profiled can be achieved. The doped nanoparticles can be delivered using a silicon ink. The residual silicon ink can be removed after the dopant drive-in or at least partially densified into a silicon material that is incorporated into the product device. The silicon doping is suitable for the introduction of dopants into crystalline silicon for the formation of solar cells.

Abstract: A comb drive includes a pivotable mirror element, a first and a second comb electrode, the second comb electrode being movable along an offset direction relative to the first electrode from a minimum into a maximum offset position, the second electrode being connected to the mirror element via a lever arm pivotable about a pivot axis, the first and second comb electrodes being interlockingly engaged so that a first comb tooth of the first electrode and a second comb tooth of the second electrode are situated adjacent to one another along a projection direction extending perpendicularly to the offset direction, the first comb tooth and/or the second comb tooth being configured so that an average distance between the first comb tooth and the second comb tooth along the projection direction extending perpendicularly to the offset direction decreases when moving the second electrode from the minimum into the maximum offset position.

Abstract: A semiconductor buffer structure includes a silicon substrate, a nucleation layer formed on the silicon substrate, and a buffer layer formed on the nucleation layer. The buffer layer includes a first layer formed of a nitride semiconductor material having a uniform composition rate, a second layer formed of the same material as the nucleation layer on the first layer, and a third layer formed of the same material with the same composition ratio as the first layer on the second layer.

Abstract: A device is described in one embodiment that includes a micro-electro-mechanical systems (MEMS) device disposed on a first substrate and a semiconductor device disposed on a second substrate. A bond electrically connects the MEMS device and the semiconductor device. The bond includes an interface between a first bonding layer including silicon on the first substrate and a second bonding layer including aluminum on the second substrate. The physical interface between the aluminum and silicon (e.g., amorphous silicon) can provide an electrical connection.

Abstract: The invention provides an array substrate, a method for manufacturing the array substrate, and a display panel, the array substrate includes a plurality of thin film transistors, and the method includes: S1. preparing a base substrate on which sources and drains of the thin film transistors are formed; S2. forming an insulation layer on the base substrate such that the insulation layer includes spacer regions and a plurality of strip-shaped electrode regions, and every two adjacent strip-shaped electrode regions are separated from each other by the spacer region; S3. forming a spacer layer on the spacer regions of the insulation layer; S4. forming a pattern including strip-shaped electrodes on the strip-shaped electrode regions of the insulation layer; S5. peeling off the spacer layer on the spacer region. The invention can prevent every two adjacent strip-shaped electrodes from interconnecting due to etching residues, so as to improve product performance.

Abstract: A manufacturing method of an image sensor is provided. A substrate is provided, and the substrate includes a pixel array region. A plurality of openings is formed in the pixel array region of the substrate. A light guide region is formed in the substrate aside each of the openings, wherein a portion of the substrate is disposed between the light guide region and the opening, and the depth of the light guide region in the substrate is greater than the depth of the opening aside the light guide region in the substrate. Isolation structures are formed in the openings to define a plurality of pixel regions respectively located between two adjacent isolation structures in the pixel array region. A photosensitive region is formed in each of the pixel regions of the substrate. A conductive line layer is formed on each of the pixel regions of the substrate.

Abstract: A sensor is made up of two substrates which are adhered together. A first substrate includes a pressure-sensitive micro-electrical-mechanical (MEMS) structure and a conductive contact structure that protrudes outwardly beyond a first face of the first substrate. A second substrate includes a complementary metal oxide semiconductor (CMOS) device and a receiving structure made up of sidewalls that meet a conductive surface which is recessed from a first face of the second substrate. A conductive bonding material physically adheres the conductive contact structure to the conductive surface and electrically couples the MEMS structure to the CMOS device.

Abstract: An image capturing apparatus having pixels is provided. Each pixel includes a photoelectric conversion unit including a charge accumulation region, an output unit configured to output a signal based on a potential of a node electrically connected to the charge accumulation region, and a connection unit configured to electrically connect a capacitance to the node. The charge accumulation region includes a first portion and a second portion. Charge is configured to be first accumulated in the first portion, and, after the first portion is saturated, be accumulated in the second portion. The output unit is configured to output a first signal based on the potential of the node before the capacitance is connected thereto, and, then a second signal based on the potential of the node after the capacitance is connected thereto.

Abstract: The invention relates to a radiation detection device including a silicon substrate and an infrared photodiode made of a material optimized for infrared detection. The substrate comprises a photosensitive area, readout circuits, and interconnects formed in an electrically-insulating material. The interconnects and the metal contact connect the readout circuits, the photosensitive areas, and the infrared photodiode. The detection device also comprises an infrared radiation filtering structure which covers the photosensitive area without covering the infrared photodiode.

Abstract: A chip package with isolated pin, isolated pad or isolated chip carrier and a method of making the same are disclosed. In one embodiment a chip package includes a chip, a package encapsulating the chip, pads or pins disposed on a first side of the package and an isolation pad or an isolation pin disposed on a second side of the package, the isolation pin or the isolation pad electrically isolated from the chip, wherein the chip comprises a magnetic field sensor configured to measure a magnetic field generated outside of the package.

Abstract: Aspects of the present disclosure disclose a component module in a process condition measuring device comprises a support for supporting a component, one or more legs configured to suspend the support in a spaced-apart relationship with respect to a substrate. An electrically conductive or low-resistivity semiconductor enclosure is configured to enclose the component, the support and the legs between the substrate and the enclosure. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: Disclosed are a touch panel and a method of manufacturing the same. The touch panel includes a gas generation layer; a sensing electrode pattern on the gas generation layer; a gas blocking layer between the gas generation layer and the sensing electrode pattern to block a gas generated from the gas generation layer.

Abstract: A stacked photodiode structure comprises a first-conductivity-type substrate, a second-conductivity-type well region and a first-conductivity-type well region. The first-conductivity-type substrate has a first surface for light incidence and a grounding terminal. The second-conductivity-type well region is formed in the first-conductivity-type substrate and adjacent to the first surface. The first-conductivity-type well region is formed in the second-conductivity-type well region and adjacent to the first surface. A PN junction between the first-conductivity-type well region and the second-conductivity-type well region generates free electrons responsive to visible light spectrum. A PN junction between the second-conductivity-type well region and the first-conductivity-type substrate generates free holes and free electrons responsive to mainly IR light.

Abstract: Exemplary embodiments of the present invention relates to a light detection device including a substrate, a non-porous layer disposed on the substrate, a light absorption layer disposed on the non-porous layer, the light absorption layer including pores formed in a surface thereof, a Schottky layer disposed on the surface of the light absorption layer and in the pores, and a first electrode layer disposed on the Schottky layer.

Abstract: A solid-state imaging device with microlenses having a first lens layer and a second lens layer, the second lens layer being formed at least at a periphery of each microlens with either a portion of the second lens layer present at a central portion of each of the microlenses being thinner than a portion of the second lens layer present at the periphery of the microlens or no portion of the second lens layer being present at the central portion of each of the first microlenses. Between first pixel portions there is an interpixel gap, and the solid-state imaging device includes light blocking layers in alignment with the gaps.

Abstract: A lithographic process will use a mask or photomask. The photomask includes a first material layer, the first material layer providing a first outer surface of the photomask. The photomask also includes a second material layer over the first material layer, the second material layer providing a second outer surface of the photomask. The two outer surfaces are substantially in parallel and a distance between the two outer surfaces along a first axis perpendicular to the two outer surfaces defines a thickness of the photomask. Also, the two outer surfaces are connected by a plurality of sides, at least one of the sides is not perpendicular to the two outer surfaces and the at least one of the sides provides substantial area for holding the lithographic photomask.

Abstract: One embodiment of the invention describes a method for producing a luminescence conversion substance layer on a substrate with a semiconductor element that emits a primary radiation during operation. A composition includes a luminescence conversion substance, a matrix material and a solvent. The composition is applied to a substrate. At least part of the solvent is removed, with the result that the luminescence conversion substance layer is formed on the substrate.

Abstract: A monosilane compound or bissilane compound of a specific structure having dimethylamino groups is contained in a surface treatment agent used in the hydrophobization treatment of substrate surfaces.

Abstract: The present invention discloses a method for inhibiting the electric crosstalk of back illuminated CMOS image sensor. This invention comprises, two ion implanting layers are implanted at the different area of the backside of the pixel unit after the thickness of the backside of CMOS image sensor is reduced. The ion concentrations implanted into the two layers are controlled to decrease progressively from top to bottom. An electric field is formed from top to bottom inside the epitaxial layer. The said electric field absorbs the incident light which arrives at the substrate region outside of the space charge of the photodiode. It reduces the electron diffuses in different pixels. Consequently, it reduces the electric crosstalk of pixels, improves the manufacture process and improve the image quality of the of CMOS image sensor.

Abstract: A method of forming a package system includes providing a first substrate having a metallic pad and at least one metallic guard ring. The method further includes bonding the metallic pad of the first substrate with a semiconductor pad of a second substrate, wherein the at least one metallic guard ring is configured to at least partially interact with the semiconductor pad to form at least a first portion of an electrical bonding material between the first and second substrates.

Abstract: A method and a semiconductor device for incorporating defect mitigation structures are provided. The semiconductor device comprises a substrate, a defect mitigation structure comprising a combination of layers of doped or undoped group IV alloys and metal or non-metal nitrides disposed over the substrate, and a device active layer disposed over the defect mitigation structure. The defect mitigation structure is fabricated by depositing one or more defect mitigation layers comprising a substrate nucleation layer disposed over the substrate, a substrate intermediate layer disposed over the substrate nucleation layer, a substrate top layer disposed over the substrate intermediate layer, a device nucleation layer disposed over the substrate top layer, a device intermediate layer disposed over the device nucleation layer, and a device top layer disposed over the device intermediate layer.

Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a sacrificial layer over a first surface of a workpiece having the first surface and an opposite second surface. A membrane is formed over the sacrificial layer. A through hole is etched through the workpiece from the second surface to expose a surface of the sacrificial layer. At least a portion of the sacrificial layer is removed from the second surface to form a cavity under the membrane. The cavity is aligned with the membrane.

Abstract: A method for constructing a MEMS system includes first depositing on a surface of a substrate a first plurality of thin film layers formed of dielectric material. The first plurality of thin-film layers includes at least one conductive trace extending a distance on the substrate, parallel to the surface. A second plurality of layers is then deposited to form at least one MEMS device. The MEMS device is responsive to a control signal applied to a first input terminal and an electrical connection is formed from the conductive trace to the input terminal.

Abstract: A method of modulating an infrared headphone interface signal includes providing a first audio signal having an analog audio value. A memory is provided having a plurality of locations and containing digital phase offset values. A clock signal having a clock frequency is provided. A second audio signal having a center carrier frequency that deviates with the analog audio value of the first audio signal is provided. An instantaneous value of the center carrier frequency is determined. The clock frequency is divided by the instantaneous carrier frequency value to calculate a number of samples per cycle. A number of location addresses in the memory is divided by the number of samples per cycle to calculate a memory access interval. The memory is accessed at addresses separated by the memory access interval. The digital phase offset values at the accessed memory addresses are used to reproduce the first audio signal.

Abstract: A method of removing a plurality of semiconductor device layers from an underlying base substrate. A multilayered stack including alternating layers of sacrificial material layers and semiconductor material layers is formed on a base substrate. Each successive sacrificial material layer that is formed is thicker than the previously formed sacrificial material layer. An etch is then performed that first removes the thickest sacrificial material layer of the multilayered stack. The uppermost semiconductor device layer within the multilayered stack is accordingly first released. As the etch continues, the other sacrificial material layers are removed sequentially, in the order of decreasing thickness, and the other semiconductor device layers are removed sequentially.

Abstract: Micromachined ultrasonic transducers integrated with complementary metal oxide semiconductor (CMOS) substrates are described, as well as methods of fabricating such devices. Fabrication may involve two separate wafer bonding steps. Wafer bonding may be used to fabricate sealed cavities in a substrate. Wafer bonding may also be used to bond the substrate to another substrate, such as a CMOS wafer. At least the second wafer bonding may be performed at a low temperature.

Abstract: One method includes providing a first substrate; the first substrate may include a first MEMS device and a second MEMS device. A second substrate is also provided. The first substrate is bonded to the second substrate. The bonding may include forming a first bond ring around the first MEMS device and forming a second bond ring around the second MEMS device, wherein the second bond ring also encircles the first bond ring. In an embodiment, the eutectic point of the materials of the second bond ring is not reached during the bonding.

Abstract: According to embodiments of the invention, a TFT array substrate, a manufacturing method of the TFT array substrate and a display device are provided. The method comprises: depositing a metal film on a substrate, and forming a gate electrode and a gate line; forming a gate insulating layer and a passivation layer on the substrate; depositing a transparent conductive layer, a first source/drain metal layer and a first ohmic contact layer, and forming a drain electrode, a pixel electrode, a data line, and a first ohmic contact layer pattern provided on the drain electrode; and depositing a semiconductor layer, a second ohmic contact layer and a second source/drain metal layer, and forming a source electrode, a second ohmic contact layer pattern provided below the source electrode, and a semiconductor channel between the source electrode and the drain electrode.

Abstract: A method of producing semiconductor materials and devices that incorporate the semiconductor materials are provided. In particular, a method is provided of producing a semiconductor material, such as a III-V semiconductor, on a spinel substrate using a sacrificial buffer layer, and devices such as photovoltaic cells that incorporate the semiconductor materials. The sacrificial buffer material and semiconductor materials may be deposited using lattice-matching epitaxy or coincident site lattice-matching epitaxy, resulting in a close degree of lattice matching between the substrate material and deposited material for a wide variety of material compositions. The sacrificial buffer layer may be dissolved using an epitaxial liftoff technique in order to separate the semiconductor device from the spinel substrate, and the spinel substrate may be reused in the subsequent fabrication of other semiconductor devices.

Abstract: Method of manufacturing sinterable electrical components for jointly sintering with active components, the components in planar shape being provided with at least one planar lower face meant for sintering, and an electrical contact area on the face opposite to the sintering face being available in the form of a metallic contact face, whose upper side is contactable by means of a commonly known method of the group: wire bonding or soldering or sintering or pressure contacting, the component being a temperature sensor, whose lower face is provided with a sinterable metallization on a ceramic body, said ceramic body having two electrical contact faces for continued electrical connection.

Abstract: The invention discloses a method for fabricating power-generating module with solar cell. The method includes the steps of providing a flexible substrate; forming a solar cell unit on the flexible substrate by using a high density plasma at a temperature lower than about 150° C.; and forming a circuit unit on the flexible substrate; wherein the solar cell unit is coupled to the circuit unit, so as to provide the power needed for the operation of the circuit unit.

Abstract: The present disclosure provides a method including providing a first substrate; and forming a microelectromechanical system (MEMS) device on a first surface of the first substrate. A bond pad is formed on at least one bonding site on the first surface of the first substrate. The bonding site is recessed from the first surface. Thus, a top surface of the bond pad may lie below the plane of the top surface of the substrate. A device with recessed connective element(s) (e.g., bond pad) is also described. In further embodiments, a protective layer is formed on the recessed connective element during dicing of a substrate.

Abstract: A method (100; 100a; 100b; 100c) for manufacturing a solar cell from a semiconductor substrate (1) of a first conductivity type, the semiconductor substrate having a front surface (2) and a back surface (3). The method includes in a sequence: texturing (102) the front surface to create a textured front surface (2a); creating (103) by diffusion of a dopant of the first conductivity type a first conductivity-type doped layer (2c) in the textured front surface and a back surface field layer (4) of the first conductivity type in the back surface; removing (105; 104a) the first conductivity-type doped layer from the textured front surface by an etching process adapted for retaining texture of the textured front surface; creating (106) a layer of a second conductivity type (6) on the textured front surface by diffusion of a dopant of the second conductivity type into the textured front surface.

Abstract: A method for manufacturing a semiconductor device includes forming plural layers of a MTJ device, depositing a conductive layer over the plural layers, forming a hard mask pattern used for patterning the plural layers over the conductive layer, where the conductive layer is exposed through the hard mask pattern, performing hydrogen peroxide process to volatilize the exposed conductive layer and removing the volatilized conductive layer, and patterning the plural layers by using the hard mask pattern as an etch mask to form the MTJ device.

Abstract: The semiconductor device has a sensor unit including a sensing part, and a semiconductor substrate. The semiconductor substrate is bonded to the sensor unit through an insulation film such that the sensing part is disposed in an air-tightly sealed chamber provided between a recessed portion of the semiconductor substrate and the sensor unit. A surface of the semiconductor substrate provided on a periphery of the recessed portion includes a boundary region at a perimeter of the recessed portion and a bonding region on a periphery of the boundary region. The bonding region has an area greater than an area of the boundary region. The bonding region of the semiconductor substrate is bonded to the sensor unit through the insulation film.

Abstract: A magnetic tunnel junction (MTJ) device is formed by a process that includes forming a trench in a substrate and depositing an MTJ structure within the trench. The MTJ structure includes a bottom electrode, a fixed layer, a tunnel barrier layer, a free layer, and a top electrode. The process includes applying reverse photo etching to remove material that is not directly over the trench. The process also includes plagiarizing the MTJ structure without performing a photo-etch process on the MTJ structure.

Abstract: The present disclosure provides a biological field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET includes a microwells having a sensing layer, a top metal stack under the sensing layer, and a multi-layer interconnect (MLI) under the top metal stack. The top metal stack includes a top metal and a protective layer over and peripherally surrounding the top metal.

Abstract: Provided is a solid-state imaging device including: a photodiode which converts an optical signal to signal charges; a transfer gate which transfers the signal charges from the photodiode; an impurity diffusion layer to which the signal charges are transferred by the transfer gate; and a MOS transistor of which a gate is connected to the impurity diffusion layer. The impurity diffusion layer has a first conduction type semiconductor layer and a second conduction type semiconductor layer which is formed in the first conduction type semiconductor layer and under an end portion of the transfer gate.

Abstract: A process for encapsulating a microelectronic device, comprising the following steps: make the microelectronic device on a first substrate; make one portion of a first material not permeable to the ambient atmosphere and permeable to a noble gas in a second substrate comprising a second material not permeable to the ambient atmosphere and the noble gas; secure the second substrate to the first substrate, forming at least one cavity inside which the microelectronic device is encapsulated such that said portion of the first material forms part of a wall of the cavity; inject the noble gas into the cavity through the portion of the first material; hermetically seal the cavity towards the ambient atmosphere and the noble gas.

Abstract: A magnetic sensor and a manufacturing method thereof are provided. The magnetic sensor includes: a substrate comprising a plurality of Hall elements, a protective layer formed on the substrate, a base layer formed on the protective layer, and an integrated magnetic concentrator (IMC) formed on the base layer and comprising a surface with an elevated portion. The base layer has a larger cross-sectional area than the IMC.

Abstract: Described is a personal device and methods for measuring the concentration of an analyte in a sample of gas. The device and method may utilize a chemically selective sensor element with low power consumption integrated with circuitry that enables wireless communication between the sensor and any suitable electronic readout such as a smartphone, tablet, or computer. In preferred form, the sensor circuitry relies upon the quantum capacitance effect of graphene as a transduction mechanism. Also in preferred form, the device and method employ the functionalization of the graphene-based sensor to determine the concentration of ethanol in exhaled breath.

Abstract: An organic light-emitting display apparatus includes a buffer layer that is on a substrate and includes nanoparticles including nickel (Ni), a pixel electrode on the buffer layer, an organic emission layer on the pixel electrode, and an opposite electrode on the organic emission layer. A method of manufacturing the organic light-emitting display apparatus is provided.

Abstract: The threshold voltage is shifted in a negative or positive direction in some cases by an unspecified factor in a manufacturing process of the thin film transistor. If the amount of shift from 0 V is large, driving voltage is increased, which results in an increase in power consumption of a semiconductor device. Thus, a resin layer having good flatness is formed as a first protective insulating film covering the oxide semiconductor layer, and then a second protective insulating film is formed by a sputtering method or a plasma CVD method under a low power condition over the resin layer. Further, in order to adjust the threshold voltage to a desired value, gate electrodes are provided over and below an oxide semiconductor layer.

Abstract: The objective of the present invention is to provide a fingerprint sensor package having a novel structure and a method for manufacturing same, the fingerprint sensor package enabled with obtaining an accurate fingerprint image by minimizing the distance between a top surface of a sensing portion in a fingerprint sensor and a fingerprint, so as to improve mechanical strength and tolerance to electrostatic discharge compared to existing fingerprint sensor packages.

Abstract: This document refers to apparatus and methods for a device layer of a microelectromechanical system (MEMS) sensor having vias with reduced shunt capacitance. In an example, a device layer can include a substrate having a pair of trenches separated in a horizontal direction by a portion of the substrate, wherein each trench of the pair of trenches includes first and second vertical layers including dielectric, the first and second vertical layers separated by a third vertical layer including polysilicon.

Abstract: An organic ambipolar light emitting field effect transistor having an architecture with layers stacked one over the other, adapted to generate a diffused illumination is described.

Abstract: A high-voltage MEMS system compatible with low-voltage semiconductor process technology is disclosed. The system comprises a MEMS device coupled to a high-voltage bias generator employing an extended-voltage isolation residing in a semiconductor technology substrate. The system avoids the use of high-voltage transistors so that special high-voltage processing steps are not required of the semiconductor technology, thereby reducing process cost and complexity. MEMS testing capability is addressed with a self-test circuit allowing modulation of the bias voltage and current so that a need for external high-voltage connections and associated electro-static discharge protection circuitry are also avoided.

Abstract: According to one embodiment, a strain sensor includes a substrate, a lid, a frame, and a sensing unit. The substrate has a first surface. The lid is provided on the first surface. The frame is provided between the substrate and the lid. The frame is nonconductive and includes a magnetic body. The sensing unit is provided inside the frame between the substrate and the lid, and includes a magnetoresistance effect element.