Abstract: A method of applying a pattern of metal, metal oxide, and/or semiconductor material on a substrate, a pattern created by that method, and uses of that pattern.

Abstract: Integrated Circuits and methods for reducing thermal neutron soft error rate (SER) of a digital circuit are provided by doping a protection layer on top of the metal layer and in physical contact with the metal layer of the digital circuit, wherein the protection layer is doped with additional thermal neutron absorbing material. The thermal neutron absorbing material can be selected from the group consisting of Gd, Sm, Cd, B, and combinations thereof. The protection layer may comprise a plurality of sub-layers among which a plurality of them containing additional thermal neutron absorbing material.

Abstract: Example embodiments relate to a heterojunction diode, a method of manufacturing the heterojunction diode, and an electronic device including the heterojunction diode. The heterojunction diode may include a first conductive type non-oxide layer and a second conductive type oxide layer bonded to the non-oxide layer. The non-oxide layer may be a Si layer. The Si layer may be a p++ Si layer or an n++ Si layer. A difference in work functions of the non-oxide layer and the oxide layer may be about 0.8-1.2 eV. Accordingly, when a forward voltage is applied to the heterojunction diode, rectification may occur. The heterojunction diode may be applied to an electronic device, e.g., a memory device.

Abstract: By providing a protective layer in an intermediate manufacturing stage, an increased surface protection with respect to particle contamination and surface corrosion may be achieved. In some illustrative embodiments, the protective layer may be used during an electrical test procedure, in which respective contact portions are contacted through the protective layer, thereby significantly reducing particle contamination during a respective measurement process.

Abstract: A non-volatile bistable nano-electromechanical switch is provided for use in memory devices and microprocessors. The switch employs carbon nanotubes as the actuation element. A method has been developed for fabricating nanoswitches having one single-walled carbon nanotube as the actuator. The actuation of two different states can be achieved using the same low voltage for each state.

Abstract: A simplified method for fabricating a solar cell device is provided. The solar cell device has silicon nanowires (SiNW) grown on an upgraded metallurgical grade (UMG) silicon (Si) substrate. Processes of textured surface process and anti-reflection thin film process can be left out for further saving costs on equipment and manufacture investment. Thus, a low-cost Si-based solar cell device can be easily fabricated for wide application.

Abstract: The thermal energy transfer techniques of the disclosed embodiments utilize passive thermal energy transfer techniques to reduce undesirable side effects of trapped thermal energy at the circuit level. The trapped thermal energy may be transferred through the circuit with thermally conductive structures or elements that may be produced as part of a standard integrated circuit process. The localized and passive removal of thermal energy achieved at the circuit level rather just at the package level is both more effective and more efficient.

Abstract: A thermal path is formed in a layer transferred semiconductor structure. The layer transferred semiconductor structure has a semiconductor wafer and a handle wafer bonded to a top side of the semiconductor wafer. The semiconductor wafer has an active device layer formed therein. The thermal path is in contact with the active device layer within the semiconductor wafer. In some embodiments, the thermal path extends from the active device layer to a substrate layer of the handle wafer. In some embodiments, the thermal path extends from the active device layer to a back side external thermal contact below the active device layer.

Abstract: A hot filament chemical vapor deposition method has been developed to grow at least one vertical single-walled carbon nanotube (SWNT). In general, various embodiments of the present invention disclose novel processes for growing and/or producing enhanced nanotube carpets with decreased diameters as compared to the prior art.

Abstract: An electronic device and method of manufacturing the device. The device includes a semiconducting region, which can be a nanowire, a first contact electrically coupled to the semiconducting region, and at least one second contact capacitively coupled to the semiconducting region. At least a portion of the semiconducting region between the first contact and the second contact is covered with a dipole layer. The dipole layer can act as a local gate on the semiconducting region to enhance the electric properties of the device.

Abstract: A method includes providing a semiconductor substrate having a gate trench and depositing a metal layer, using a physical vapor deposition (PVD) process, over the substrate to partially fill the trench. The metal layer includes a bottom portion and a sidewall portion that is thinner than the bottom portion. The method also includes forming a coating layer on the metal layer, etching back the coating layer such that a portion of the coating layer protects a portion of the metal layer within the trench, and removing the unprotected portion of the metal layer. A different aspect involves a semiconductor device that includes a gate that includes a trench having a top surface, and a metal layer formed over the trench, wherein the metal layer includes a sidewall portion and a bottom portion, and wherein the sidewall portion is thinner than the bottom portion.

Abstract: A method of joining a flexible layer and a support includes forming a first metal layer on one surface of the flexible layer, forming a second metal layer on one surface of the support, cleaning the first metal layer and the second metal layer, and joining the first metal layer to the second metal layer, such that the first metal layer is between the flexible layer and the second metal layer.

Abstract: Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a plurality of vias through the substrate from an opposing surface of the substrate to the layer of conductive material. In some embodiments, a temporary carrier may be secured to the layer of conductive material on a side thereof opposite the substrate prior to forming the vias. Structures, including workpieces formed using such methods, are also disclosed.

Abstract: Methods for forming nanodots and/or a patterned material are provided. One such method involves forming a first patterning material over a base. Blades of a nanoimprint lithography template are placed within the first patterning material, wherein the blades extend along the base in a first direction. With the blades within the first patterning material, the first patterning material are cured. The blades are removed from the first patterning material to form a patterned first patterning material. The base is etched using the patterned first patterning material as a pattern to form openings in the base. The patterned first patterning material is removed from the base. A second patterning material is formed over the base and within the openings in the base. Blades of a nanoimprint lithography template are placed within the second patterning material, wherein the blades extend along the base in a second direction, which is generally perpendicular with respect to the first direction.

Abstract: Provided are beam ablation lithography methods capable of removing and manipulating material at the nanoscale. Also provided are nanoscale devices, nanogap field effect transistors, nano-wires, nano-crystals and artificial atoms made using the disclosed methods.

Abstract: There is disclosed a wafer processing apparatus having optimized electrode patterns for its resistive heating element. The optimized electrode pattern is designed to compensate for the heat loss around contact areas, electrical connections, and through-holes, etc., by generating more heat near or around those areas, providing maximum temperature uniformity. In another embodiment of the optimized design of the invention, the resistance of heating element closely matches the impedance of the power supply for higher efficiency, especially when higher operating temperature or higher electrical power is required.

Abstract: A semiconductor switch device and a method of manufacturing the semiconductor switch device are provided. The semiconductor switch device includes semiconductor elements on a single semiconductor substrate. At least one of the semiconductor elements constitutes a switch circuit and at least one other of the semiconductor elements constitutes a logic (connection) circuit. Each semiconductor element includes a recess, a gate electrode in the recess, a drain electrode, and a source electrode. In one representative aspect, the gate electrode in the switch circuit can have a rectangular external shape in section, and the gate electrode in the connection circuit has a shape in section other than rectangular.

Abstract: Provided are a wire structure, a method for fabricating a wire, a thin film transistor (TFT) substrate, and a method for fabricating a TFT substrate.

Abstract: Provided is a method of planarizing a semiconductor device. The method includes providing a substrate. The method includes forming a first layer over the substrate. The method includes forming a second layer over the first layer. The first and second layers have different material compositions. The method includes forming a third layer over the second layer. The method includes performing a polishing process on the third layer until the third layer is substantially removed. The method includes performing an etch back process to remove the second layer and a portion of the first layer. Wherein an etching selectivity of the etch back process with respect to the first and second layers is approximately 1:1.

Abstract: A semiconductor device manufacture method includes: forming a first film above a semiconductor substrate; forming a first mask film above the first film; patterning the first mask film; executing a plasma process for a side wall of the patterned first mask film to transform the side wall into a transformed layer; after the plasma process, forming a second mask film covering the first mask film; etching the second mask film to remove the second mask film above the first mask film and leave the second mask film formed on the side wall; after the etching the second mask film, removing the transformed layer; and after the removing the transformed layer, etching the first film by using the first mask film and the second mask film as mask.

Abstract: Some embodiments include methods of forming diodes. A stack may be formed over a first conductive material. The stack may include, in ascending order, a sacrificial material, at least one dielectric material, and a second conductive material. Spacers may be formed along opposing sidewalls of the stack, and then an entirety of the sacrificial material may be removed to leave a gap between the first conductive material and the at least one dielectric material. In some embodiments of forming diodes, a layer may be formed over a first conductive material, with the layer containing supports interspersed in sacrificial material. At least one dielectric material may be formed over the layer, and a second conductive material may be formed over the at least one dielectric material. An entirety of the sacrificial material may then be removed.

Abstract: A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.

Abstract: A backplane having a circuit array having at least one region comprising a substrate having a conductive plane under a dielectric surface, a first conductive layer on said dielectric surface, a selectively disposed insulator disposed over said first conductive layer, and a second conductive layer disposed on said insulator, wherein said first conductive layer is electrically insulated from said second conductive layer, said first conductive layer being formed electrographically, and said second conductive layer being formed by a process comprising selective deposition of liquid droplets, which are then solidified. The second conductive layer may be formed electrographically or by a raster deposition process. The backplane preferably forms an active matrix for a flat panel display using organic semiconductor active elements.

Abstract: Methods for forming a dense dielectric layer over the surface of an opening in a porous inter-layer dielectric having an ultra-low dielectric constant are disclosed. The disclosure provides methods for exposing the sidewall surface and the bottom surface of the opening to a plurality of substantially parallel ultra-violet (UV) radiation rays to form a dense dielectric layer having a substantially uniform thickness over both the sidewall surface and the bottom surface.

Abstract: A hybrid multilayer substrate in an electronic package. The substrate includes a first portion having m layers and a second portion having n layers such that m is less than n. The first portion has a first height and the second portion has a second height. The first height is different than the second height. In another embodiment, a surface is formed between the first portion and the second portion, and a shielding material can be applied to the surface. In a different embodiment, the hybrid multilayer substrate is manufactured for shielding a first die from a second die.

Abstract: In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the exposed portions of the sidewall spacers may be selectively removed. Finally, the lower portion of the stack may be removed to form a T-shaped trench which may be filled with the metal replacement.

Abstract: Implementations of encapsulated nanowires are disclosed.

Abstract: A method for producing an electrically-conductive inorganic coating includes depositing, on a substrate, a coating-precursor containing a plurality of inorganic particles and at least one kind of organic component by a liquid-phase method by using a material-liquid containing the inorganic particles and an organic solvent. The inorganic particles are coated with a dispersant binding to the surfaces of the inorganic particles by chemical bonds that can be broken by oxidation. Further, the method includes oxidizing the coating-precursor at a temperature exceeding 100° C., and that is less than or equal to the pyrolysis initiation temperature of an organic component that has the highest pyrolysis initiation temperature among the at least one kind of organic component and less than or equal to the heat-resistance temperature of the substrate, thereby breaking the chemical bonds to eliminate the dispersant from the surfaces, and decomposing the at least one kind of organic component.

Abstract: A method for high resolution ink-jet print using a pre-patterned substrate employs an ink-jet printing device including an ink-jet head for discharging conductive ink droplets and a driving stage for supporting a substrate to which the conductive ink droplets are hit, to draw a fine line width pattern on the substrate. The method includes (A) forming a stripe pattern with repeated stripes on a substrate surface on which a fine line width pattern will be formed, thereby preparing a pre-patterned substrate; (B) loading the substrate to the ink-jet printing device; and (C) injecting conductive ink droplets to a substrate region where the stripe pattern is formed. An equivalent interval (d) of the stripe pattern and a fine line width (D) of the drawn fine line width pattern satisfy a relation of d<<D, and the hit ink droplets are flowed in an anisotropic form within the region.

Abstract: An image display system and manufacturing method are disclosed. According to the present invention, the image display system comprises a substrate, a switching TFT, a driving TFT, a photo sensor and a capacitor. A buffer layer is formed on a substrate. A separation layer is formed in a first area for forming a switching TFT, but no heat sink layer is formed thereon. A heat sink layer is formed on a second area for forming the driving TFT, the photo sensor and the capacitor, and then, the separation layer is formed thereafter. The present invention can form poly silicon layers with different crystal grain sizes on the first area and on the second area in a single laser crystallization process by utilizing the heat sink phenomenon of ELA with or without the heat sink layer. Therefore, the image display system of the present invention can operate with good luminance uniformity.

Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface-electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.

Abstract: An apparatus comprises a first layer within a semiconductor chip having active structures electrically connected to other active structures and having electrically isolated first inactive structures. A second layer within the semiconductor chip is physically connected to the first layer. The second layer comprises an insulator and has second inactive structures. The first inactive structures are physically aligned with the second inactive structures.

Abstract: The present invention describes a method of fabrication of nanocomposite semiconductor materials comprising aligned arrays of metal or semiconductor nanowires incorporated into semiconductor material for application in various electronic, optoelectronic, photonic and plasmonic devices employing self-assembling of the nanowires under light illumination from charged interstitial defect atoms, which are either inherently present in the semiconductor material or artificially introduced in the matrix semiconductor material.

Abstract: The described embodiments of methods of bottom-up metal deposition to fill interconnect and replacement gate structures enable gap-filling of fine features with high aspect ratios without voids and provide metal films with good film quality. In-situ pretreatment of metal film(s) deposited by gas cluster ion beam (GCIB) allows removal of surface impurities and surface oxide to improve adhesion between an underlying layer with the deposited metal film(s). Metal films deposited by photo-induced chemical vapor deposition (PI-CVD) using high energy of low-frequency light source(s) at relatively low temperature exhibit liquid-like nature, which allows the metal films to fill fine feature from bottom up. The post deposition annealing of metal film(s) deposited by PI-CVD densifies the metal film(s) and removes residual gaseous species from the metal film(s). For advanced manufacturing, such bottom-up metal deposition methods address the challenges of gap-filling of fine features with high aspect ratios.

Abstract: The present invention relates to growth of III-V semiconductor nanowires (2) on a Si substrate (3). Controlled vertical nanowire growth is achieved by a step, to be taken prior of the growing of the nanowire, of providing group III or group V atoms to a (111) surface of the Si substrate to provide a group III or group V 5 surface termination (4). A nanostructured device comprising a plurality of aligned III-V semiconductor nanowires (2) grown on, and protruding from, a (111) surface of a Si substrate (3) in an ordered pattern in compliance with a predetermined device layout is also presented.

Abstract: In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film.

Abstract: Embodiments of a method for assembling a multi-chip module (MCM) are described. During this method, a fluid that includes coupling elements is applied to a surface of a base plate in the MCM. Then, at least some of the coupling elements are positioned into negative features on the surface of the base plate using fluidic assembly. Note that a given coupling element selects a given negative feature using chemical-based selection and/or geometry-based selection. Next, the fluid and excess coupling elements (which reside in regions outside of the negative features on the surface) are removed.

Abstract: A thermal interface member includes a bulk layer and a surface layer that is disposed on at least a portion of a surface of the bulk layer. The surface layer is highly thermally conductive, has a melting point exceeding a solder reflow temperature, and has a maximum cross-sectional thickness of less than about 10 microns.

Abstract: A method of crystallizing a silicon layer and a method of manufacturing a thin film transistor using the same, the method of crystallizing the silicon layer including forming an amorphous silicon layer on a substrate; performing a hydrophobicity treatment on a surface of the amorphous silicon layer so as to obtain a hydrophobic surface thereon; forming a metallic catalyst on the amorphous silicon layer that has been subjected to the hydrophobicity treatment; and heat-treating the amorphous silicon layer including the metallic catalyst thereon to crystallize the amorphous silicon layer into a polycrystalline silicon layer.

Abstract: Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a more nonlinear, asymmetric I-V curve and enhanced rectifying behavior in the select devices. The select devices may comprise, for example, a metal-insulator-insulator-metal (MIIM) diode. Various methods may be used to form select devices and memory systems including such select devices. Memory devices and electronic systems include such select devices.

Abstract: A manufacturing method for a silicon carbide semiconductor device is disclosed. It includes an etching method in which an Al film and Ni film are laid on an SiC wafer in this order and wet-etched, whereby a two-layer etching mask is formed in which Ni film portions overhang Al film portions. Mesa grooves are formed by dry etching by using this etching mask.

Abstract: A compound semiconductor device is provided, including a gallium arsenide (GaAs) substrate having a first protrusion portion and a second protrusion portion, wherein the first protrusion portion is formed over a first portion of the GaAs substrate and the second protrusion is formed over a second portion of the GaAs substrate. A first element is disposed over the first protrusion portion, and a second element is disposed over the second protrusion portion.

Abstract: The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement. The volume element is being doped in order to provide a high charge carrier injection into the nanoelement and a low access resistance in an electrical connection. The nanoelement may be upstanding from a semiconductor substrate. A concentric layer of low resistivity material forms on the volume element forms a contact.

Abstract: A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK1+TK2; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.

Abstract: A method of assembling a bent circuit chip package and a circuit chip package having a bent structure. The circuit chip package includes: a substrate having a first coefficient of thermal expansion (CTE); a circuit chip, having a second CTE, mounted onto the substrate; a metal foil disposed on the circuit chip in thermal contact with the chip; a metal lid having (i) a third CTE that is different from the first CTE and (ii) a bottom edge region, where the metal lid is disposed on the metal foil in thermal contact with the metal foil; and an adhesive layer along the bottom edge of the metal lid, cured at a first temperature, bonding the lid to the substrate, producing an assembly which, at a second temperature, is transformed to a bent circuit chip package.

Abstract: A method and mesh reference applications are provided for implementing Z-axis cross-talk reduction. A mesh reference plane including a grid of mesh traces is formed with the mesh traces having selected thickness and width dimensions effective for reference current-flow distribution. An electrically conductive coating is deposited to fill the mesh electrical holes in the mesh reference plane to reduce cross-talk, substantially without affecting mechanical flexibility.

Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.

Abstract: A chemical bath deposition (CBD) process is provided for forming a textured zinc oxide film pattern from a zinc oxide printed seed layer. The process provides a substrate and prints a zinc oxide seed layer in a pattern overlying the substrate. Using a CBD process, a textured zinc oxide film is grown overlying the zinc oxide seed layer pattern, where the textured zinc oxide film has a variation in film thickness of greater than 200 nanometers (nm). In one aspect, growing the textured zinc oxide film includes: preparing a ZnO precursor bath; maintaining a bath temperature of about 70 degrees C.; and, leaving the substrate in the bath for about an hour. In another aspect, growing the textured zinc oxide film includes forming a textured zinc oxide film with zinc oxide crystals having a pyramidal shape with a height of greater than 200 nm.

Abstract: Provided is an electrode patterning layer used for forming an electrode pattern of any optional shape depending on the difference in wettability with an electrode-forming solution, the electrode patterning layer employing a polyimide type resin which is highly reliable as an electronic material. The electrode patterning layer is prepared by irradiating a layer comprising a polyamic acid having repeating units at the formula (1) or a polyimide obtainable by cyclodehydration of such a polyamic acid, with ultraviolet ray in a pattern shape: wherein A is a tetravalent organic group, B is a bivalent organic group, each of A and B may be of a single type or plural types, and n is a positive integer, provided that at least one type of A is a tetravalent organic group having an alicyclic structure.

Abstract: Functionalized nanoparticles are deposited on metal lines inlaid in dielectric to form a metal cap layer that reduces electromigration in the metal line. The functionalized nanoparticles are deposited onto activated metal surfaces, then sintered and annealed to remove the functional agents leaving behind a continuous capping layer. The resulting cap layer is about 1 to 10 nm thick with 30-100% atomic of the nanoparticle material. Various semiconductor processing tools may be adapted for this deposition process without adding footprint in the semiconductor fabrication plant.