Abstract: The present invention relates to a process for producing a carbon nanotube (CNT) mat on a conductive or semiconductor substrate. According to this process, a catalytic complex comprising at least one metal layer is firstly deposited on said substrate. Said metal layer then undergoes an oxidizing treatment. Finally, carbon nanotubes are grown from the metal layer thus oxidized. The present invention also relates to a process for producing a via using said CNT mat production process.

Abstract: Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.

Abstract: A method for fabricating an integrated device is disclosed. A polysilicon gate electrode layer is provided on a substrate. In an embodiment, a treatment is provided on the polysilicon gate electrode layer to introduce species in the gate electrode layer and form an electrically neutralized portion therein. Then, a hard mask layer with limited thickness is applied on the treated polysilicon gate electrode layer. A tilt angle ion implantation is thus performing on the substrate after patterning the hard mask layer and the treated polysilicon gate electrode to from a gate structure.

Abstract: A chip identification for organic laminate packaging and methods of manufacture is provided. The method includes forming a material on a wafer which comprises a plurality of chips. The method further includes modifying the material to provide a unique identification for each of the plurality of chips on the wafer. The organic laminate structure includes a chip with a device and a material placed on the chip which is modified to have a unique identification mark for the chip.

Abstract: A substrate, the presence of which can be detected with a method similar to a conventional method of detecting a Si substrate even if the substrate is transparent, and a method of manufacturing the substrate are provided. Light incident on an end portion of a transparent substrate is not transmitted through the substrate as with the light incident on a central portion of the substrate, but is totally reflected from a total reflection surface in a detection region present in at least a portion of the end portion of the substrate. A photoelectric sensor can recognize that a ratio of transmission of the light at the end portion of the substrate has become smaller, thereby detecting the presence of the substrate.

Abstract: A method is provided for producing semiconductor nanoparticles comprising: (i) dissolving a semiconductor compound or mixture of semiconductor compounds in a solution; (ii) generating spray droplets of the resulting solution of semiconductor compound(s); (iii) vaporizing the solvent of said spray droplets, consequently producing a stream of unsupported semiconductor nanoparticles; and (iv) collecting said unsupported semiconductor nanoparticles on a support.

Abstract: A layer-stacked wiring made up of a microcrystalline silicon thin film and a metal thin film is provided which is capable of suppressing an excessive silicide formation reaction between the microcrystalline silicon thin film and metal thin film, thereby preventing peeling of the thin film. In a polycrystalline silicon TFT (Thin Film Transistor) using the layer-stacked wiring, the microcrystalline silicon thin film is so configured that its crystal grains each having a length of the microcrystalline silicon thin film in a direction of a film thickness being 60% or more of a film thickness of the microcrystalline silicon thin film amount to 15% or less of total number of crystal grains or that its crystal grains each having a length of the microcrystalline silicon thin film in a direction of a film thickness being 50% or less of a film thickness of the microcrystalline silicon thin film amount to 85% or more of the total number of crystal grains making up the microcrystalline silicon thin film.

Abstract: A dual zone plasma processing chamber is provided. The plasma processing chamber includes a first substrate support having a first support surface adapted to support a first substrate within the processing chamber and a second substrate support having a second support surface adapted to support a second substrate within the processing chamber. One or more gas sources in fluid communication with one or more gas distribution members supply process gas to a first zone adjacent to the first substrate support and a second zone adjacent to the second substrate support. A radio-frequency (RF) antenna adapted to inductively couple RF energy into the interior of the processing chamber and energize the process gas into a plasma state in the first and second zones. The antenna is located between the first substrate support and the second substrate support.

Abstract: The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes.

Abstract: A circuit element is disposed on an organic substrate and is connected to a wiring pattern provided on the organic substrate. Internal connection electrodes are formed on a support of a conductive material through electroforming such that the internal connection electrodes are integrally connected to the support. First ends of the internal connection electrodes integrally connected by the support are connected to the wiring pattern. After the circuit element is resin-sealed, the support is removed so as to separate the internal connection electrodes from one another. Second ends of the internal connection electrodes are used as external connection electrodes on the front face, and external connection electrodes on the back face are connected to the wiring pattern.

Abstract: A transistor with a gate stack having a metal electrode and a method for forming the same. The method includes providing a structure which includes (a) a substrate, (b) a gate dielectric layer on the substrate, and (c) a gate layer on the gate dielectric layer. The gate layer includes an oxidized layer. The oxidized layer comprises an oxidized material. Then, the structure is exposed to a first plasma resulting in removal of oxygen atoms from molecules of the oxidized material.

Abstract: Disclosed herein is a method for forming a dual gate of a semiconductor device. The method comprises the steps of forming a first polysilicon layer doped with p-type impurity ions and a second polysilicon layer doped with n-type impurity ions on a first region and a second region of a semiconductor substrate, respectively, and sequentially subjecting the surfaces of the first and second polysilicon layers to wet cleaning, drying, and dry cleaning. The wet cleaning is performed by using a sulfuric acid peroxide mixture (SPM), a buffered oxide etchant (BOE), and Standard Clean-1 (SC-1) as cleaning solutions.

Abstract: Disclosed herein is a method for forming a dual gate of a semiconductor device. The method comprises the steps of forming a first polysilicon layer doped with p-type impurity ions and a second polysilicon layer doped with n-type impurity ions on a first region and a second region of a semiconductor substrate, respectively, and sequentially subjecting the surfaces of the first and second polysilicon layers to wet cleaning, drying, and dry cleaning. The wet cleaning is performed by using a sulfuric acid peroxide mixture (SPM), a buffered oxide etchant (BOE), and Standard Clean-1 (SC-1) as cleaning solutions.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a first active area, and a second transistor having a second active area. A top surface of the first active area is elevated or recessed with respect to a top surface of the second active area, or a top surface of the first active area is elevated or recessed with respect to a top surface of at least portions of an isolation region proximate the first transistor.

Abstract: Gate spacers are formed in FinFETS having a bottom portion of a first material extending to the height of the fins, and a top portion of a second material extending above the fins. An embodiment includes forming a fin structure on a substrate, the fin structure having a height and having a top surface and side surfaces, forming a gate substantially perpendicular to the fin structure over a portion of the top and side surfaces, for example over a center portion, forming a planarizing layer over the gate, the fin structure, and the substrate, removing the planarizing layer from the substrate, gate, and fin structure down to the height of the fin structure, and forming spacers on the fin structure and on the planarizing layer, adjacent the gate.

Abstract: This invention describes a method of making solar cells wherein the efficiency of the solar cell is enhanced by defining a diffraction grating either on top of the cell or at the bottom of the cell. The diffraction grating spacing is defined such that it bends one or more wavelengths of the incident radiation thereby making those wavelengths traverse in the direction of the plane of the device. The addition of a diffraction grating is done in conjunction with thinning down the cell such that the minority carriers generated (holes and electrons) have a higher probability of being collected. The combined effect of the diffraction grating and the reduced thickness in the solar cell increases the efficiency of the solar cell.

Abstract: The invention relates to a resonance filter (1) made of silicon for use in the micrometer and millimeter wave length range. Accordingly, a resonance filter having low loss and a high Q-factor is provided, comprising two layers. A first layer thereof carries only resonance cavities and a second layer carries only coupling cavities. Furthermore, a method for the production of the filter according to the invention is provided. This enables the cost-effective production of the resonance filter by means of KOH or TMAH etching technology.

Abstract: A programmable resistance, chalcogenide, switching or phase-change material device includes a substrate with a plurality of stacked layers including a conducting bottom electrode layer, an insulative layer having an opening formed therein, an active material layer deposited over both the insulative layer, within the opening, and over selected portions of the bottom electrode, and a top electrode layer deposited over the active material layer. The device uses temperature and pressure control methods to increase surface mobility in an active material layer, thus providing complete coverage or fill of the openings in the insulative layer, selected exposed portions of the bottom electrode layer, and the insulative layer.

Abstract: An object is to provide a method for manufacturing a light-emitting device with high definition, high light-emitting characteristics, and the long lifetime by employing a method in which a desired evaporation pattern can be formed and an excess evaporation of a material layer which is to be the transfer layer is prevented and in which deterioration of the material or the like is hard to occur in a transfer step. This is a method for manufacturing a light-emitting device, in which irradiation with first light is performed to pattern a material layer over a first substrate which is an evaporation donor substrate and irradiation with second light is performed to evaporate the material layer patterned onto a second substrate which is a deposition target substrate.

Abstract: A method for encapsulating a micro component positioned on and/or in a substrate, including the following steps: depositing at least one sacrificial material covering the micro component, making a cap covering the sacrificial material, removing the sacrificial material via at least one opening formed through the cap, forming a cavity in which the micro component is positioned, depositing, on the cap, at least one layer of plugging material capable of plugging the opening, localized deposition of a portion of mechanically reinforcing material of the cap, covering at least the cap.

Abstract: Methods are disclosed for activating dopants in a doped semiconductor substrate. A carbon precursor is flowed into a substrate processing chamber within which the doped semiconductor substrate is disposed. A plasma is formed from the carbon precursor in the substrate processing chamber. A carbon film is deposited over the substrate with the plasma. A temperature of the substrate is maintained while depositing the carbon film less than 500° C. The deposited carbon film is exposed to electromagnetic radiation for a period less than 10 ms, and has an extinction coefficient greater than 0.3 at a wavelength comprised by the electromagnetic radiation.

Abstract: A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and prior to the joining thereto of a substrate during the fabrication of an electronic package. The methods entail either treating the backside with a wet etch, or alternatively, applying a protective film layer thereon prior to forming an electronic package incorporating the chip or wafer.

Abstract: After etching a polysilicon film, when a protective film made of a carbon polymer is formed on a sidewall of the polysilicon film using plasma containing carbons, a metallic material as a lower film is etched using plasma containing a halogen gas under an etching condition in which volatility is improved due to the rise in a wafer temperature or the low pressure of a processing pressure, thereby preventing a side etching and unevenness of a sidewall of the polysilicon film. Further, by using the protective film made of a carbon polymer, metallic substances scattered at the time of etching the metallic material are not directly attached to the polysilicon film, but can be simply removed along with the protective film made of a carbon polymer in an asking step.

Abstract: An area where a lower electrode is in contact with a variable resistance material needs to be reduced to lower the power consumption of a variable resistance memory device. The present invention is to provide a method of producing a variable resistance memory element whereby the lower electrode can be formed smaller. Combining an anisotropic etching process with an isotropic etching process enables the lower electrode to be formed smaller.

Abstract: The invention relates to a semiconductor device manufactured in a process technology, the semiconductor device having at least one wire located in an interconnect layer of said semiconductor device, the at least one wire having a wire width (W) and a wire thickness (T), the wire width (W) being equal to a minimum feature size of the interconnect layer as defined by said process technology, wherein the minimum feature size is smaller than or equal to 0.32 ?m, wherein the aspect ratio (AR) of the at least one wire is smaller than 1.5, the aspect ratio (AR) being defined as the wire thickness (T) divided by the wire width (W). The invention further discloses a method of manufacturing such a semiconductor device.

Abstract: A heat processing apparatus includes a heating plate configured to heat the substrate; a cover configured to surround a space above the heating plate; an exhaust gas flow forming mechanism configured to exhaust gas inside the cover to form exhaust gas flows within the space above the heating plate; a downflow forming mechanism configured to form downflows uniformly supplied onto an upper surface of the substrate placed on the heating plate; and a control mechanism configured to execute mode switching control between a mode arranged to heat the substrate while forming the downflows by the downflow forming mechanism and a mode arranged to heat the substrate while forming the exhaust gas flows by the exhaust gas flow forming mechanism.

Abstract: A manufacturing method of a thin film transistor includes forming a pair of source/drain electrodes on a substrate, such that the source/drain electrodes define a gap therebetween; forming low resistance conductive thin films, which define a gap therebetween, on the source/drain electrodes; and forming an oxide semiconductor thin film layer on upper surface of the low resistance conductive thin films and in the gap defined between the low resistance conductive thin films so that the oxide semiconductor thin film layer functions as a channel. The low resistance conductive thin films and the oxide semiconductor thin film layer are etched so that side surfaces of the resistance conductive thin films and corresponding side surfaces of the oxide semiconductor thin film layer coincide with each other in a channel width direction of the channel. A gate electrode is mounted over the oxide semiconductor thin film layer.

Abstract: A flash memory device and a method for fabricating the same are disclosed. The flash memory device includes an ONO layer on a substrate, polysilicon gates on the ONO layer, a gate oxide layer on the substrate, the ONO layer and the polysilicon gates, and a low temperature oxide layer and polysilicon sidewall spacers on outer side surfaces of the polysilicon gates, except in a region between nearest adjacent polysilicon gates.

Abstract: A semiconductor wafer may include, but is not limited to, the following elements. A semiconductor substrate has a device region and a dicing region. A stack of inter-layer insulators may extend over the device region and the dicing region. Multi-level interconnections may be disposed in the stack of inter-layer insulators. The multi-level interconnections may extend in the device region. An electrode layer may be disposed over the stack of inter-layer insulators. The electrode layer may extend in the device region. The electrode layer may cover the multi-level interconnections. A cracking stopper groove may be disposed in the dicing region. The cracking stopper groove may be positioned outside the device region.

Abstract: A liquid crystal display device and a fabrication method thereof, are discussed. According to an embodiment, the liquid crystal display device includes gate lines on a substrate; data lines on the substrate; common lines disposed substantially in parallel to the gate lines; TFTs formed at intersections between the gate and data lines, each of the TFTs including a gate electrode extending from the corresponding gate line, a gate insulation layer, an active layer, an ohmic contact layer, a source electrode extending from the corresponding data line and a drain electrode spaced apart from the source electrode; passivation layers, each formed on the TFT and having a contact hole for exposing a part of the corresponding drain electrode; and pixel electrodes, each composed of a conductive layer and an insulation layer formed on the corresponding passivation layer and electrically connected to the corresponding drain electrode via the corresponding contact hole.

Abstract: A conductive layer may be fabricated on a semiconductor substrate by loading a silicon substrate in to a chamber whose inside temperature is at a loading temperature in the range of approximately 250° C. to approximately 300° C., increasing the inside temperature of the chamber from the loading temperature to a process temperature, and sequentially stacking a single crystalline silicon layer and a polycrystalline silicon layer over the silicon substrate by supplying a silicon source gas and an impurity source gas in to the chamber, where the chamber may be, for example, a CVD chamber or a LPCVD chamber.

Abstract: Nicotinamide and/or a compound which is chemically combined with nicotinamide may be used as a carbon nanotube (“CNT”) n-doping material. CNTs n-doped with the CNT n-doping material may have long-lasting doping stability in the air without de-doping. Further, CNT n-doping state may be easily controlled when using the CNT n-doping material. The CNT n-doping material and/or CNTs n-doped with the CNT n-doping material may be used for various applications.

Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle.

Abstract: Semiconductor device including a metal carrier substrate. Above the carrier substrate a first semiconductor layer of Alx1Gay1Inz1N (x1+y1+z1=1, x1?0, y1?0, z1?0) is formed. A second semiconductor layer of Alx2Gay2Inz2N (x2+y2+z2=1, x2>x1, y2?0, z2?0) is arranged on the first semiconductor layer and a gate region is arranged on the second semiconductor layer. The semiconductor device furthermore includes a source region and a drain region, wherein one of these regions is electrically coupled to the metal carrier substrate and includes a conductive region extending through the first semiconductor layer.

Abstract: A method for fabricating a circuitry component comprises depositing a first metal layer over a substrate; forming a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposing said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; removing said first pattern-defining layer; forming a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposing said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first metal layer not under said second metal layer; and forming a polymer layer over said second metal layer, wherein said third metal layer is used as a metal bump bonded to an external circuitry.

Abstract: By providing a protective layer in an intermediate manufacturing stage, an increased surface protection with respect to particle contamination and surface corrosion may be achieved. In some illustrative embodiments, the protective layer may be used during an electrical test procedure, in which respective contact portions are contacted through the protective layer, thereby significantly reducing particle contamination during a respective measurement process.

Abstract: A method of forming an electronic component package includes forming a patterned dielectric layer comprising circuit pattern artifacts and at least one electronic component opening. An etch stop metal protected circuit pattern is plated with the circuit pattern artifacts. An electronic component is mounted in the electronic component opening. The etch stop metal protected circuit pattern provide an etch stop for substrate formation etch processes. In this manner, etching of a patterned conductor layer is avoided insuring that impedance is controlled to within tight tolerance.

Abstract: A method of manufacturing a semiconductor device is disclosed, wherein a plating layer is formed on a first surface side of a semiconductor substrate stably and at a low cost, while preventing the plating liquid from being contaminated and avoiding deposition of uneven plating layer on a second surface side. An electrode is formed on the first surface of the semiconductor substrate, and another electrode is formed on the second surface. A curing resin is applied on the electrode on the second surface and a film is stuck on the curing resin, and the curing resin is then cured. After that, a plating process is conducted on the first surface. The film and the curing resin are then peeled off.

Abstract: A method for forming an electrode for Group-III nitride compound semiconductor light-emitting devices includes a step of forming a first electrode layer having an average thickness of less than 1 nm on a Group-III nitride compound semiconductor layer, the first electrode layer being made of a material having high adhesion to the Group-III nitride compound semiconductor layer or low contact resistance with the Group-III nitride compound semiconductor layer and also includes a step of forming a second electrode layer made of a highly reflective metal material on the first electrode layer.

Abstract: CMOS image sensors and methods of fabricating the same. The CMOS image sensors include a pixel array region having an active pixel portion and an optical block pixel portion which encloses the active pixel portion. The optical block pixel portion includes an optical block metal pattern for blocking light. The optical block metal pattern may be connected to a ground portion.

Abstract: In one embodiment, the present disclosure provides a target or mold having one or more support arms coupled to a substrate. The support arm can be used in handling or positioning a target. In another embodiment, the present disclosure provides target molds, targets produced using such molds, and a method for producing the targets and molds. In various implementations, the targets are formed in a number of disclosed shapes, including a funnel cone, a funnel cone having an extended neck, those having Gaussian-profile, a cup, a target having embedded metal slugs, metal dotted foils, wedges, metal stacks, a Winston collector having a hemispherical apex, and a Winston collector having an apex aperture. In yet another embodiment, the present disclosure provides a target mounting and alignment system.

Abstract: A method for making a micro structure (100) is proposed. The method starts with the step of providing a silicon substrate (102), which has a main surface. A porous silicon layer (103)—extending into the silicon substrate from the main surface—is then formed. The method continues by etching the porous silicon layer selectively to obtain a set of projecting microelements of porous silicon (112); each projecting microelement projects from a remaining portion of the silicon substrate (106), thereby exposing a corresponding external surface. The projecting microelements are then treated to obtain a set of corresponding conductive (115) or insulating (115?) microelements; each conductive or insulating microelement is obtained by converting at least a prevalent portion of the porous silicon (extending into the corresponding projecting element from the external surface) into porous metal or ceramics, respectively.

Abstract: A method includes providing a semiconductor substrate having a gate trench and depositing a metal layer, using a physical vapor deposition (PVD) process, over the substrate to partially fill the trench. The metal layer includes a bottom portion and a sidewall portion that is thinner than the bottom portion. The method also includes forming a coating layer on the metal layer, etching back the coating layer such that a portion of the coating layer protects a portion of the metal layer within the trench, and removing the unprotected portion of the metal layer. A different aspect involves a semiconductor device that includes a gate that includes a trench having a top surface, and a metal layer formed over the trench, wherein the metal layer includes a sidewall portion and a bottom portion, and wherein the sidewall portion is thinner than the bottom portion.

Abstract: Under one aspect, a method of cooling a circuit element includes providing a thermal reservoir having a temperature lower than an operating temperature of the circuit element; and providing a nanotube article in thermal contact with the circuit element and with the reservoir, the nanotube article including a non-woven fabric of nanotubes in contact with other nanotubes to define a plurality of thermal pathways along the article, the nanotube article having a nanotube density and a shape selected such that the nanotube article is capable of transferring heat from the circuit element to the thermal reservoir.

Abstract: The invention provides a manufacturing method for a semiconductor photoelectrochemical cell, comprising the steps of burning a base made of titanium or a titanium alloy in an atmosphere of 700° C. to 1000° C. at a rate of temperature increase of no lower than 5° C./second so that a titanium oxide layer is formed on the surface, and thus, mixing titanium metal into said titanium oxide layer.

Abstract: In a manufacturing process of a semiconductor device, a manufacturing technique for reducing the number of lithography processes that use a photoresist and simplifying the process is provided, which improves throughput. An etching mask for forming a pattern of a layer to be processed such as a conductive layer or a semiconductor layer is manufactured without using a lithography technique that uses a photoresist. The etching mask is formed of a light absorption layer including a material which absorbs a laser beam. The mask is formed by irradiating the light absorption layer with a laser beam through a photomask and utilizing laser ablation by energy of the laser beam absorbed by the light absorption layer.

Abstract: A method is provided to form densely spaced metal lines. A first set of metal lines is formed by etching a first metal layer. A thin dielectric layer is conformally deposited on the first metal lines. A second metal is deposited on the thin dielectric layer, filling gaps between the first metal lines. The second metal layer is planarized to form second metal lines interposed between the first metal lines, coexposing the thin dielectric layer and the second metal layer at a substantially planar surface. In some embodiments, planarization continues to remove the thin dielectric covering tops of the first metal lines, coexposing the first metal lines and the second metal lines, separated by the thin dielectric layer, at a substantially planar surface.

Abstract: A semiconductor electronic device that includes a semiconductor substrate having a top surface; a seed layer positioned on the substrate and having a notched wall extending transversely with respect to the substrate top surface, the wall defining a first recess extending into the seed layer with a height equal to a thickness of the seed layer; a first conductive nanowire in contact with the notched wall, the first conductive nanowire having a contact portion extending into the first recess and covering opposite sidewalls and a bottom of the first recess; a first insulating nanowire in contact with a sidewall of the first conductive nanowire; an insulating layer on the contact portion of the first conductive nanowire and having a first window substantially in correspondence with the contact portion of the first conductive nanowire; and a first conductive die on the insulating layer that includes a conductive contact extending into the first window and contacting the contact portion of the first conductive nano

Abstract: A method of reducing the loss of elements of a photovoltaic thin film structure during an annealing process, includes depositing a thin film on a substrate, wherein the thin film includes a single chemical element or a chemical compound, coating the thin film with a protective layer to form a coated thin film structure, wherein the protective layer prevents part of the single chemical element or part of the chemical compound from escaping during an annealing process, and annealing the coated thin film structure to form a coated photovoltaic thin film structure, wherein the coated photovoltaic thin film retains the part of the single chemical element or the part of the chemical compound that is prevented from escaping during the annealing by the protective layer.

Abstract: A semiconductor device and a manufacturing method thereof that can prevent mutual diffusion of impurity in a silicide layer and can decrease sheet resistance of an N-type polymetal gate electrode and a P-type polymetal gate electrode, respectively in the semiconductor device having gate electrodes of a polymetal gate structure and a dual gate structure are provided. The P-type polymetal gate electrode includes a P-type silicon layer containing P-type impurity, a silicide layer formed on the P-type silicon layer and having a plurality of silicide grains which are discontinuously disposed in a direction substantially parallel with the surface of the semiconductor substrate, a silicon film continuously formed on the surface of the P-type silicon layer exposed on the discontinuous part of the silicide layer and on the surface of the silicide layer, a second metal nitride layer formed on the silicon film, and a metal layer formed on the metal nitride layer.