Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.

Abstract: Various die crack deflection structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes fabricating a semiconductor chip including an outer edge, a first side and a second side opposite to the first side. A deflection structure is fabricated in the semiconductor chip. The deflection structure includes a sloped profile to deflect a crack propagating in the semiconductor chip toward the first side or the second side of the semiconductor chip.

Abstract: A microelectronic programmable structure suitable for storing information and array including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the structure, and thus information may be stored using the structure.

Abstract: It is possible to efficiently remove deposited materials such as a conductive film or insulting film adhered to parts such as the inner wall of a processing chamber and a substrate supporting tool disposed in the processing chamber. There is provided a method of manufacturing a semiconductor device. The method comprises: loading a substrate into a processing chamber; forming a conductive film or an insulating film on the substrate by supplying a plurality of source gases into the processing chamber; unloading the substrate from the processing chamber; and modifying a conductive film or an insulating film adhered to the processing chamber by supplying a modifying gas into the processing chamber. After performing a cycle of the loading, the forming, the unloading, and the modifying processes a plurality of times, the modified conductive film or the modified insulating film adhered to the processing chamber is removed from the processing chamber by supplying a cleaning gas into the processing chamber.

Abstract: The present invention relates to a semiconductor device. The semiconductor device includes a fluorocarbon film formed on a substrate and a film containing metal formed on the fluorocarbon film, wherein the content amount of fluorine atom on the fluorocarbon film, which contacts the film containing metal, is in a predetermined range.

Abstract: Methods of fabricating transistor in which a first Group III nitride layer is formed on a substrate in a reactor, and a second Group III nitride layer is formed on the first Group III nitride layer. An insulating layer such as, for example, a silicon nitride layer is formed on the second Group III nitride layer in-situ in the reactor. The substrate including the first Group III nitride layer, the second group III nitride layer and the silicon nitride layer is removed from the reactor, and the silicon nitride layer is patterned to form a first contact hole that exposes a first contact region of the second Group III nitride layer. A metal contact is formed on the first contact region of the second Group III nitride layer.

Abstract: A semiconductor memory includes a composite floating structure where an insulation film is formed on a semiconductor substrate, Si-based quantum dots covered with an extremely thin Si oxide film is formed on the insulation film, silicide quantum dots covered with a high dielectric insulation film are formed on the extremely thin Si oxide film, and Si-based quantum dots covered with a high dielectric insulation film are formed on the high dielectric insulation film. Multivalued memory operations can be conducted at a high speed and with stability by applying a certain positive voltage to a gate electrode to accumulate electrons in the silicide quantum dots and by applying a certain negative voltage and weak light to the gate electrode to emit the electrons from the silicide quantum dots.

Abstract: Hybrid semiconductor materials have an inorganic semiconductor incorporated into a hole-conductive fluorene copolymer film. Nanometer-sized particles of the inorganic semiconductor may be prepared by mixing inorganic semiconductor precursors with a steric-hindering coordinating solvent and heating the mixture with microwaves to a temperature below the boiling point of the solvent.

Abstract: In one embodiment, a method is provided for forming stress in a semiconductor device. The semiconductor device may include a gate structure on a substrate, wherein the gate structure includes at least one dummy material that is present on a gate conductor. A conformal dielectric layer is formed atop the semiconductor device, and an interlevel dielectric layer is formed on the conformal dielectric layer. The interlevel dielectric layer may be planarized to expose at least a portion of the conformal dielectric layer that is atop the gate structure, in which the exposed portion of the conformal dielectric layer may be removed to expose an upper surface of the gate structure. The upper surface of the gate structure may be removed to expose the gate conductor. A stress inducing material may then be formed atop the at least one gate conductor.

Abstract: A process for forming a strained channel region for a MOSFET device via formation of adjacent silicon-germanium source/drain regions, has been developed. The process features either blanket deposition of a silicon-germanium layer, or selective growth of a silicon-germanium layer on exposed portions of a source/drain extension region. A laser anneal procedure results in formation of a silicon-germanium source/drain region via consumption of a bottom portion of the silicon-germanium layer and a top portion of the underlying source/drain region. Optimization of the formation of the silicon-germanium source/drain region via laser annealing can be achieved via a pre-amorphization implantation (PAI) procedure applied to exposed portions of the source/drain region prior to deposition of the silicon-germanium layer. Un-reacted top portions of the silicon-germanium layer are selectively removed after the laser anneal procedure.

Abstract: Atomic layer deposition methods as described herein can be advantageously used to form a metal-containing layer on a substrate. For example, certain methods as described herein can form a strontium titanate layer that has low carbon content (e.g., low strontium carbonate content), which can result in layer with a high dielectric constant.

Abstract: A thermal interface material is provided using composite particles. Advantages include increased thermal conductivity and improved mechanical properties such as lower viscosity. In selected embodiments free particles such as metallic particles or carbon nanotubes, etc. are included in a thermal interface material along with composite particles. An advantage of including free particles along with composite particles includes improved packing density within selected embodiments of thermal interface materials.

Abstract: Semiconductor-based electronic devices and techniques for fabrication thereof are provided. In one aspect, a device is provided comprising a first pad; a second pad and a plurality of nanowires connecting the first pad and the second pad in a ladder-like configuration formed in a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer, the nanowires having one or more dimensions defined by a re-distribution of silicon from the nanowires to the pads. The device can comprise a field-effect transistor (FET) having a gate surrounding the nanowires wherein portions of the nanowires surrounded by the gate form channels of the FET, the first pad and portions of the nanowires extending out from the gate adjacent to the first pad form a source region of the FET and the second pad and portions of the nanowires extending out from the gate adjacent to the second pad form a drain region of the FET.

Abstract: Methods of forming ruthenium or ruthenium dioxide are provided. The methods may include using ruthenium tetraoxide (RuO4) as a ruthenium precursor. In some embodiments for forming ruthenium, methods include forming a seed layer, and forming a ruthenium layer on the seed layer, using RuO4. In other embodiments, methods include performing atomic layer deposition cycles, which include using RuO4 and another ruthenium-containing co-precursor. In yet other embodiments, methods include adsorbing a reducing agent over a substrate, and supplying RuO4 to be reduced to ruthenium by the adsorbed reducing agent. In other embodiments for forming ruthenium dioxide, methods may include providing an initial seed layer formed of, for example, an organic compound, and supplying RuO4 over the seed layer.

Abstract: A noble metal nanoparticle can be grown on a semiconductor substrate by contacting a predetermined region of the substrate with a solution including noble metal ions. The predetermined region of the semiconductor substrate can be exposed by applying a polymeric layer over the substrate selectively removing a portion of the polymeric layer. The nanoparticles can be prepared in a predetermined pattern. Nanowires having a predetermined diameter and a predetermined position can be grown from the nanoparticles.

Abstract: Compositions, inks and methods for forming a patterned silicon-containing film and patterned structures including such a film. The composition generally includes (a) passivated semiconductor nanoparticles and (b) first and second cyclic Group IVA compounds in which the cyclic species predominantly contains Si and/or Ge atoms. The ink generally includes the composition and a solvent in which the composition is soluble. The method generally includes the steps of (1) printing the composition or ink on a substrate to form a pattern, and (2) curing the patterned composition or ink. In an alternative embodiment, the method includes the steps of (i) curing either a semiconductor nanoparticle composition or at least one cyclic Group IVA compound to form a thin film, (ii) coating the thin film with the other, and (iii) curing the coated thin film to form a semiconducting thin film.

Abstract: The semiconductor device includes: memory cells each having a first multilayer electrode including a first lower electrode made of a first conductive film and a first upper electrode made of a second conductive film formed one on the other with a first interface film therebetween; and a diode having a diode electrode made of the second conductive film and a second interface film as a silicon oxide film formed at the interface between the diode electrode and a substrate. The first interface film has a thickness with which electrical connection between the lower electrode and the upper electrode is maintained, and the second interface film has a thickness with which epitaxial growth between the substrate and the diode electrode is inhibited.

Abstract: In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film.

Abstract: Methods for fabricating semiconductor device structures are disclosed. In some embodiments, methods for fabricating semiconductor device structures may comprising forming at least one raised element on a surface of a substrate, the at least one raised element including sloped sides and a peak, aligning a strip comprising conductive material at least partially over the at least one raised element, and at least partially securing the strip to a surface of the at least one raised element and the surface of the substrate.

Abstract: Methods for forming patterns having triple the line frequency of a first pattern using only a single spacer are disclosed. For example, the first pattern is formed in a first and a second material using a lithographic process. Sidewall spacers are formed from a third material adjacent to exposed sidewalls of features in the second material. The width of the features in the first pattern in the first material is reduced. For example, the width is reduced to about the target width of features in a final pattern. The width of features in the first pattern in the second material is reduced using remaining portions of the first material as a mask. A second pattern is formed based on remaining portions of the second material and the sidewall spacers. The features in the second pattern may be lines having about ? the width of lines in the first pattern.

Abstract: A method of manufacturing a semiconductor device includes depositing a first capping layer on a dielectric layer. The method also includes etching the first capping layer from a second portion of the semiconductor device. The first capping layer remaining in a first portion of the semiconductor device may form a PMOS device. The method further includes depositing a second capping layer after etching the first capping layer. After the second capping layer is deposited a maskless process results in selectively etching the second capping layer from the first portion of the semiconductor device. The second portion of the semiconductor device may be a NMOS device. The method described may be used in manufacturing integrated CMOS devices as scaling reduces device size. Additionally, the method of selectively etching capping layers may be used to manufacture multi-threshold voltage devices.

Abstract: Semiconductor device performance is improved via a gate structure having a tunable effective workfunction and reduced gate depletion effects. According to an example embodiment, the design threshold voltage of a semiconductor device is adjusted in a manner that includes providing a gate having a workfunction that enables operation of the semiconductor device at a selected voltage. The gate is formed having two different conductive materials with different electric workfunctions that both significantly contribute to the overall workfunction of the gate. The relative composition, thickness, and arrangement of each of the two conductive materials is selected to attain a gate electrode workfunction that is different than the workfunctions of each of the two layers and that sets the threshold voltage of the semiconductor device. The adjustability of the effective workfunction of the gate electrode can be applied to a variety of semiconductor devices.

Abstract: A low resistivity interface material is provided between a self-aligned vertical heater element and a contact region of a selection device. A phase change chalcogenide material is deposited directly on the vertical heater element. In an embodiment, the vertical heater element in L-shaped, having a curved vertical wall along the wordline direction and a horizontal base. In an embodiment, the low resistivity interface material is deposited into a trench with a negative profile using a PVD technique. An upper surface of the low resistivity interface material may have a tapered bird-beak extension.

Abstract: Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. An integrated circuit memory cell can be fabricated by forming a cup-shaped electrode on sidewalls of an opening in an insulation layer and through the opening on an ohmic layer that is stacked on a conductive structure. An insulation filling member is formed that at least partially fills an interior of the electrode. The insulation filling member is formed within a range of temperatures that is sufficiently low to not substantially change resistance of the ohmic layer. A variable resistivity material is formed on the insulation filling member and is electrically connected to the electrode.

Abstract: Methods and devices for controlling a growth rate of films in semiconductor structures are shown. Chemical vapor deposition methods and devices include the use of a reaction inhibitor that selectively varies a deposition rate along a surface. One specific method includes atomic layer deposition. One method shown provides high step coverage over features such as trenches in trench plate capacitors. Also shown are methods and devices to provide uniform batch reactor layer thicknesses. Also shown are methods for forming alloy layers with high control over composition. Also shown are methods to selectively control growth rate to provide growth only on selected surfaces.

Abstract: Provided are a thin film transistor for display devices and a manufacturing method of the thin film transistor. The thin film transistor for display devices includes: a flexible substrate; a gate electrode layer formed on the flexible substrate; a first insulating layer formed on the flexible substrate and the gate electrode; a source and a drain formed on the first insulating layer; an active layer formed on the first insulating layer between the source and the drain; a second insulating layer formed on the first insulating layer, the source, the drain, and the active layer; and a drain electrode that opens the second insulating layer to be connected to the drain and is formed of a CNT dispersed conductive polymer.

Abstract: A thin wafer handling structure includes a semiconductor wafer, a release layer that can be released by applying energy, an adhesive layer that can be removed by a solvent, and a carrier, where the release layer is applied on the carrier by coating or laminating, the adhesive layer is applied on the semiconductor wafer by coating or laminating, and the semiconductor wafer and the carrier is bonded together with the release layer and the adhesive layer in between. The method includes applying a release layer on a carrier, applying an adhesive layer on a semiconductor wafer, bonding the carrier and the semiconductor wafer, releasing the carrier by applying energy on the release layer, e.g. UV or laser, and cleaning the semiconductor's surface by a solvent to remove any residue of the adhesive layer.

Abstract: A method of fabricating a photoactive array having an integrated backplane is provided. The layers of the device may be stamped or deposited on a planar or a curved substrate, such as a semispherical or ellipsoidal substrate. Each metal layer may be stamped using an elastomeric stamp and a vacuum mold. By depositing the patterned and full-surface layers in a single process, a photosensitive array with an integrated transistor backplane may be fabricated, resulting in improved sensitivity and performance.

Abstract: A semiconductor device includes a transistor having a recessed gate, contact plugs formed in a region of a plurality of trenches, which are formed by recessing a semiconductor substrate. Further, a metal line and a source/drain region can be connected through the contact plug, so that on-current can be increased as much as an increased channel area.

Abstract: A method for introducing a precursor vapor to a process chamber configured for forming a thin film on a substrate is described. The method includes transporting a process gas containing metal precursor vapor and a CO delivery gas to a process chamber, and introducing a CO saturation gas to the precursor vapor in the process chamber and optionally adjusting the spatial distribution of the CO saturation gas addition in order to affect improvements to the properties of the deposited film.

Abstract: A method is provided for making a crystalline silicon solar cell on a low purity substrate by depositing p+-p-n+, or n+-n-p+ layers of amorphous silicon, depending on the type of wafer, on a crystalline silicon substrate, such as an upgraded metallurgical grade silicon substrate, with substrate vias of varying diameters formed thereon, annealing the stack of amorphous silicon layers to cause solid phase epitaxial crystallization, and metallizing the substrate assembly using standard metallization techniques. One embodiment of the present invention provides depositing a passivation layer onto the third deposited silicon layer subsequent to the crystallization. Another embodiment provides depositing a passivation layer on the back side of the substrate subsequent to crystallization and punching selected regions at the substrate vias prior to back metallization.

Abstract: Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus comprises a processing chamber, a load lock coupled to the processing chamber via a transfer port, a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock, a remote plasma source configured to provide a remote plasma to the load lock, and an ion filter disposed between the remote plasma source and the wafer pedestal.

Abstract: A method of fabricating a semiconductor device, in which although a metal layer is included in a gate pattern, the gap-fill characteristic of contact plugs coupled to junctions can be improved and degradation in the data retention characteristic can also be prevented. According to the method, a semiconductor substrate in which lower gate patterns and gate hard mask patterns are sequentially stacked is first provided. Junctions are formed in the semiconductor substrate on both sides of each of the lower gate patterns. A first pre-metal dielectric layer is formed over the semiconductor substrate in which the hard mask patterns and the junctions are formed. Contact holes through which the junctions are exposed are formed in the first pre-metal dielectric layer. Gate trenches through which the lower gate patterns are exposed are formed by removing the hard mask patterns. Upper gate patterns, each including a metal layer, are formed in the gate trenches, and first contact plugs are formed in the contact holes.

Abstract: Methods for forming titanium nitride layers are provided herein. In some embodiments, a method of forming a titanium nitride layer on a substrate may include providing a substrate into a processing chamber having a target comprising titanium disposed therein; supplying a nitrogen-containing gas into the processing chamber; sputtering a titanium source material from the target in the presence of a plasma formed from the nitrogen-containing gas to deposit a titanium nitride layer on the substrate; and upon depositing the titanium nitride layer to a desired thickness, forming a magnetic field that biases ions in the processing chamber away from the substrate.

Abstract: In one embodiment, a semiconductor device has a topmost or highest conductive layer with at least one opening. The semiconductor device includes a semiconductor substrate having a cell array region and an interlayer insulating layer covering the substrate having the cell array region. The topmost conductive layer is disposed on the interlayer insulating layer in the cell array region. The topmost conductive layer has at least one opening. A method of fabricating the semiconductor device is also provided. The openings penetrating the topmost metal layer help hydrogen atoms reach the interfaces of gate insulating layers of cell MOS transistors and/or peripheral MOS transistors during a metal alloy process, thereby improve a performance (production yield and/or refresh characteristics) of a memory device.

Abstract: A semiconductor device has a conductive via formed around a perimeter of the semiconductor die. First and second conductive layers are formed on opposite sides of the semiconductor die and thermally connected to the conductive via. An insulating layer is formed over the semiconductor die. A portion of the insulating layer is removed to expose the first conductive layer and a thermal dissipation region of semiconductor die. A thermal via is formed through the insulating layer to the first conductive layer. A thermally conductive layer is formed over the thermal dissipation region and thermal via. A thermal conduction path is formed from the thermal dissipation region through the thermally conductive layer, thermal via, first conductive layer, conductive via, and second conductive layer. The thermal conduction path terminates in an external thermal ground point. The thermally conductive layer provides shielding for electromagnetic interference.

Abstract: Techniques for fabricating a photovoltaic device having a chalcopyrite absorber layer, such as a copper indium gallium selenide/sulfide (CIGSS) absorber layer, are provided. In one aspect, a method for fabricating a photovoltaic device is provided. The method includes the following steps. A precursor solution of metal chalcogenide dissolved in hydrazine or a hydrazine-like solvent is formed. Spray pyrolysis in an inert environment is used to deposit the precursor solution onto a substrate to form a metal chalcogenide layer on the substrate. A buffer layer is formed adjacent to a side of the metal chalcogenide layer opposite the substrate. A transparent conductive contact is formed adjacent to a side of the buffer layer opposite the metal chalcogenide layer.

Abstract: A method of forming metal lines of a semiconductor device, comprising providing a semiconductor substrate in which a plurality of gates and junctions formed between the gates are included in a cell area and a peripheral area; forming an insulating layer over the semiconductor substrate including the gates; forming an etch protection layer over the insulating layer; etching the etch protection layer and the insulating layer, and gap-filling conductive material to form contact plugs contacting the junctions of the cell area; and, forming first metal lines contacting the contact plugs and forming second metal lines contacting the junctions of the peripheral area by etching the etch protection layer and the insulating layer.

Abstract: Oxidation of a metal film disposed under a high permittivity insulation film can be suppressed, and the productivity of a film-forming process can be improved. In a method of manufacturing a semiconductor device, a first high permittivity insulation film is formed on a substrate by alternately repeating a process of supplying a source into a processing chamber in which the substrate is accommodated and exhausting the source and a process of supplying a first oxidizing source into the processing chamber and exhausting the first oxidizing source; and a second high permittivity insulation film is formed on the first high permittivity insulation film by alternately repeating a process of supplying the source into the processing chamber and exhausting the source and a process of supplying a second oxidizing source different from the first oxidizing source into the processing chamber and exhausting the second oxidizing source.

Abstract: A semiconductor power device with Zener diode for providing an electrostatic discharge (ESD) protection and a thick insulation layer to insulate the Zener diode from a doped body region. The semiconductor power device further includes a Nitride layer underneath the thick oxide layer working as a stopper layer for protecting the thin oxide layer and the body region underneath whereby the over-etch damage and punch-through issues in process steps are eliminated.

Abstract: The present invention relates to methods for fabricating nanoscale electrodes separated by a nanogap, wherein the gap size may be controlled with high precision using a self-aligning aluminum oxide mask, such that the gap width depends upon the thickness of the aluminum oxide mask. The invention also provides methods for using the nanoscale electrodes.

Abstract: A nanowire, nanosphere, metallized nanosphere, and methods for their fabrication are outlined. The method of fabricating nanowires includes fabricating the nanowire under thermal and non-catalytic conditions. The nanowires can at least be fabricated from metals, metal oxides, metalloids, and metalloid oxides. In addition, the method of fabricating nanospheres includes fabricating nanospheres that are substantially monodisperse. Further, the nanospheres are fabricated under thermal and non-catalytic conditions. Like the nanowires, the nanospheres can at least be fabricated from metals, metal oxides, metalloids, and metalloid oxides. In addition, the nanospheres can be metallized to form metallized nanospheres that are capable as acting as a catalyst.

Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.

Abstract: A ball grid array (BGA) package having a half-etched bonding pad and a cut plating line and a method of fabricating the same. In the BGA package, the plating line is cut to form a predetermined uneven bonding pad using half-etching, thereby increasing the contact area between the bonding pad and a solder ball. The BGA package includes a first external layer having a first circuit pattern and a wire bonding pad pattern wherein a chip is connected to a wire bonding pad using wire bonding. A second external layer includes a second circuit pattern, a cut plating line pattern, and a half-etched uneven solder ball pad pattern. In the second external layer, another chip is mounted on a solder ball pad. An insulating layer having a through hole interposed between the first and second external layers and electrically connects the first and second external layers therethrough.

Abstract: A semiconductor memory has a composite floating structure in which quantum dots composed of Si and coated with a Si oxide thin film are deposited on an insulating film formed on a semiconductor substrate, quantum dots coated with a high-dielectric insulating film are deposited on the quantum dots, and quantum dots composed of Si and coated with a high-dielectric insulating film are further deposited. Each of the quantum dots includes a core layer and a clad layer which covers the core layer. The electron occupied level in the core layer is lower than that in the clad layer.

Abstract: A method of forming a semiconductor device having a through-silicon via (TSV) is provided. A semiconductor device is provided having a first dielectric layer formed thereon. One or more dielectric layers are formed over the first dielectric layer, such that each of the dielectric layers have a stacking structure, wherein the stacking structures in the one or more dielectric layers are vertically aligned. The stacking structures may be, for example, metal rings. The stacking structures are then removed to form a first recess. A second recess is formed by extending the first recess into the substrate. The second recess is filled with a conductive material to form the TSV.

Abstract: Effective fillability and the uniformity electrodeposition of a copper electroplating solution is judged by determining the time-dependent potential change thereof at a cathode current density of 0.1-20 A/dm2. The potential change is determined at a working electrode rotation of 100-7500 rpm, and the fillability with the solution is judged from the curve profile. The time-dependent potential change curve within a predetermined period of time after the start of electrolysis is approximated according to the Boltzmann's function, and the potential change speed dx and the potential convergent point A2 are obtained to judge the fillability with a plating solution.

Abstract: The invented ink-jet printing method for the construction of thin film transistors using all SWNTs on flexible plastic films is a new process. This method is more practical than all of existing printing methods in the construction TFT and RFID tags because SWNTs have superior properties of both electrical and mechanical over organic conducting oligomers and polymers which often used for TFT. Furthermore, this method can be applied on thin films such as paper and plastic films while silicon based techniques can not used on such flexible films. These are superior to the traditional conducting polymers used in printable devices since they need no dopant and they are more stable. They could be used in conjunction with conducting polymers, or as stand-alone inks.

Abstract: Metallization contact structures and methods for forming a multiple-layer electrode structure on solar cells include depositing a conductive contact layer on a semiconductor substrate and depositing a metal bearing ink onto a portion of the conductive contact layer, wherein exposed portions of the conductive contact layer are adjacent to the metal bearing ink. The conductive contact layer is patterned by removing exposed portions of the conductive contact layer from the semiconductor substrate. The metal bearing ink is aligned with openings in a dielectric layer of the semiconductor substrate and with unexposed portions of the conductive contact layer. The unexposed portions of the conductive contact layer are interposed between the metal bearing ink and the dielectric layer such that the conductive contact layer pattern is aligned with metal bearing ink. The semiconductor substrate is thermally processed to form a current carrying metal gridline by sintering the metal bearing ink.

Abstract: An interconnector line of thin film comprising 0.001 to 30 at % of at least one kind of a first element capable of constituting an intermetallic compound of aluminum and/or having a higher standard electrode potential than aluminum, for example, at least one kind of the first element selected from Y, Sc, La, Ce, Nd, Sm, Gd, Tb, Dy, Er, Th, Sr, Ti, Zr, V, Nb, Ta, Cr, Mo, W, Mn, Tc, Re, Fe, Co, Ni, Pd, Ir, Pt, Cu, Ag, Au, Cd, Si, Pb and B; and one kind of a second element selected from C, O, N and H in a proportion of 0.01 at ppm to 50 at % of the first element, with the balance comprising substantially Al. In addition to having low resistance, such an Al interconnector line of thin film can prevent the occurrence of hillocks and the electrochemical reaction with an ITO electrode. The interconnector line of thin film can be obtained by sputtering in a dust-free manner by using a sputter target having a similar composition.