Abstract: According to example embodiments, a method of forming micropatterns includes forming dummy patterns having first widths on a dummy region of a substrate, and forming cell patterns having second widths on an active line region of the substrate. The active line region may be adjacent to the dummy region and the second widths may be less than the first widths. The method may further include forming damascene metallization by forming a seed layer on the active line region and the dummy region, forming a conductive material layer on a whole surface of the substrate, and planarizing the conductive material layer to form metal lines.

Abstract: A multilevel interconnect structure in a semiconductor device and methods for fabricating the same are described. The multilevel interconnect structure in the semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere.

Abstract: A semiconductor wafer including patterns transferred to a plurality of shot regions of the semiconductor wafer respectively, a plurality of chip regions being formed in the plurality of shot regions respectively, a plurality of first dummy patterns being formed respectively in a first chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of first dummy patterns being arranged repeatedly in a first manner, a plurality of second dummy patterns being formed respectively in a second chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of second dummy patterns being arranged repeatedly in a second manner different from the first manner.

Abstract: A method of manufacturing is provided that includes fabricating a first plurality of electrically functional interconnects on a front side of a first semiconductor chip and fabricating a first plurality of electrically non-functional interconnects on a back side of the first semiconductor chip. Additional chips may be stacked on the first semiconductor chip.

Abstract: A semiconductor device comprising a first insulating layer, a first metal conductor layer formed over the first insulating layer, a second insulating layer comprising a low-k insulating material formed over the first metal conductor, a second metal conductor layer formed over the second insulating layer, vias formed in the second insulating layer connecting the first metal conductor layer to the second metal conductor layer, and a plurality of metal lines. One of the metal lines is expanded around one of the vias compared to metal lines around other ones of the vias so that predetermined areas around each of the vias meets a minimum metal density.

Abstract: The invention is directed to firm bonding between semiconductor dies etc bonded to a lead frame and wire-bonding portions of the lead frame by ultrasonic Al wire bonding, and the prevention of shortcircuit between the semiconductor dies etc due to a remaining portion of the outer frame of the lead frame after the outer frame is cut. By extending the wire-bonding portion etc on the lead frame in a wire-bonding direction and connecting the wire-bonding portion etc to the outer frame of the lead frame through a connection lead etc, the ultrasonic vibration force in the ultrasonic Al wire bonding is prevented from dispersing and the Al wire and the wire-bonding portion etc are firmly bonded. The outer frame is cut after a resin sealing process is completed.

Abstract: When forming a trench of a narrow width in a thick semiconductor layer, a trench can be formed without the occurrence of semiconductor residue. In this Specification, a semiconductor device in which a trench is formed in a semiconductor layer is disclosed. In the semiconductor layer of the semiconductor device, a compensation pattern which compensates for sudden changes in the width of the trench is formed at a place at which the width of the trench changes suddenly. In the semiconductor layer of the above-described semiconductor device, since a compensation pattern is formed at a place at which the trench width changes suddenly, in the case where forming the trench using a deep RIE method, the occurrence of steep inclined portions arising from semiconductor residue can be prevented. Consequently, when forming a trench of a narrow width in a thick semiconductor layer, the occurrence of semiconductor residue can be prevented.

Abstract: A structure includes a semiconductor device formed in a substrate; an insulator adjacent to the semiconductor device; an electrical contact electrically coupled to the semiconductor device, wherein the electrical contact includes tungsten; and an electrical connector coupled to the electrical contact, wherein the electrical connector includes aluminum. A surface of the insulator and a surface of the electrical contact form a substantially even surface.

Abstract: Disclosed are embodiments of a contact formation technique that incorporates a preventative etch step to reduce interlayer dielectric material flaking (e.g., borophosphosilicate glass (BPSG) flaking) and, thereby to reduce surface defects. Specifically, contact openings, which extend through a dielectric layer to semiconductor devices in and/or on a center portion of a substrate, can be filled with a conductor layer deposited by chemical vapor deposition (CVD). Chemical mechanical polishing (CMP) of the conductor layer can be performed to complete the contact structures. However, before the CMP process is performed (e.g., either before the contact openings are ever formed or before the contact openings are filled), a preventative etch process can be performed to remove any dielectric material from above the edge portion of the substrate. Removing the dielectric material from above the edge portion of the substrate prior to CMP reduces the occurrence of surface defects caused by dielectric material flaking.

Abstract: A semiconductor device includes an embedding layer in which one or more semiconductor element(s) is embedded and one or more interconnect layers as well as one or more insulation layers on one or both sides of the embedding layer. The embedding layer includes a woven cloth formed by reinforcement fibers. The woven cloth has an opening on its site embedding the semiconductor element. The opening is arranged so that direction of the reinforcement fibers will have a preset angle with respect to a direction of a side of or a tangent to at least a portion of the opening, the preset angle being other than a square angle or a zero angle (parallelism).

Abstract: The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure.

Abstract: Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.

Abstract: Embodiments of a process comprising forming one or more micro-electro-mechanical (MEMS) probe on a conductive metal oxide semiconductor (CMOS) wafer, wherein each MEMS probe comprises a cantilever beam with a fixed end and a free end and wherein the CMOS wafer has circuitry thereon; forming an unsharpened tip at or near the free end of each cantilever beam; depositing a silicide-forming material over the tip; annealing the wafer to sharpen the tip; and exposing the sharpened tip.

Abstract: An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a gate cut region across the first gate structure, the second gate structure, or a combination thereof; providing a first gate contact over the first gate structure; providing a second gate contact over the second gate structure; and providing a diffusion contact structure coupling the first gate contact to the second gate contact, the diffusion contact structure having vertices within the gate cut region.

Abstract: A system and a method for protecting vias is disclosed. An embodiment comprises forming an opening in a substrate. A barrier layer disposed in the opening including along the sidewalls of the opening. The barrier layer may include a metal component and an alloying material. A conductive material is formed on the barrier layer and fills the opening. The conductive material to form a via (e.g., TSV).

Abstract: A system and method is disclosed for manufacturing thin film resistors using a trench and chemical mechanical polishing. A trench is etched in a layer of dielectric material and a thin film resistor layer is deposited so that the thin film resistor layer lines the trench. A thin film resistor protection layer is then deposited to fill the trench. Then a chemical mechanical polishing process removes excess portions of the thin film resistor layer and the thin film resistor protection layer. An interconnect metal is then deposited and patterned to create an opening over the trench. A central portion of the thin film resistor protection material is removed down to the thin film resistor layer at the bottom of the trench. The resulting structure is immune to the effects of topography on the critical dimensions (CDs) of the thin film resistor.

Abstract: An apparatus includes a device package, a first Integrated Circuit (IC) that is packaged in the device package, and a second IC, which is packaged in the device package and is fabricated on a multi-layer interconnection circuit including a plurality of interconnection layers for interconnecting components of the second IC, wherein a selected layer in the plurality is configured to serve as a conductive shield for reducing interference between the first and second ICs.

Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.

Abstract: Embodiments of a microelectronic package including at least one trench via are provided, as are embodiments of a method for fabricating such a microelectronic package. In one embodiment, the method includes the step of depositing a dielectric layer over a first microelectronic device having a plurality of contact pads, which are covered by the dielectric layer. A trench via is formed in the dielectric layer to expose the plurality of contact pads therethrough. The trench via is formed to include opposing crenulated sidewalls having a plurality of recesses therein. The plurality of contact pads exposed through the trench via are then sputter etched. A plurality of interconnect lines is formed over the dielectric layer, each of which is electrically coupled to a different one of the plurality of contact pads.

Abstract: A semiconductor device. In one embodiment the device includes a carrier. A first material is deposited on the carrier. The first material has an elastic modulus of less than 100 MPa. A semiconductor chip is placed over the first material. A second material is deposited on the semiconductor chip, the second material being electrically insulating. A metal layer is placed over the second material.

Abstract: A method for forming semiconductor devices using damascene techniques provides self-aligned conductive lines that have an end-to-end spacing less than 60 nm without shorting. The method includes using at least one sacrificial hardmask layer to produce a mandrel and forming a void in the mandrel. The sacrificial hardmask layers are formed over a base material which is advantageously an insulating material. Another hardmask layer is also disposed over the base material and under the mandrel in some embodiments. Spacer material is formed alongside the mandrel and filling the void. The spacer material serves as a mask and at least one etching procedure is carried out to translate the pattern of the spacer material into the base material. The patterned base material includes trenches and raised portions. Conductive features are formed in the trenches using damascene techniques.

Abstract: Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed substantially within a cavity of a substrate. Peripheral circuitry can be formed adjacent to a surface of the substrate and adjacent to the memory array. Additional apparatuses and methods are described.

Abstract: An interconnect structure including a gouging feature at the bottom of one of the via openings. The structure includes an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein. The conductively filled via is in contact with an exposed surface of the at least one conductive feature of a first interconnect level by an anchoring area. The conductively filled via is separated from the second dielectric material by a first diffusion barrier layer, and the conductively filled line is separated from the second dielectric material by a second continuous diffusion barrier layer thereby the second dielectric material includes no damaged regions in areas adjacent to the conductively filled line.

Abstract: A multilayer interconnect structure is formed by, providing a substrate having thereon a first dielectric for supporting a multi-layer interconnection having lower conductor MN, upper conductor MN+1, dielectric interlayer (DIL) and interconnecting via conductor VN+1/N. The lower conductor MN has a first upper surface located in a recess below a second upper surface of the first dielectric. The DIL is formed above the first and second surfaces. A cavity is etched through the DIL from a desired location of the upper conductor MN+1, exposing the first surface. The cavity is filled with a further electrical conductor to form the upper conductor MN+1 and the connecting via conductor VN+1/N making electrical contact with the first upper surface. A critical dimension between others of lower conductors MN and the via conductor VN+1/N is lengthened. Leakage current and electro-migration there-between are reduced.

Abstract: Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device.

Abstract: The present invention provides a method of forming connection holes. The method utilizes two different gases to perform two etching processes for the interlayer dielectric layer so as to form connection holes. The etching rate of the interlayer dielectric layer in the first etching process using the first etching gas is proportional to the size of the openings which defines the connection hole while the etching rate of the interlayer dielectric layer in the second etching process using the second etching gas is inversely related with size of the openings. According to the present invention, the first etching gas and the second etching gas compensate for each other to eliminate the loading effect, thus the connection holes are formed with almost the same depth. Therefore the damage of the etching stopper layer due to the high etching rate in the larger connection holes can be avoided, which prevents the excessive variation of the connecting resistance and expands the process window.

Abstract: A method of fabricating an airgap-containing interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a dielectric material is provided. Specifically, a simplified method of fabricating single-damascene and dual-damascene airgap-containing low-k interconnect structures with at least one patternable low-k dielectric and at least one inorganic antireflective coating is provided.

Abstract: Structure and methods for forming a semiconductor structure. The semiconductor structure includes a plurality of layers comprising at least one copper interconnect layer. The copper interconnect layer provides an electrical conduit between one of physically adjacent layers in the semiconductor structure and an integrated circuit in the semiconductor structure and an electronic device. A plurality of studs is positioned within the at least one copper interconnect layer. The studs are spaced apart by a distance less than or equal to a Blech length of the at least one copper interconnect layer. The Blech length is a length below which damage due to electromigration of metal atoms within the at least one copper interconnect layer does not occur. The plurality of studs comprises copper atom diffusion barriers.

Abstract: There is provided a film forming method for forming a film on a target object having thereon an insulating layer 1 that is made of a low-k film and having a recess 2 whose bottom surface is exposed to a metallic layer 3. The film forming method includes forming a first-metal-containing film containing a first metal such as ruthenium (Ru); and after forming the first-metal-containing film, forming a second-metal-containing film containing a second metal such as a manganese (Mn) having a barrier property against a filling metal to be filled in the recess.

Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.

Abstract: A secure electronic structure including a plurality of sub-lithographic conductor features having non-repeating random shapes as a physical unclonable function (PUF) and an integrated circuit including the same are provided. Some of the conductor features of the plurality of conductor features form ohmic electrical contact to a fraction of regularly spaced array of conductors that are located above or beneath the plurality of conductor features having the non-repeating shapes, while other conductor features of the plurality of conductor features do not form ohmic electrical contact with any of the regularly spaced array of conductors. Thus, a unique signature of electrical continuity is provided which can be used as a PUF within an integrated circuit.

Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.

Abstract: A semiconductor package and testing method is disclosed. The package includes a substrate having top and bottom surfaces, a semiconductor chip mounted in a centrally located semiconductor chip mounting area of the substrate, and a plurality of test pads disposed on top and bottom surfaces of the substrate and comprising a first group of test pads configured on the top and bottom surfaces of the substrate and having a first height above the respective top and bottom surface of the substrate, and a second group of test pads disposed on the lower surface of the substrate and having a second height greater than the first, wherein each one of the second group of test pads includes a solder ball attached thereto.

Abstract: A contiguous layer of graphene is formed on exposed sidewall surfaces and a topmost surface of a copper-containing structure that is present on a surface of a substrate. The presence of the contiguous layer of graphene on the copper-containing structure reduces copper oxidation and surface diffusion of copper ions and thus improves the electromigration resistance of the structure. These benefits can be obtained using graphene without increasing the resistance of copper-containing structure.

Abstract: Systems and methods are provided for an interposer for coupling two or more integrated circuit dies to a circuit package. A first integrated circuit portion is disposed on a first location of a single semiconductor substrate. A second integrated circuit portion is disposed on a second location of the single semiconductor substrate, where the second integrated circuit portion is electrically isolated from the first integrated circuit portion along a first axis. The first and second integrated circuit portions are configured to provide an electrical coupling to two or more corresponding top die integrated circuits across a second axis that is perpendicular to the first axis.

Abstract: An electronic device manufacturing process includes depositing a bottom electrode layer. Then an electronic device is fabricated on the bottom electrode layer. Patterning of the bottom electrode layer is performed after fabricating the electronic device and in a separate process from patterning a top electrode. A first dielectric layer is then deposited on the electronic device and the bottom electrode layer followed by a top electrode layer. The top electrode is then patterned in a separate process from the bottom electrode. Separately patterning the top and bottom electrodes improves yields by reducing voids in the dielectric material between electronic devices. One electronic device the manufacturing process is well-suited for is magnetic tunnel junctions (MTJs).

Abstract: A method of manufacturing a semiconductor device includes forming a first interconnection and a second interconnection above a semiconductor substrate, forming a first sidewall insulating film on a side wall of the first interconnection, and a second sidewall insulating film on a side wall of the second interconnection, forming a conductive film above the semiconductor substrate with the first interconnection, the first sidewall insulating film, the second interconnection and the second sidewall insulating film formed on, and selectively removing the conductive film above the first interconnection and the second interconnection to form in a region between the first interconnection and the second interconnection a third interconnection formed of the conductive film and spaced from the first interconnection and the second interconnection by the first sidewall insulating film and the second sidewall insulating film.

Abstract: The present invention provides a semiconductor device with an improved yield ratio and reduced height and manufacturing cost; and a method of manufacturing the semiconductor device. According to an aspect of the present invention, there is provided a semiconductor device including a substrate, a semiconductor element that is flip-chip connected to the substrate, and a molding portion that seals the semiconductor element. The side surfaces of the semiconductor element are enclosed by the molding portion. An upper surface of the semiconductor element is not enclosed by the molding portion. Damage to the side surfaces of the semiconductor element caused by an external impact when the semiconductor device is stored is minimized, because the molding portion protects the side surfaces of the semiconductor element. Accordingly, the yield ratio of the semiconductor device is improved.

Abstract: A single damascene or dual damascene interconnect structure fabricated with a photo-patternable low-k dielectric (PPLK) which is cured after etching. This method prevents the PPLK damage and the tapering of the edges of the interconnect structure. In one embodiment, the method of the present invention includes depositing a photo-patternable low-k (PPLK) material atop a substrate. The at least one PPLK material is patterned, creating a single damascene structure. For dual damascene structures, a second PPLK layer is coated and patterned. An etch process is performed to transfer the pattern from the PPLK material into at least a portion of the substrate. A diffusion liner and a conductive material can be deposited after the etch process. The resulting structure is cured anytime after etching in order to transform the resist like PPLK into a permanent low-k material that remains within the structure.

Abstract: A method of forming a semiconductor structure includes forming a sacrificial conductive material layer. The method also includes forming a trench in the sacrificial conductive material layer. The method further includes forming a conductive feature in the trench. The method additionally includes removing the sacrificial conductive material layer selective to the conductive feature. The method also includes forming an insulating layer around the conductive feature to embed the conductive feature in the insulating layer.

Abstract: According to example embodiments, a methods includes forming a peripheral structure including peripheral circuits on a peripheral circuits region of a substrate, recessing a cell array region of the substrate to form a concave region having a bottom surface lower than a top surface of the peripheral structure, forming a stacked layer structure conformally covering the concave region, the stacked layer structure including a plurality of layers sequentially stacked and having a lowest top surface in the cell array region and a highest top surface in the peripheral circuits region, forming a planarization stop layer that conformally covers the stacked layer structure, and planarizing the stacked layer structure using the planarization stop layer in the cell array region as a planarization end point to expose top surfaces of the thin layers between the cell array region and the peripheral circuits region simultaneously with a top surface of the peripheral structure.

Abstract: The various embodiments of the present invention provide fine pitch, chip-to-substrate interconnect assemblies, as well as methods of making and using the assemblies. The assemblies generally include a semiconductor having a die pad and a bump disposed thereon and a substrate having a substrate pad disposed thereon. The bump is configured to electrically interconnect at least a portion of the semiconductor with at least a portion of the substrate when the bump is contacted with the substrate pad. In addition, when the bump is contacted to the substrate pad, at least a portion of the bump and at least a portion of the substrate pad are deformed so as to create a non-metallurgical bond therebetween.

Abstract: A clock architecture for a Structured ASIC chip, manufactured using a CMOS process is shown. A via-configurable logic block (VCLB) architecture in the Structured ASIC has a core region containing memory and logic cells arranged in columns that are supplied by a clock network having a global clock network tree and a low-level clock mesh to distribute the global clock signal in a repeating pattern. The clock mesh has a fishbone configuration in outline and allows for scalable expansion of the clock network. In one embodiment 36 global clocks may be provided to the Structured ASIC, with four clocks per logic cell. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node, having several metal layers but preferably is programmable on a single via layer.

Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.

Abstract: A method of patterning a metal layer is disclosed. The method includes providing a substrate and forming a material layer over the substrate. The method includes forming a second material layer over the first material layer. The method includes performing a first patterning process to the second material layer to form a trench in the second material layer. The first patterning process defines a width size of the trench, the width size being measured in a first direction. The method includes performing a second patterning process to the trench to transform the trench. The second patterning process defines a length size of the transformed trench. The length size is measured in a second direction different from the first direction. The method also includes filling the transformed trench with a conductive material.

Abstract: In a method for manufacturing a light-emitting device according to an embodiment of the present invention, one surface of a first substrate including a reflective layer including an opening, a light absorption layer formed over the reflective layer to cover the opening in the reflective layer, a protective layer formed over the light absorption layer and including a groove at a position overlapped with the opening in the reflective layer, and a material layer formed over the protective layer and a deposition surface of a second substrate are disposed to face each other and light irradiation is performed from the other surface side of the first substrate, so that an EL layer is formed in a region on the deposition surface of the second substrate, which is overlapped with the opening in the reflective layer.

Abstract: A semiconductor device includes a carrier and a first chip attached to the carrier. The semiconductor device includes a sintered insulation material over at least a portion of the carrier and the first chip.

Abstract: The present invention relates to a method of manufacturing a semiconductor device by which the length of nanowires perpendicularly formed can be fabricated with high reproducibility. The method of manufacturing a semiconductor device includes the steps of forming a first layer; forming a stop layer on the first layer, the stop layer having a higher Young's modulus than the first layer; forming a recess by partially removing the first layer and the stop layer; growing nanowires in the recess; forming a planarizing layer; removing the planarizing layer to the level of the stop layer to expose the nanowires from the surface of the planarizing layer; and forming an electrode so as to be in contact with the upper ends of the nanowires.

Abstract: One embodiment of the present invention relates to a photolithography mask configured to form a metallization and via level utilizing a single lithography and etch process. More particularly, a photolithography mask comprising a mask via shape and one or more metal wire shapes is configured to produce both on-wafer metal lines and via levels. The mask via shape corresponds to an on-wafer photoresist via opening having a first critical dimension (CD). The one or more mask wire shapes correspond to one or more on-wafer photoresist wire openings respectively having a second CD. The first CD is larger than the second CD thereby providing a greater vertical etch rate for ILD exposed by the photoresist via opening than for ILD exposed by the one or more photoresist wire openings. This difference in CD results in a via extending vertically below the metal wire level, thereby making physical contact with underlying metal.

Abstract: A method for manufacturing a semiconductor device is disclosed, which reduces a step difference between a peripheral region and a cell region. In the semiconductor device, a metal contact of the peripheral region is configured in a multi-layered structure. Prior to forming a bit line and a storage node contact in the cell region, a contact and a line are formed in the peripheral region, such that a step difference between the cell region and the peripheral region is reduced, resulting in a reduction in parasitic capacitance between lines.