Abstract: The present invention provides a neural sensing device and method for making the same. The neural sensing device includes a base, an integrated circuit portion, a plurality of microprobes and at least one conductive via. The base has an active surface and a backside surface. The integrated circuit portion is disposed on the active surface of the base. The microprobes protrude from the backside surface of the base. The through silicon via is disposed in the base and electrically connects the integrated circuit portion and the microprobes. Each of the microprobes includes an isolation layer partially covering a conductive layer.

Abstract: The present disclosure is directed to a semiconductor structure and a method of manufacturing a semiconductor structure in which a spacer element is formed adjacent to a metal body embedded in a first dielectric layer of a first interconnect layer. A via which is misaligned relative to an edge of the metal body is formed in a second dielectric material in second interconnect layer disposed over the first interconnect layer and filled with a conductive material which is electrically coupled to the metal body. The method allows for formation of an interconnect structure without encountering the various problems presented by via substructure defects in the dielectric material of the first interconnect layer, as well as eliminating conventional gap-fill metallization issues.

Abstract: Capacitively coupled vertical transitions may be configured with a desired amount of mutual capacitance to at least partially cancel crosstalk for an overall channel crosstalk (e.g., FEXT) reduction. In embodiments, capacitive coupling of adjacent vertical transitions is achieved with overlapping metal surfaces within the vertical transitions. In embodiments, one or more of the overlapping metal surfaces are vias, via pads, or metal stub features extending off a vertical transition. In embodiments, signal paths with overlapped vertical transitions are utilized to achieve crosstalk reduction of more than one victim-aggressor pair and/or to achieve crosstalk reduction of more than two aggressors. In embodiments, capacitively coupled vertical transitions are implemented in a package substrate, an interposer, or a printed circuit board.

Abstract: A vertical NAND string device includes a semiconductor channel, where at least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of a substrate, at least one semiconductor or electrically conductive landing pad embedded in the semiconductor channel, a tunnel dielectric located adjacent to the semiconductor channel, a charge storage region located adjacent to the tunnel dielectric, a blocking dielectric located adjacent to the charge storage region and a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate.

Abstract: Vertical mount packages and methods for making the same are disclosed. A method for manufacturing a vertical mount package includes providing a device substrate with a plurality of device regions on a front surface, and a plurality of through-wafer vias. MEMS devices or integrated circuits are formed or mounted onto the device regions. A capping substrate having recesses is mounted over the device substrate, enclosing the device regions within cavities defined by the recesses. A plurality of aligned through-wafer contacts extend through the capping substrate and the device substrate. The device substrate and capping substrate can be singulated by cutting through the aligned through-wafer contacts, with the severed through-wafer contacts forming vertical mount leads. A vertical mount package includes a device sealed between a device substrate and a capping substrate. At least of the side edges of the package includes exposed conductive elements for vertical mount leads.

Abstract: A method for fabricating integrated circuits includes providing a substrate including a protecting layer over an oxide layer and etching a recess through the protecting layer and into the oxide layer. A barrier material is deposited over the substrate to form a barrier layer including a first region in the recess and a second region outside the recess. A conductive material is deposited over the barrier layer and forms an embedded electrical interconnect in the recess and an overburden region outside the recess. The overburden region of the conductive material is removed and a portion of the embedded electrical interconnect is recessed. Thereafter, the barrier layer is etched to remove the second region of the barrier layer and to recess a portion of the first region of the barrier layer. After etching the barrier layer, the protecting layer is removed from the oxide layer.

Abstract: A sensor array for detecting particles, the sensor array comprising a substrate having a plurality of holes, a plurality of electronic sensor chips each having a sensor active region being sensitive to the presence of particles to be detected, and an electric contacting structure adapted for electrically contacting the plurality of electronic sensor chips, wherein the plurality of electronic sensor chips and/or the electric contacting structure are connected to the substrate in such a manner that the plurality of holes in combination with the plurality of electronic sensor chips and/or the electric contacting structure form a plurality of wells with integrated particle sensors.

Abstract: A plug structure including a first dielectric layer, a second dielectric layer, a barrier layer and a second plug is provided. The first dielectric layer having a first plug therein is located on a substrate, wherein the first plug physically contacts a source/drain in the substrate. The second dielectric layer having an opening exposing the first plug is located on the first dielectric layer. The barrier layer conformally covers the opening, wherein the barrier layer has a bottom part and a sidewall part, and the bottom part is a single layer and physically contacts the first plug while the sidewall part is a dual layer. The second plug fills the opening and on the barrier layer. Moreover, a process of forming a plug structure is also provided.

Abstract: In a metallization system of a semiconductor device, a transition via may be provided with an increased degree of tapering by modifying a corresponding etch sequence. For example, the resist mask for forming the via opening may be eroded once or several times in order to increase the lateral size of the corresponding mask opening. Due to the pronounced degree of tapering, enhanced deposition conditions may be accomplished during the subsequent electrochemical deposition process for commonly filling the via opening and a wide trench connected thereto.

Abstract: A capacitor dielectric can be between the storage node and the electrode layer. A supporting pattern can be connected to the storage node, where the supporting pattern can include at least one first pattern and at least one second pattern layered on one another, where the first pattern can include a material having an etch selectivity with respect to the second pattern.

Abstract: A spacer etching process produces ultra-narrow conductive lines in a plurality of semiconductor dice. Sub-lithographic patterning of the conductive lines are compatible with existing aluminum and copper backend processing. A first dielectric is deposited onto the semiconductor dice and trenches are formed therein. A conductive film is deposited onto the first dielectric and the trench surfaces. All planar conductive film is removed from the faces of the semiconductor dice and bottoms of the trenches, leaving only conductive films on the trench walls, whereby “fence conductors” are created therefrom. Thereafter the gap between the conductive films on the trench walls are filled in with insulating material. A top portion of the insulated gap fill is thereafter removed to expose the tops of the fence conductors. Portions of the fence conductors and surrounding insulating materials are removed at appropriate locations to produce desired conductor patterns comprising isolated fence conductors.

Abstract: A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. A notch is designed in the layout on a selective portion of the mask for patterning conductor line. The existence of a shape of notch on the selective portion generates extra stress components within the conductor line than if without the existence of the notch. The position of the notch is selected so that the extra stress components substantially counteract the residual stresses, thereby causing a net reduction in the residual stresses. The reduction in the residual stresses results in a corresponding mechanical stress migration and therefore improvement in the reliability of the device.

Abstract: A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die.

Abstract: Methods for fabricating conductive metal lines of a semiconductor device are described herein. In one embodiment, such a method may comprise depositing a conductive material over a substrate, and depositing a first barrier layer on the conductive layer. Such a method may also comprise patterning a mask on the first barrier layer, the pattern comprising a layout of the conductive lines. Such an exemplary method may also comprise etching the conductive material and the first barrier layer using the patterned mask to form the conductive lines. In addition, a low temperature post-flow may be performed on the structure. The method may also include depositing a dielectric material over and between the patterned conductive lines.

Abstract: A semiconductor memory device having a cell pattern formed on an interconnection and capable of reducing an interconnection resistance and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate in which a cell area, a core area, and a peripheral area are defined and a bottom structure is formed, a conductive line formed on an entire structure of the semiconductor substrate, a memory cell pattern formed on the conductive line in the cell area, and a dummy conductive pattern formed on any one of the conductive line in the core area and the peripheral area.

Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

Abstract: Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds.

Abstract: A chip contact pad and a method of making a chip contact pad are disclosed. An embodiment of the present invention includes forming a plurality of contact pads over a workpiece, each contact pad having lower sidewalls and upper sidewalls and reducing a lower width of each contact pad so that an upper width of each contact pad is larger than the lower width. The method further includes forming a photoresist over the plurality of contact pads and removing portions of the photoresist thereby forming sidewall spacers along the lower sidewalls.

Abstract: A method for patterning a semiconductor structure is provided. The method comprises following steps. A first mask defining a first pattern in a first region and a second pattern in a second region adjacent to the first region is provided. The first pattern defined by the first mask is transferred to a first film structure in the first region, and the second pattern defined by the first mask is transferred to the first film structure in the second region. A second film structure is formed on the first film structure. A second mask defining a third pattern in the first region is provided. At least 50% of a part of the first region occupied by the first pattern defined by the first mask is identical with a part of the first region occupied by the third pattern defined by the second mask.

Abstract: Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

Abstract: A method of manufacturing an encapsulation substrate for an organic light emitting diode display, includes fabricating a composite panel by forming an uncured carbon fiber resin portion having a plate shape and including an upper surface and a lower surface and forming an uncured insulating resin portion arranged to surround edges of the carbon fiber resin portion, the uncured insulating resin portion being perforated by a plurality of penetration holes, inserting a plurality of conductive components into corresponding ones of the plurality of penetration holes, covering upper and lower surfaces of the composite panel with metal films and bonding the metal films to the composite panel while simultaneously curing the carbon fiber resin and the insulating resin portion by applying heat and pressure to the composite panel. Therefore, fabrication processes of the encapsulation substrate are simple, and fabrication costs are reduced.

Abstract: A semiconducting multi-layer structure comprising a plurality of first conductive layers, a plurality of first insulating layers and a second conductive layer is disclosed. The first conductive layers are separately disposed. Each of the first conductive layers has an upper surface, a bottom surface opposite to the upper surface and a lateral surface. The first insulating layers surround the peripherals of the first conductive layers. Each of the first insulating layers covers at least a part of the upper surface of each of the first conductive layers, at least a part of the bottom surface of each of the first conductive layers and the two lateral surface of each of the first conductive layers. The second conductive layer covers the first conductive layers and the first insulating layers.

Abstract: A semiconductor package and a method for fabricating the same. The semiconductor package includes a first substrate including a first pad, a second substrate spaced apart from the first substrate and where a second pad is formed to face the first pad, a first bump electrically connecting the first pad to the second pad, and a second bump mechanically connecting the first substrate to the second substrate is disposed between the first substrate where the first pad is not formed and the second substrate where the second pad is not formed. A coefficient of thermal expansion (CTE) of the second bump is smaller than that of the first bump.

Abstract: A selective conductive cap is deposited on exposed metal surfaces of a metal line by electroless plating selective to exposed underlying dielectric surfaces of a metal interconnect structure. A dielectric material layer is deposited on the selective conductive cap and the exposed underlying dielectric layer without a preclean. The dielectric material layer is planarized to form a horizontal planar surface that is coplanar with a topmost surface of the selective conductive cap. A preclean is performed and a dielectric cap layer is deposited on the selective conductive cap and the planarized surface of the dielectric material layer. Because the interface including a surface damaged by the preclean is vertically offset from the topmost surface of the metal line, electromigration of the metal in the metal line along the interface is reduced or eliminated.

Abstract: One method disclosed herein includes forming a plurality of source/drain contacts that are conductively coupled to a source/drain region of a plurality of transistor devices, wherein at least one of the source/drain contacts is a local interconnect structure that spans the isolation region and is conductively coupled to a first source/drain region in a first active region and to a second source/drain region in a second active region, and forming a patterned mask layer that covers the first and second active regions and exposes at least a portion of the local interconnect structure positioned above an isolation region that separates the first and second active regions. The method further includes performing an etching process through the patterned mask layer to remove a portion of the local interconnect structure, thereby defining a recess positioned above a remaining portion of the local interconnect structure, and forming an insulating material in the recess.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on a heavily doped layer and having an active cell area and an edge termination area. The edge termination area comprises a plurality P-channel MOSFETs. By connecting the gate to the drain electrode, the P-channel MOSFET transistors formed on the edge termination are sequentially turned on when the applied voltage is equal to or greater than the threshold voltage Vt of the P-channel MOSFET transistors, thereby optimizing the voltage blocked by each region.

Abstract: An electromigration and stress migration enhancement liner is provided for use in an interconnect structure. The liner includes a metal that has a thickness at a bottom of the at least one via opening and on an exposed portion of an underlying conductive feature that is greater than a remaining thickness that is located on exposed sidewalls of the interconnect dielectric material. The thinner portion of the electromigration and stress migration enhancement liner is located between the interconnect dielectric material and an overlying diffusion barrier. The thicker portion of the electromigration and stress migration enhancement liner is located between the underlying conductive feature and the diffusion barrier as well as between an adjacent dielectric capping layer and the diffusion barrier. The remainder of the at least one via opening is filled with an adhesion layer and a conductive material.

Abstract: A structure and method of making the structure. The structure includes a dielectric layer on a substrate; a first wire formed in a first trench in the dielectric layer, a first liner on sidewalls and a bottom of the first trench and a first copper layer filling all remaining space in the first trench; a second wire formed in a second trench in the dielectric layer, a second liner on sidewalls and a bottom of the second trench and a second copper layer filling all remaining space in the second trench; and an electromigration stop formed in a third trench in the dielectric layer, a third liner on sidewalls and a bottom of the third trench and a third copper layer filling all remaining space in the third trench, the electromigration stop between and abutting respective ends of the first and second wires.

Abstract: A method of forming an interlayer conductor structure. The method includes forming a stack of semiconductor pads coupled to respective active layers for a circuit. The semiconductor pads include outside perimeters each having one side coupled to a respective active layer. Impurities are implanted along the outside perimeters to form outside lower resistance regions on the pads. Openings are then formed in the stack of the semiconductor pads to expose a landing area for interlayer conductors on a corresponding semiconductor pad and to define an inside perimeter on at least one of the semiconductor pads. Inside lower resistance regions are formed along the inside perimeters by implanting impurities for interlayer conductor contacts and configured to overlap and be continuous with the corresponding outside lower resistance region.

Abstract: Methods of forming integrated circuit devices include forming first and second electrically conductive lines at side-by-side locations on an integrated circuit substrate. Steps are performed to selectively etch each of the first and second electrically conductive lines into a respective pair of interconnects having facing ends that are separated from each other. This selective etching step is performed using a photolithography mask having a modified-rectangular mask pattern thereon, which is configured to define a shape of the facing ends of each of the pair of interconnects.

Abstract: A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.

Abstract: A multilayer interconnect structure is formed by, providing a substrate (40) having thereon a first dielectric (50, 27) for supporting a multi-layer interconnection (39) having lower conductor MN (22, 23), upper conductor MN+1 (34, 35), dielectric interlayer (DIL) (68) and interconnecting via conductor VN+1/N (36, 36?). The lower conductor MN (22, 23) has a first upper surface (61) located in a recess below a second upper surface (56) of the first dielectric (50, 27). The DIL (68) is formed above the first (61) and second (56) surfaces. A cavity (1263) is etched through the DIL (68) from a desired location (122) of the upper conductor MN+1 (34), exposing the first surface (61). The cavity (1263) is filled with a further electrical conductor (80) to form the upper conductor MN+1 (34) and the connecting via conductor VN+1/N (36, 36?) making electrical contact with the first upper surface (61).

Abstract: Some embodiments include methods of forming electrical contacts. A row of semiconductor material projections may be formed, with the semiconductor material projections containing repeating components of an array, and with a terminal semiconductor projection of the row comprising a contact location. An electrically conductive line may be along said row, with the line wrapping around an end of said terminal semiconductor projection and bifurcating into two branches that are along opposing sides of the semiconductor material projections. Some of the semiconductor material of the terminal semiconductor projection may be replaced with dielectric material, and then an opening may be extended into the dielectric material. An electrical contact may be formed within the opening and directly against at least one of the branches. Some embodiments include memory arrays.

Abstract: The invention concerns a method comprising: forming a plurality of parallel lines (502, 504, 506) of a sacrificial material over a layer of conductive material (510) of an integrated circuit, said parallel lines being separated by trenches, at least one of said lines being interrupted along its length by an opening (516) dividing it into first and second line portions (504A, 504B) separated by a space (S); forming spacers (522, 524, 526, 528, 530) in said trenches on lateral sides of said line portions and filling at least a bottom part of said opening between the line portions; removing the sacrificial material by etching; and forming interconnection lines (302, 304A, 304B, 306A, 306B, 308, 310) of said conductive material based on a pattern defined by said spacers.

Abstract: A method for fabricating through-silicon vias (TSVs) for semiconductor devices is provided. Specifically, the method involves utilizing copper contact pads in a back-end-of-line wiring level, wherein the copper contact pads act as cathodes for performing an electroplating technique to fill TSVs with plated-conductive material (e.g., copper) from an electroplating solution. Moreover, the method provides a way to fill high aspect ratio TSVs with minimal additional semiconductor fabrication process steps, which can increase the silicon area that is available for forming additional electronic components on integrated circuits.

Abstract: A method of forming a memory device. A first thickness of dielectric material overlies a surface region of a substrate. A first wiring material including a first lining material and a silver material are formed overlying the dielectric material. A first adhesion material and an amorphous silicon switching material including a contact material are deposited overlying the first wiring material. The method forms one or more first structures configured to spatially extend in a first direction from the amorphous silicon switching material, the contact material, and the first wiring material. A thickness of second dielectric material is deposited overlying the one or more first structures. The method forms a second wiring structure comprising at least a second silver material and a second lining material spatially extending in a second direction orthogonal to the first direction overlying the second dielectric material and in electrical contact with the switching material.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device, includes forming first layer on first and second regions in substrate, first layer having first width in first region and having larger dimension than first width in second region, forming first sidewall on first layer, forming second layer covering first sidewall in the second region and forming third layer having second width smaller than first width on the side face of first sidewall having second width after removing first layer, forming second and third sidewalls having second width so that second and third sidewalls is adjacent to first sidewall across third layer by second width in first region and across second and third layers by second interval larger than second width in the second region.

Abstract: An embodiment of the invention provides a chip package which includes: a substrate; a device region disposed in or on the substrate; a signal pad disposed in or on the substrate and electrically connected to the device region; a ground pad disposed in or on the substrate; a signal bump disposed on a surface of the substrate, wherein the signal bump is electrically connected to the signal pad through a signal conducting layer; a ground conducting layer disposed on the surface of the substrate and electrically connected to the ground pad; and a protection layer disposed on the surface of the substrate, wherein the protection layer completely covers the entire side terminals of the signal conducting layer and partially covers the ground conducting layer such that a side terminal of the ground conducting layer is exposed on a side of the substrate.

Abstract: Methods of forming fine patterns are provided. The methods may include forming first hard mask patterns extending in a first direction on a lower layer, forming second hard mask patterns filling gap regions between the first hard mask patterns, forming first mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the first mask patterns as etch masks to form first openings, forming second mask patterns filling the first openings and extending in the second direction, and etching the second hard mask patterns using the second mask patterns as etch masks to form second openings spaced apart from the first openings in a diagonal direction with respect to the first direction.

Abstract: Methods and memory devices formed using etch bias homogenization are provided. One example method of forming a memory device using etch bias homogenization includes forming conductive material at respective levels over a substrate. Each respective level of conductive material is electrically coupled to corresponding circuitry on the substrate during patterning of the respective level of conductive material so that each respective level of conductive material has a homogenized etch bias during patterning thereof. Each respective level of conductive material electrically coupled to corresponding circuitry on the substrate is patterned.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece and a plurality of first conductive lines disposed over the workpiece in a metallization layer. A plurality of second conductive lines is disposed over the workpiece in the metallization layer. The plurality of second conductive lines comprises a greater vertical height in a cross-sectional view of the workpiece than a vertical height of the plurality of first conductive lines.

Abstract: A rewiring is formed by forming a Cu seed layer of copper over an opening and insulating films, forming a photoresist film over the Cu seed layer, a step of forming copper film by plating-growth over the Cu seed layer, and forming a Ni film. After forming an Au film in an opening (pad region) over the rewiring, the photoresist film is removed and passivation processing is performed on the Ni film. Then, the Cu seed layer other than the formation region of the rewiring is etched. According to these steps, a passivation film is formed on the surface of the Ni film and the reduction in film thickness of the Ni film by the etching can be reduced. Furthermore, it is possible to reduce trouble due to distortion of a substrate resulting from an increase in thickness of the Ni film in view of reduction in film thickness.

Abstract: Methods and apparatus for manufacturing semiconductor devices, and such semiconductor devices, are described. According to various aspects of the disclosure, a semiconductor device can be manufactured by forming a core region of the semiconductor device and forming a periphery region of the semiconductor device. A first polysilicon region can then be formed over the core and periphery regions of the semiconductor device. A first mask is formed on the first poly silicon layer and a second polysilicon layer is disposed such that the second polysilicon layer covers the first mask. A second mask can then be formed on the second polysilicon layer. After forming the second mask, portions of the first and second polysilicon layers that are uncovered by either the first or second masks are removed.

Abstract: According to one embodiment, a method for forming an interconnection pattern includes forming an insulating pattern, forming a self-assembled film, and forming a conductive layer. The insulating pattern has a side surface on a major surface of a matrix. The self-assembled film has an affinity with a material of the insulating pattern on the side surface of the insulating pattern. The forming the conductive layer includes depositing a conductive material on a side surface of the self-assembled film.

Abstract: A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of interconnect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.

Abstract: Methods are provided for fabricating interconnect structures containing various capping materials for electrical fuses and other related applications. The method includes forming a first interconnect structure having a first interfacial structure and forming a second interconnect structure adjacent to the first structure. The second interconnect structure is formed with a second interfacial structure different from the first interfacial structure of the first interconnect structure.

Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect embedded in a first surface of the first dielectric layer, and a second interconnect on the first surface of the first dielectric layer. The first interconnect is offset from the first surface of the first dielectric layer. The first interconnect being offset towards an inner portion of the first dielectric layer. In some implementations, the substrate further includes a third interconnect embedded in the first surface of the first dielectric layer, and a fourth interconnect on the first surface of the first dielectric layer. The first interconnect and the second interconnect are adjacent interconnects. In some implementations, the substrate further includes a first pad on the first surface of the first dielectric layer. The first pad is coupled to the first interconnect.

Abstract: The present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device comprises: providing a silicon substrate having a gate stack structure formed thereon and having {100} crystal indices; forming an interlayer dielectric layer coving a top surface of the silicon substrate; forming a first trench in the interlayer dielectric layer and/or in the gate stack structure, the first trench having an extension direction being along <110> crystal direction and perpendicular to that of the gate stack structure; and filling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile stress dielectric layer. The present invention introduces a tensile stress in the transverse direction of a channel region by using a simple process, which improves the response speed and performance of semiconductor devices.

Abstract: A method of fabricating a semiconductor device, comprising: forming a plurality of memory cell strings; coupling an interconnection to at least two of the memory cell strings; and coupling a bitline to the interconnection. The interconnection includes a body extending along a first direction and a protrusion protruding from the body along a second direction.

Abstract: The invention relates to a method of etching a layer of porous dielectric material, characterized in that the etching is performed in a plasma formed from at least one silicon-based gas mixed with oxygen (O2) and/or nitrogen (N2) so as to grow a passivation layer all along said etching, at least on flanks of the layer of porous dielectric material and wherein the silicon-based gas is taken from all the compounds of the type SixHy for which the ratio x/y is equal or greater than 0.3 or is taken from all the compounds of the following types: SixFy and SixCly, where x is the proportion of silicon (Si) in the gas and y is the proportion of fluorine (F) or chlorine (Cl) or hydrogen (H) in the gas.