Abstract: A system determines an event location of an event within an indoor environment based on an event sound generated by the event. The system employs time-reversal techniques based on a received event sound to identify the event location as being in the vicinity of one of a plurality of locator devices at locator locations in the environment. The system includes a base array located within the environment that receives an indication that an event has been detected. Upon receiving the event sound, the system generates a time-reversed event sound for each transceiver and transmits via each transceiver the time-reversed event sound for that transceiver. When a locator device receives a time-reversed event sound, the locator device determines whether the event is in the vicinity of that locator location of the locator device and, if so, outputs an indication that the event occurred at that locator location.

Abstract: A current frame in a sequence is encoded at a first bitrate to generate one or more encoded source frames. One or more previous frames in the sequence are encoded at a second bitrate that is lower than the first bitrate to generate one or more encoded FEC frames. The one or more encoded source frames and the one or more encoded FEC frames are packetized into one or more data packets.

Abstract: According to one embodiment, a memory system manages a plurality of parallel units each including blocks belonging to different nonvolatile memory dies. When receiving from a host a write request designating a third address to identify first data to be written, the memory system selects one block from undefective blocks included in one parallel unit as a write destination block by referring to defect information, determines a write destination location in the selected block, and writes the first data to the write destination location. The memory system notifies the host of a first physical address indicative of both of the selected block and the write destination location, and the third address.

Abstract: This application discloses an information processing method and apparatus, a communications device, and a communications system. The method includes: encoding an input sequence by using a low-density parity-check (LDPC) matrix, to obtain a bit sequence D, where a base matrix of the LDPC matrix is represented as a matrix of m rows and n columns, each column corresponds to a group of Z consecutive bits in the bit sequence D, and n and Z are both integers greater than 0; and obtaining an output bit sequence based on a bit sequence V, where the bit sequence V is obtained by permuting two groups of bits corresponding to at least two parity check columns in the bit sequence D.

Abstract: An error correction circuit includes ECC encoder and an ECC decoder. The ECC encoder generates, based on a first main data obtained by selectively shifting data bits of a main data based on a LSB of a row address, a parity data using an ECC and stores a codeword including the main data and the parity data in a target page. The ECC decoder generates a syndrome based on a second main data obtained by selectively shifting data bits of the main data based on the LSB of the row address, the parity data and a parity check matrix based on the ECC, and corrects a single bit error or corrects two bit errors when the two bit errors occur in adjacent two memory cells based on the syndrome. The mis-corrected bit is generated when the multiple error bits are present in the main data.

Abstract: A memory system includes a non-volatile memory configured to store an N-dimensional error correction code and a memory controller.

Abstract: Devices, systems, and methods for detecting and mitigating oscillations in a bit-flipping decoder associated with a non-volatile memory are described. An example method includes receiving a noisy codeword based on a transmitted codeword generated from a low-density parity-check code, performing a first plurality of decoding iterations on the noisy codeword, which comprises performing a message passing algorithm in a first order, computing, based on a completion of the first plurality of decoding iterations, a plurality of checksum values and a plurality of bit flip counts corresponding to the first plurality of decoding iterations, determining that the plurality of checksum values and the plurality of bit flip counts are periodic with a period less than a predetermined threshold, and performing a subsequent decoding iteration on the noisy codeword, the subsequent decoding iteration comprising performing the message passing algorithm in a second order different from the first order.

Abstract: Methods for data storage on polymers are provided. In various embodiments, an erasure error correcting code is selected. Input data is read from an input file. The erasure error correcting code is applied to the input data to generate a code word. The code word is encoded according to a chemical alphabet. A number of cycles required for synthesis is determined for the code word. The encoded code word is screened according to the number of cycles. The code word is retained where passing the screening.

Abstract: Described herein is a method for improving the reception of a satellite navigation message divided in several pages and transmitted by one or several satellites. A satellite navigation message M of k pages is encoded inn pages, and any k retrieved pages from any satellite enables decoding of the original satellite navigation message M. An implementation of the method uses parallel block encoding for a binary erasure channel with high parity and zero overhead, where symbols at a fixed position of all pages are encoded in parallel into shorter codes. This method achieves full page interchangeability in the message transmission, optimizes message reception and reduces decoding cost.

Abstract: A signal transmission method includes: combining a plurality of low-order modulated signals into N modulated signals; and transmitting the N modulated signals on N subcarriers, where the N subcarriers are subcarriers on frequency domain resources of M channels, an nth modulated signal in the N modulated signals is transmitted on an nth subcarrier in the N subcarriers, N is an integer greater than or equal to 2, M is an integer greater than or equal to 2, and n=1, 2, . . . , N. The signal transmission method can improve efficiency of a diversity gain.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a random access memory and a controller. When writing n?1 data portions of a first unit that are included in n?1 error correction code frames of a first size, respectively, in the nonvolatile memory, the controller generates a second error correction code that constitutes an error correction code frame of a second size together with the n?1 data portions of the first unit and a second data portion to be written into the nonvolatile memory by encoding the n?1 data portions of the first unit and the second data portion, and writes the second data portion and the second error correction code into the nonvolatile memory.

Abstract: Techniques related to improving power consumption of an LDPC decoder are described. In an example, the LDPC decoder uses a message passing algorithm between variable nodes and check nodes. A check node processing unit that generates check node to variable node messages implements a plurality of check node processing mode. Operation in each mode consumes a certain amount of power while providing a certain accuracy. Depending on a reliability of a variable node to check node message received by the check node processing unit, an appropriate check node processing mode is selected and used to generate a corresponding check node to variable node message. The reliability can be estimated for a set of variable node to check node messages based on, for instance, syndrome-related parameters.

Abstract: A data generation method includes: with regard to a target in which a plurality of sets of reference source data and reference target data are connectable by using edges, extracting information that corresponds to a complete bipartite graph from the connected target; and when there are a plurality of sets of reference source data and a plurality of sets of reference target data that are the extracted information and that constitute the complete bipartite graph, generating a virtual node between the reference source data and the reference target data.

Abstract: An LDPC parity check matrix, includes a systematic portion having a plurality of systematic elements having a value, the value each systematic element determining a cyclic shift to be applied to rows of an identity submatrix corresponding to that element; and a parity portion having a plurality of panty elements having a value, the value of each parity element determining a cyclic shift to be applied to rows of an identity submatrix corresponding to that element; wherein the weights of each column of a group of columns of the parity portion is the same. The LDPC parity check matrix may be used for data access, communication and storage, and may be used, for example for communications among a plurality of network nodes.

Abstract: A controller includes an Error Correction Code (ECC) encoder adding a first parity to data to generate a data set, and encoding the data set to generate a first parity data set, a buffer temporarily storing the first parity data set, an ECC decoder decoding the first parity data set received from the buffer to generate a decoded data set, a first checker performing a Low Density Parity Check (LDPC) encoding on the decoded data set to generate an LDPC data set to which a second parity is added, and a second checker performing a syndrome check operation on the LDCP data set including the first and second parities.

Abstract: Devices, systems and methods for convolutional precoding and decoding of polar codes are disclosed. An example method for error correction in a data processing system includes receiving a noisy codeword, the codeword having been generated based on an outer stream decodable code and an inner polar code and provided to a communication channel or a storage channel prior to reception by the decoder, the stream decodable code characterized by a trellis, and performing, based on the trellis, a list-decoding operation on the noisy codeword vector to generate a plurality of information symbols, the list-decoding operation being configured to traverse through a plurality of states at one or more stages of a plurality of decoding stages.

Abstract: Aspects of the disclosure relate to wireless communication devices configured to generate polar codewords utilizing a single master sequence constructed using density evolution with a nested structure for identifying the frozen bit locations and information bit locations. This single master sequence may be used for any codeword length N up to a maximum codeword length Nmax, and may further be utilized for any code rate R. For example, from the master sequence of length Nmax, a bit location sequence S with codeword length N (where N<Nmax) may be obtained by selecting the bit locations (indexes) in the master sequence corresponding to each bit location in S in the order provided in the master sequence.

Abstract: A method includes receiving a data object for storage in a storage system. The storage system includes a number of datacenters (s) interconnected by a first network. Each of the datacenters is located in a geographic location that is different than any geographic locations of any other of the datacenters. The method includes creating secondary copies of the data object. A number of secondary copies is equal to at least s?1. The method includes, in accordance with a placement map of at least one of the datacenters, storing a primary copy of the data object in one of the datacenters. The method also includes, in each other of the datacenters, storing at least one of the secondary copies. The method also includes monitoring, via a plurality of data monitors, an accessibility of data stored in the storage system. The data includes the primary copy and the secondary copies of the data objects.

Abstract: A data transmission method includes: obtaining Q first code block streams, wherein Q is an integer greater than 1, the coding type is M1/N1 bit coding, and one code block in the first code block stream comprises a synchronization header area of (N1?M1) bits and a non-synchronization one code block in the second code block stream comprises a synchronization header area of (N1?M1) bits and a non-synchronization header area of M1 bits, and a non-synchronization header area of a code block in the Q first code block streams is carried in a non-synchronization header area of a code block in the second code block stream. header area of M1 bits; and placing non-synchronization header areas of code blocks in the Q first code block streams into a to-be-sent second code block stream, wherein a coding type of the second code block stream is M1/N1 bit coding.

Abstract: A technique for efficient scheduling of operations in a program for parallelized execution thereof using a multi-processor runtime environment having two or more processors includes constraining the type or number of loop optimization transforms that may be explored such that memory and processing capacity available for the scheduling task are not exceeded, while facilitating a tradeoff between memory locality, parallelization, and/or data communication between memory modules of the multi-processor runtime environment.

Abstract: Described is a method of processing a signal received at an uplink control information (UCI) receiver in a wireless communication system. The method comprises processing a signal received on an uplink (UL) at said UCI receiver to transform said received signal into a likelihood calculation of possible transmitted codewords (?1 . . . ?i . . . ?N) and determining a maximum magnitude ?max value from said likelihood calculation. The method includes comparing said maximum magnitude ?max value to a selected, calculated or predetermined scaled threshold S·? where ? is a threshold and S is a scaling factor for the threshold ?. The comparison step is such that, where |?max|2>S·?, the method comprises determining that the signal received comprises a linear block encoded signal. In the method, prior to said comparison step, the scaling factor S is selected from a plurality of scaling factor options.

Abstract: Methods and systems are described for obtaining a plurality of information bits, and responsively partitioning the obtained plurality of information bits into a plurality of subsets of information bits, generating a plurality of streams of forward error correction (FEC)-encoded bits using a plurality of FEC encoders receiving respective subsets of the plurality of subsets of information bits, providing the plurality of streams of FEC-encoded bits to a plurality of sub-channel encoders, each sub-channel encoder receiving a respective stream of FEC-encoded bits from a different FEC encoder of the plurality of FEC encoders for generating a set of codewords of a vector signaling code, and wherein sequential streams of FEC-encoded bits from a given FEC encoder are provided to different sub-channel encoders for each successively generated set of codewords, and transmitting the successively generated sets of codewords of the vector signaling code over a multi-wire bus.

Abstract: Provided are a processing method and device for quasi-cyclic low density parity check (LDPC) coding. The processing method for LDPC coding includes: determining, according to a data feature of an information bit sequence to be encoded, a processing strategy for the quasi-cyclic LDPC coding according to a data feature of an information bit sequence to be encoded; and performing, according to the processing strategy and based on a base matrix and a lifting size, the quasi-cyclic LDPC coding and rate matching output on the information bit sequence according to the processing strategy, a base matrix and a lifting value. This technical solution is able to improve adaptability and flexibility of the quasi-cyclic LDPC coding.

Abstract: A system includes a memory array with memory cells and a processing device coupled thereto. The processing device performs program targeting operations that include to: determine a set of difference error counts corresponding to programming distributions of the memory array; identify, based on a comparison of the set of difference error counts, valley margins corresponding to the programming distributions; select, based on values of the valley margins, a program targeting rule from a set of rules; perform, based on the program targeting rule, a program targeting operation to adjust a voltage level associated with an erase distribution of the memory array; determine a bit error rate (BER) of the memory array; in response to the BER satisfying a BER control value, reduce the voltage level by a voltage step; and in response to the BER not satisfying the BER control value, increase the voltage level by the voltage step.

Abstract: A method and system for rate matching in a wireless communication system is disclosed. The method comprises receiving K information bits at a channel encoder and generating N output bits. The N output bits may be interleaved by an interleaver. In a HARQ retransmission the output bits may be placed into a circular buffer. The N output bits may be divided into two or more parts comprising at least a first part and a second part. The method further comprises mapping a first part of one or more parts of the N output bits to a M1 (=2m1)-ary modulation and mapping a second part of one or more parts of the N output bits to a M2 (=2m2))-ary modulation. The output bits may be transmitted by a wireless transmit/receive unit (WTRU), a base station, or the like.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.

Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method.

Abstract: At a physical data-link in a network, a current status of a plurality of logical data-channels in the network is determined, using machine learning to infer the current status. A plurality of cross-layer error correction coding schemes for transmissions is adaptively adjusted, based on the determined current status, and based on an application transmitting data. Transmission of the data, and a plurality of information-exchange requirements, are supported, using the adaptively adjusted plurality of error correction coding schemes.

Abstract: Provided is a signal interleaving method which includes: interleaving parity bits by encoding input bits based on a low density parity check (LDPC) code according to a code rate of 6/15 and a code length of 64800; splitting a codeword comprising the input bits and the interleaved parity bits into a plurality of bit groups; interleaving the plurality of bit groups according to a specific permutation order to provide an interleaved codeword; de-multiplexing bits of the interleaved codeword to generate data cells; mapping the data cells onto constellation points for 1024-quadrature amplitude modulation (QAM); and transmitting a signal based on the constellation points.

Abstract: A device is disclosed. The device may include an input buffer to receive a first low bit width message. A reconstruction circuit may implement a reconstruction function on the first low bit width message, producing a first high bit width message. A computation circuit may implementing a computation function on the first high bit width message, producing a second high bit width message. A quantization circuit may implementing a quantization function on the second high bit width message, producing a second low bit width message. A decision buffer may then store the second low bit width message. The reconstruction function and the quantization function may vary depending on an iteration and a layer of the device.

Abstract: An encoding apparatus is provided. The encoding includes a low density parity check (LDPC) encoder which performs LDPC encoding on input bits based on a parity-check matrix to generate an LDPC codeword formed of 64,800 bits, in which the parity-check matrix includes an information word sub-matrix and a parity sub-matrix, the information word sub-matrix is formed of a group of a plurality of column blocks each including 360 columns, and the parity-check matrix and the information word sub-matrix are defined by various tables which represent positions of value one (1) present in every 360-th column.

Abstract: Embodiments of this application provide a data transmission method, a communications device, and a storage medium to reduce a quantity of cross-connections of an intermediate node in a network. In the embodiments of this application, Q first code block streams that are obtained are multiplexed into one second code block stream for transmission, a coding type of the first code block streams is M1/N1 bit coding, a coding type of the second code block stream is M2/N2 bit coding, and bits corresponding to code blocks in the Q first code block streams are carried in a payload area of a code block in the second code block stream. In other words, in the solutions provided by the embodiments of this application, the code block streams are multiplexed and demultiplexed based on a code block granularity.

Abstract: Provided are an encoding method and device, a decoding method and device, and a storage medium. The encoding method comprises: encoding an initial to-be-encoded bit sequence with a low density parity check code LDPC having a code rate R1, to obtain an encoded first bit sequence, where 0?R1?1; linearly combining at least two bit sequence segments in the first bit sequence to obtain a second bit sequence; and cascading the first bit sequence and the second bit sequence to obtain a target bit sequence having a code rate R2, where 0?R2?R1?1.

Abstract: Various embodiments provide for encoding and decoding data channel information with polar codes where the frozen bits of the information block can be set to a scrambling identifier based on the device ID, cell ID, or some other unique identifier instead of being set to null. The frozen bits can be identified based on the type of polar code being used, and while the non-frozen bits can be coded with the data link data, the frozen bits can be coded with the scrambling identifier. In an example where there are more frozen bits than bits in the scrambling identifier, the most reliable of the frozen bits can be coded with the scrambling identifier. In another example, the frozen bits can be set to the CRC bits, which can then be masked by the scrambling identifier.

Abstract: A machine-implemented method of constructing multidimensional constellations having increased minimum distances between the constellation symbols thereof compared to those of comparable conventional constellations, e.g., QPSK and QAM constellations. An example multidimensional constellation so constructed may have eight or more dimensions and may be mapped onto degrees of freedom selected from, e.g., time, space, wavelength, polarization, and the in-phase and quadrature-phase components, of the optical field. The disclosed method is beneficially used to generate multidimensional modulation formats characterized by constant total optical transmit power per modulation time slot and/or applicable to the transmission of multidimensional constellation symbols having separate parts thereof primarily carried by different respective guided modes of the optical fiber. Example methods and apparatus for implementing such multidimensional modulation formats are also disclosed herein.

Abstract: A hardware efficient implementation of a threshold modified attenuated min-sum algorithm (TAMSA”) and a threshold modified offset min-sum algorithm (“TOMSA”) that improve the performance of a low density parity-check (“LDPC”) decoder by reducing the bit error rate (“BER”) compared to the conventional attenuated min-sum algorithm (“AMSA”), offset min-sum algorithm (“OMSA”), and the min-sum algorithm (“MSA”). Embodiments of the present invention preferably use circuit optimization techniques, including a parallel computing structure and lookup tables, and a field-programmable gate array (“FPGA”) or application specific integrated circuit (“ASIC”) implementation.

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to perform a low-density parity check (LDPC) encoding on input bits using a parity check matrix to generate an LDPC codeword comprising information word bits and parity bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Abstract: Read parameter estimation techniques are provided that obtain information from multiple read operations to customize read parameters for data recovery. One method comprises performing the following steps, in response to a decoding failure of a page of a memory or a codeword of the memory: obtaining at least three read values of the page or codeword; and processing the at least three read values to determine read parameters comprising: (i) a log likelihood ratio, and/or (ii) a center read reference voltage, wherein the determination is based on a signal count of a number of bits falling in particular regions of multiple regions of the memory and wherein the determined read parameters are used for a decoding of the page or codeword following the decoding failure and/or a subsequent read operation following a successful decoding of the page or codeword.

Abstract: The inventive concept provides a security device capable of reducing an area of a die required for implementation of a stable PUF by increasing the value of entropy from a predefined number of entropy sources and/or minimizing a blind zone of a validity checking module. The security device uses an asynchronous configuration to minimize a blind zone. In various embodiments of the inventive concept, the blind zone is generated only in a period when a reset signal is at a first logic level. Therefore, it is possible to minimize the blind zone by minimizing a period in which the reset signal is at such logic level. A semiconductor device, semiconductor package, and/or smart card can be provided with such security device, as well as a method for determining a validity of a random signal using a semiconductor security device.

Abstract: A data transmission method includes generating a physical layer data frame, where the physical layer data frame includes data on which probability non-uniform modulation is performed and indication information, where the indication information indicates demodulation parameters for performing probability non-uniform demodulation on the data, where the demodulation parameters include a modulation scheme for probability non-uniform modulation, a modulation order for probability non-uniform modulation, and at least one of a probability of each constellation symbol on which probability non-uniform modulation is performed, or a mapping relationship between each constellation symbol on which probability non-uniform modulation is performed and a bit stream, sending the physical layer data frame to a receive end, receiving the physical layer data frame, determining the demodulation parameters based on the indication information, and performing probability non-uniform demodulation on the data based on the demodulation

Abstract: Systems, methods, and apparatus related to memory devices such as solid state drives. In one approach, data is received from a host system (e.g., data to be written to an SSD). The received data is encoded using a first error correction code to generate first parity data. A temperature at which memory cells of a storage device (e.g., the SSD) will store the received data is determined. In response to determining the temperature, a first portion of the received data is identified (e.g., data in memory storage that is error-prone at a predicted higher temperature that has been determined based on output from an artificial neural network using sensor(s) input). The identified first portion is encoded using a second error correction code to generate second parity data. The second error correction code has a higher error correction capability than the first error correction code. The encoded first portion, the first parity data, and the second parity data are stored in the memory cells of the storage device.

Abstract: Techniques for receiving data at a physical coding sublayer (PCS) transmit structure from a media access control (MAC) sublayer are provided. A PCS transmit structure is configured to receive data from a MAC sublayer, the PCS transmit structure comprising a first FEC hardware module that performs FEC encoding, in a first clock domain, on the data to generate FEC encoded data. Further, a PCS receive structure configured to receive the FEC encoded data from the PCS transmit structure, the PCS receive structure comprising a second FEC hardware module is configured to perform FEC decoding, in the second clock domain, on the FEC encoded data to generate FEC decoded data.

Abstract: Apparatuses and methods are disclosed for a communication device associated with a wireless transmission. In one embodiment, a method includes performing one of a low-density parity check, LDPC, decoding process and an LDPC encoding process by loading a set of bits, in parallel, into a plurality of registers, the set of bits being distributed among the plurality of registers; one of de-interleaving and interleaving the loaded set of bits within the plurality of registers by rearranging the loaded set of bits into one of a de-interleaved and an interleaved set of bits; and after the set of bits is rearranged into the one of the de-interleaved and the interleaved set of bits within the plurality of registers, writing the one of the de-interleaved and the interleaved set of bits, in parallel, from the plurality of registers to memory.

Abstract: Embodiments of this application disclose provides a low density parity check (LDPC) channel encoding method for use in a wireless communications system. A communication device encodes an input bit sequence by using a LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. Embodiments of the application provide eight particular designs of the base matrix. The encoding method provided in the embodiments of the application can be used in various communications systems including the fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths.

Abstract: A remote service system includes a first computer terminal configured to add a first signature to control information representing control content to be applied to a facility and transmit the control information and a second computer terminal configured to cause the control content represented by the control information to be applied to the facility, wherein the first computer terminal and the second computer terminal are connected by a first communication network and wherein the second computer terminal and the facility are connected by a second communication network.

Abstract: Memory controllers bit-flipping (BF) decoders and methods that selectively apply a checksum-aided error reduction (CA-ER) scheme to BF decoding of a low-density parity-check (LDPC) code. In decoding a codeword, a hard decision value resulting from decoding a select variable node is changed when a first condition is satisfied to yield an updated hard decision value. Also, when the first condition is satisfied, a current checksum value after processing the select variable node is updated using the updated hard decision value. The CA-ER scheme is applied when the updated checksum value is not reduced to a set minimum and a second condition based on a previous checksum value, calculated after a previous variable node is processed, is satisfied.

Abstract: This invention presents a method and the corresponding hardware apparatus for decoding LDPC codes using a vertical layered (VL) iterative message passing algorithm. The invention operates on quasi-cyclic LDPC (QC-LDPC) codes, for which the non-zero circulant permutation matrices (CPMs) are placed at specific locations in the parity-check matrix of the codes, forming concentrated clusters of CPMs. The purpose of the invention is to take advantage of the organization of CPMs in clusters in order to derive a specific hardware architecture, consuming less power than the classical VL decoders. This is achieved by minimizing the number of read and write accesses to the main memories of the design.

Abstract: A hard-decision (HD) forward error correcting (FEC) coded signal is decoded by a decoder to produce decoded bits using marked reliable bits of the HD-FEC coded signal and marked unreliable bits of the HD-FEC coded signal. The marked reliable and unreliable bits are computed by calculation and marking blocks based on an absolute value of log-likelihood ratios of the HD-FEC coded signal. The HD-FEC coded signal may be, for example, a staircase code coded signal or a product code coded signal.

Abstract: A system and method for erasure coding. The method includes distributing a plurality of data chunks according to a mirroring scheme, wherein the plurality of data chunks is distributed as a plurality of rows among a plurality of non-volatile memory (NVM) nodes, wherein the mirroring scheme defines a plurality of groups, each group including a subset of the plurality of data chunks, wherein each data chunk in a group has a role corresponding to a relative position of the data chunk within the group, wherein data chunks included in the plurality of groups having the same relative positions within their respective groups have the same role, wherein each row of the plurality of rows includes at least one summation data chunk that is a function of at least one data chunk included in the row and of at least one extra data chunk included in at least one other row.

Abstract: Disclosed is a method for transmitting a broadcast signal. The method comprises formatting input streams with multiple data transmission channels, and the formatting step comprises adding a header indicating a format of a payload of the BBF.