Abstract: The present technology relates to a data processing device and a data processing method capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code having a code length N of 64800 bits and a coding rate r of 9/15, 11/15, or 13/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of LDPC codes after the group-wise interleave is returned to an original sequence. The present technology, for example, can be applied to a case where data transmission using an LDPC code or the like is performed.

Abstract: Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method by a transmitting device generally includes selecting a first lifting size value and a first set of lifting values; generating a first lifted LDPC code by applying the first set of lifting values to interconnect edges in copies of a parity check matrix (PCM) having a first number of variable nodes and a second number of check nodes; determining a second set of lifting values for generating a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values; encoding a set of information bits based the first lifted LDPC code or the second lifted LDPC code to produce a code word; and transmitting the code word.

Abstract: Methods and devices for performing rate adaptive forward error correction using a flexible irregular error-correcting code, such as a staircase code. Each codeword of the ECC uses one of two or more different encodings, each encoding having a different number of parity bits. By adjusting the proportions of codewords of each encoding included in a data block, the FEC overhead can be finely adjusted, achieving flexible levels of FEC overhead in response to increased or decreased noise or perturbations in a communication channel. Three types of flexible irregular zipper codes are described: general zipper codes, staircase codes, and oFEC codes.

Abstract: Methods and Apparatus for processing data encoded by low density parity check (LDPC) in a communication system are disclosed herein. In one embodiment, a method performed by a first node is disclosed. The method comprises: encoding an information bit sequence based on an LDPC coding scheme to obtain an encoded bit sequence; generating a master bit sequence based on the encoded bit sequence; selecting a subset of the master bit sequence according to a rate matching rule to obtain a rate matched bit sequence; interleaving the rate matched bit sequence according to a predetermined index sequence to obtain a to-be-transmitted bit sequence; and transmitting the to-be-transmitted bit sequence to a second node.

Abstract: Wireless communication devices are adapted to facilitate information sequences included in frozen sub-channels of polar coded transmissions. According to one example, an apparatus can generate a mask sequence based on a plurality of parameters, including at least one of a transmitting-device-specific sequence or a receiving-device-specific sequence. In some examples, the frozen bits may be masked with the mask sequence, and an information block may be encoded utilizing polar coding. In other examples, the mask sequence may be compared to the frozen bits of a received information block, and the received information block may be determined as intended for the apparatus when the mask sequence matches to the frozen bits. Other aspects, embodiments, and features are also included.

Abstract: A method for execution by a processing module of a distributed storage includes transmitting a request to retrieve a set of encoded data slices (EDSs) to a plurality of storage nodes followed by receiving a threshold number of EDSs from one or more of the plurality of storage nodes, and decoding the EDSs to produce a transposed encrypted data segment. The method continues with the processing module partitioning the encrypted data segment into an encoded encryption key and encrypted data, performing a hash function on the encrypted data to produce a digest resultant and combining the digest resultant with the encoded encryption key to generate combined key data. The method then continues with decoding the combined key data to recover an encryption key and decrypting the encrypted data using the encryption key to recover a data segment.

Abstract: Provided in an embodiment of the invention are a method for transmitting data, a receiving-end device, and a transmitting-end device. The method comprises: a receiving-end device receiving, on a time unit, a first part and at least one second part of data, wherein first modulation and coding processing is performed on the first part, and second modulation and coding processing is performed on the at least one second part; and the receiving-end device performing demodulation on the first part and the at least one second part. The method for transmitting data, the receiving-end device, and the transmitting-end device provided in the embodiment of the invention achieve a higher frequency spectrum efficiency, thereby realizing fast demodulation.

Abstract: An image processing system comprises a first image processing apparatus and a second image processing apparatus. The first image processing apparatus obtains image data and transmits, to the second image processing apparatus, the obtained image data and information relating to the image data. The second image processing apparatus receives the image data and sets a condition for determining whether the image data is the image data to be processed, and determines whether or not the received image data is the image data to be processed, based on the set condition and the information. The second image processing apparatus executes, when it is determined that the received image data is the image data to be processed, image processing on the image data, based on the information and stores a result of the execution of the image processing.

Abstract: The present technology relates to a data processing apparatus and a data processing method which enable provision of an LDPC code that achieves good error-rate performance. An LDPC encoding unit performs encoding using an LDPC code having a code length of 64800 bits and a code rate of 24/30, 25/30, 26/30, 27/30, 28/30, or 29/30. The LDPC code includes information bits and parity bits, and a parity check matrix H is composed of an information matrix portion corresponding to the information bits of the LDPC code, and a parity matrix portion corresponding to the parity bits. The information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table that shows positions of elements of 1 in the information matrix portion in units of 360 columns. The present technology may be applied to LDPC encoding and LDPC decoding.

Abstract: The present technology relates to a transmission device, a transmission method, a reception device, and a reception method for securing good communication quality in data transmission using an LDPC code. The LDPC coding is performed on the basis of the parity check matrix of the LDPC code with the code length N of 17280 bits and the coding rate r of 9/16 or 10/16. The LDPC code includes information bits and parity bits, and the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits. The information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix for every 360 columns. The present technology can be applied to data transmission using an LDPC code.

Abstract: Disclosed are: a communication technique for merging, with IoT technology, a 5G communication system for supporting a data transmission rate higher than that of a 4G system; and a system therefor. The present disclosure can be applied to intelligent services (for example, smart home, smart building, smart city, smart car or connected car, healthcare, digital education, retail, security and safety related services, and the like) on the basis of 5G communication technology and IoT-related technology.

Abstract: A method, an apparatus and an equipment for determining a transport block size are provided. The method for determining a transport block size includes: determining an initial transport block size; comparing the initial transport block size with a threshold to obtain a comparison result; quantizing the initial transport block size based on the comparison result to obtain a quantized initial transport block size; and determining a final transport block size based on the quantized initial transport block size.

Abstract: An apparatus for determining a bit index for a parity bit of a polar codeword is disclosed. Each index of a polar codeword may have an associated weight and an associated reliability value. The apparatus may compare the weights and reliability values of a group of bit indices in parallel to determine a bit index of the group associated with the lowest weight and highest reliability value. Additional groups may be processed until all of the bit indices of the polar codeword have been examined and the bit index with the lowest weight and highest reliability value is identified.

Abstract: A transmission method and a reception device for securing favorable communication quality in data transmission using an LDPC code. In group-wise interleaving, the LDPC code with a code length N of 69120 bits is interleaved in units of 360-bit bit groups. In group-wise deinterleaving, a sequence of the LDPC code after group-wise interleaving is returned to an original sequence.

Abstract: A method including determining a cyclic redundancy check (CRC) generator sequence defining a one to one mapping between a sequence of control information values and cyclic redundancy check (CRC) sequence values; and determining a combined sequence, the combined sequence formed by distributing the cyclic redundancy check (CRC) value sequence within the sequence of control information values, wherein the distributing the cyclic redundancy check (CRC) value sequence within the sequence of control information values is based on a selected part of the cyclic redundancy check (CRC) generator sequence.

Abstract: Aspects of the present application provide methods and devices for using a combined QAM and APSK modulation scheme in a hybrid modulation form in order to benefit from advantages of each respective modulation scheme. The proposed hybrid modulation scheme is less sensitive to phase noise and has lower PAPR than QAM and has very similar performance as QAM with respect to AWGN.

Abstract: A parity check matrix managing technology generating and modifying parity check matrix for encoding and decoding data to be processed in a communication system, memory system, and the like is disclosed. A parity check matrix managing apparatus may include an input device configured to receive a parity check matrix as a modification target; a matrix modifier configured to modify the parity check matrix by performing at least one of a cyclic shift on unit components of at least one row or column in the parity check matrix and a location change between at least two rows or columns in the parity check matrix to generate a modified parity check matrix; and a controller configured to control the matrix modifier to compare a matrix size of the modified parity check matrix with a set matrix size, so that the matrix size is less than or equal to the set matrix size.

Abstract: A data storage device includes a nonvolatile memory device configured to read and output a plurality of data chunks; and a data processing block configured to perform decoding on the data chunks, the data processing block comprising a sequencer configured to generate a decoding information on the data chunks; and a core circuit configured to perform normal decoding on a first data chunk among the data chunks based on the decoding information, and perform fast decoding on a second data chunk among the data chunks depending on whether a result of the normal decoding satisfies a fast decoding condition, wherein the fast decoding requires a shorter execution time than the normal decoding.

Abstract: An LDPC (Low-Density Parity Check) code based on a control matrix represented by a Tanner bipartite graph includes 128 variable nodes of the graph and 64 constraint nodes of the graph, the code being wherein each of the constraint nodes of the graph is connected to 7 variable nodes of the graph; each of the cycles of the graph has a length greater than or equal to 6; the minimum distance of the code is equal to or greater than a predefined threshold for minimum distance.

Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.

Abstract: A method of soft decoding received signals. The method comprising defining quantisation intervals for a signal value range, determining a number of bits in each quantisation interval that are connected to unsatisfied constraints, providing, the number of bits in each quantisation interval that are connected to unsatisfied constraints, as an input to a trained model, wherein the trained model has been trained to cover an operational range of a device for soft decoding of signals, determining, using the trained model, a log likelihood ratio for each quantisation interval, and performing soft decoding using the log likelihood ratios.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-Generation (4G) communication system, such as long-term evolution (LTE). The disclosure provides decoding of a low-density parity-check (LDPC) code in a wireless communication system, and a decoding method of the LDPC code may include receiving a codeword, performing decoding iterations on the codeword a predefined maximum number of times using a parity check matrix, performing partial decoding using a partial area of the parity check matrix, and determining decoding success or failure of the codeword based a result of the partial decoding.

Abstract: The present technology relates to a transmission method and a reception device for securing favorable communication quality in data transmission using an LDPC code. In group-wise interleaving, the LDPC code with a code length N of 17280 bits is interleaved in units of 360-bit bit groups 0 to 47. In group-wise deinterleaving, a sequence of the LDPC code after group-wise interleaving is returned to an original sequence. The present technology can be applied, for example, in a case of performing data transmission using an LDPC code, and the like.

Abstract: According to some embodiments, a method of operation of a transmit node in a wireless communication system comprises performing polar encoding of a set of K information bits to thereby generate a set of polar-encoded information bits. The K information bits are mapped to the first K bit locations in an information sequence SN. The information sequence SN is a ranked sequence of N information bit locations among a plurality of input bits for the polar encoding where N is equivalent to a code length. A size of the information sequence SN is greater than or equal to K. The information sequence SN is optimized for the specific value of the code length (N). The method may further comprise transmitting the set of polar-encoded information bits.

Abstract: A system and method for using free space to improve erasure code locality. The method includes logically segmenting an erasure coding data set into a stripe based on an erasure coding scheme, wherein the erasure coding data set includes a plurality of chunks, wherein the plurality of chunks includes a plurality of chunks of systematic data and a plurality of chunks of parity data, wherein the stripe includes free user data; and distributing the stripe across a plurality of non-volatile memory nodes based on the erasure coding scheme, wherein the free user data is stored in at least one memory location among the plurality of non-volatile memory nodes, wherein each non-volatile node is a unit of non-volatile memory.

Abstract: Methods, systems and devices for forward error correction in orthogonal time frequency space (OTFS) communication systems using non-binary low-density parity-check (NB-LDPC) codes are described. One exemplary method for forward error correction includes receiving data, encoding the data via a non-binary low density parity check (NB-LDPC) code, wherein the NB-LDPC code is characterized by a matrix with binary and non-binary entries, modulating the encoded data to generate a signal, and transmitting the signal. Another exemplary method for forward error correction includes receiving a signal, demodulating the received signal to produce data, decoding the data via a NB-LDPC code, wherein the NB-LDPC code is characterized by a matrix with binary and non-binary entries, and providing the decoded data to a data sink.

Abstract: Disclosed is a method and apparatus for encoding an erasure code for storing data. The disclosed method for encoding an erasure code comprises the steps of: (a) generating a first local parity group including two or more local parity nodes for data nodes; (b) generating at least one global parity node for the data nodes; (c) generating at least one second local parity group including two or more local parity nodes for the data nodes; and (d) storing the data nodes, the first local parity group, the second local parity group, and the global parity node. According to the disclosed method, it is possible to store and recover data safely and efficiently.

Abstract: A method for iteratively decoding read bits in a solid state storage device, wherein the read bits are encoded with a Q-ary LDPC code defined over a binary-extension Galois field GF(2r) and having length N. The method comprises: determining a binary Tanner graph of the Q-ary LDPC code based on a binary coset representation of the Galois field GF(2r) the binary Tanner graph comprising (2r?1) binary variable nodes, (2r?1?r) binary parity-check nodes each one connected to one or more binary variable nodes according to the binary coset representation and (2r?1) binary check nodes each one connected to a respective binary variable node mapping the read bits into N symbols providing each symbol of the N symbols to a respective Q-ary variable node; providing each bit of the symbol to a respective binary variable node of the respective Q-ary variable node and iteratively decoding each symbol.

Abstract: Examples include techniques to use intrinsic information when implementing a bit-flipping algorithm. An error correction control (ECC) decoder uses the intrinsic information to decode a low density parity count (LDPC) codeword. The intrinsic information including bits of a copy of a received LDPC codeword are compared to bits for variable nodes during an iteration of the bit-flipping algorithm to aid a determination as whether one or more bits for the variable nodes are to be flipped.

Abstract: A processing device in a memory system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device determines a syndrome for the sense word using the plurality of parity check equation results, determines whether the syndrome for the sense word satisfies a codeword criterion, and responsive to the syndrome for the sense word not satisfying the codeword criterion, performs an iterative LDPC correction process, wherein at least one iteration after a first iteration in the LDPC correction process uses a criterion based at least partially on a previous iteration or partial iteration.

Abstract: Disclosed herein is a decoder 10 for decoding a family of L rate compatible parity check codes, said family of parity check codes comprising a first code that can be represented by a bipartite graph having variable nodes, check nodes, and edges, and L?1 codes of increasingly lower code rate, among which the i-th code can be represented by a bipartite graph corresponding to the bipartite graph representing the (i?1)-th code, to which an equal number of ni variable nodes and check nodes are added, wherein the added check nodes are connected via edges with selected ones of the variable nodes included in said i-th code, while the added variable nodes are connected via edges with selected added check nodes only. The decoder comprising L check node processing units 14, among which the i-th check node processing unit processes only the check nodes added in the i-th code over the (i?1)-th code, wherein said L check node processing units 14 are configured to operate in parallel.

Abstract: Provided is an optical transmission/reception device including: an error correction encoding unit configured to encode a sequence to be transmitted with one type of LDPC code; and an error correction decoding unit configured to decode a received sequence encoded with the LDPC code. The error correction decoding unit performs decoding processing for the received sequence based on a check matrix of an LDPC convolutional code. The decoding processing is windowed decoding processing, which is performed by using a window extending over one or more check submatrices. A window size of the window and a decoding iteration count are configured to be variable, and the window size and the decoding iteration count are input from a control circuit connected to the error correction decoding unit.

Abstract: A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme.

Abstract: A particular overall architecture for transmission over a bonded channel system consisting of two interconnected MoCA (Multimedia over Coax Alliance) 2.0 SoCs (Systems on a Chip) and a method and apparatus for the case of a “bonded” channel network. With a bonded channel network, the data is divided into two segments, the first of which is transported over a primary channel and the second of which is transported over a secondary channel.

Abstract: The invention discloses a method for transmitting additional information using linear block codes, which comprises the following steps: when encoding: a linear block code C with a code length of n and an information bit length of k is used as a payload code, to embed an additional information sequence v of length m by superposition coding and resulting into a codeword c of length n. When decoding, firstly decode the additional information according to the received sequence y: select an additional information sequence with the largest characteristic metric function value as the decode output. Then perform payload information sequence decoding: remove the interference of superposition sequence ? from the received sequence y, and then use the basic linear block code C decoder to decode.

Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for low density parity check (LDPC)-based incremental redundancy (IR) hybrid automatic repeat request (HARQ) transmission processing. In one aspect, an apparatus for wireless communications is configured to generate a first packet using a LDPC encoding process. The apparatus is further configured to generate coded bits using a second LDPC encoding process if the first packet is not successfully decoded by a wireless device, generate a second packet including at least some of the coded bits generated using the second LDPC encoding process, and output the second packet for transmission.

Abstract: A low-density parity check convolution code (LDPC-CC) is made, and a signal sequence is sent after being subjected to an error-correcting encodement using the low-density parity check convolution code. In this case, a low-density parity check code of a time-variant period (3g) is created by linear operations of first to 3g-th (letter g designates a positive integer) parity check polynomials and input data.

Abstract: Memory controllers, decoders and methods perform decoding of a codeword comprising multiple bits. For a select one of those bits, which belongs to at least one component codeword of the codeword, at an iteration of decoding, the following operations are performed. Channel information for the select bit is biased based on degree of the select bit. A reliability indicator of an initial decision as to whether to flip the select bit is computed based on the initial decision and the biased channel information. The reliability indicator is compared with an adaptive threshold, which is determined based on the degree of the select bit and unsatisfied check (USC) information from the initial decision. A decision is then made as to whether to flip the select bit. The decision and syndromes of each component codeword to which the select bit belongs are updated based on the compare operation.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.

Abstract: Provided herein is an error correction decoder and a memory system having the same. The error correction decoder includes a memory configured to store a hard decision value of a variable node. The decoder further includes a flipping function value generator configured to generate, in an i-th iteration, a first value based on a number of unsatisfied check nodes (UCNs) corresponding to the variable node, and to generate a flipping function value as (i) a difference between the first value and an offset value or (ii) a set value, wherein i is a non-negative integer. The decoder also includes a comparator configured to output, in the i-th iteration, a first signal indicating whether to flip or not flip the hard decision value of the variable node in the memory based on comparing the flipping function value to a flipping threshold value.

Abstract: This application provides a polar code encoding method and apparatus. The method includes: obtaining, by a sending device, a sequence corresponding to a required mother code length; obtaining, by the sending device, a to-be-encoded bit; and performing, by the sending device, polar code encoding on the to-be-encoded bit by using the sequence corresponding to the required mother code length, to obtain an encoded bit, where the sequence is generated based on a basic sequence, and a length of the basic sequence is less than the mother code length.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

Abstract: A pre-5th-generation (pre-5G) or 5G communication system for supporting higher data rates beyond a 4th-generation (4G) communication system, such as long term evolution (LTE) is provided. A channel encoding method in a communication or broadcasting system includes identifying an input bit size, determining a block size (Z), determining a low density parity check (LDPC) sequence to perform LDPC encoding, and performing the LDPC encoding based on the LDPC sequence and the block size.

Abstract: A controller is provided to include a processor reading data from a memory device, and a decoder receiving the data and decoding the data, the data being represented with check nodes and variable nodes. The decoder includes a check unit calculating syndrome values, a calculation unit receiving the decision values of the variable nodes and calculating flipping function values, a setting unit receiving the flipping function values and generating a candidate vector by dividing the flipping function values into groups and selecting at least some maximum values from the groups, the setting unit setting a flipping function threshold value, and a flipping unit receiving the flipping function threshold value, comparing the flipping function values of the variable nodes with the flipping function threshold value, and flipping a decision value of a target variable node having a greater flipping function value than the flipping function threshold value.

Abstract: Embodiments of polar encoding/decoding methods and apparatuses are described. CRC encoding is performed on an information block to obtain a CRC encoded block with a length of B, where a CRC length is Lcrc, an information block length is K, and B=K+Lcrc. The CRC encoded block is interleaved. Lpc CRC bits in the interleaved encoded block are located between bits of the information block. Each CRC bit of the Lpc CRC bits is located after all bits checked by using the CRC bit. Lpc is an integer greater than 0 and less than Lcrc. The interleaved encoded block is mapped to information bits. A frozen bit is set to an agreed fixed value. Polar encoding is performed on the information bits and the frozen bit to obtain a polar encoded codeword to improve performance of a CA-polar code.

Abstract: Servicing I/O operations in a virtual storage system, including: receiving, by the virtual storage system, a request to write data to the virtual storage system; storing, within staging memory provided by one or more virtual drives of the virtual storage system, both the data and an erasure code based on the data; and migrating, from the staging memory to more durable data storage provided by a cloud services provider, at least a portion of data stored within the staging memory without migrating the erasure code based on the data.

Abstract: A base matrix of a rate-adaptive irregular QC-LDPC code is provided, the base matrix being formed by columns and rows having entries representing circulant submatrices. The columns of the base matrix are divided into at least one or more higher weight first columns and lower weight second columns and the rows of the base matrix are divided into first high weight rows corresponding to the high rate mother code and second low weight rows corresponding to the extension part related to the lower rate codes. A first submatrix formed by an intersection of entries of the second columns and entries of the first and the second rows is divided into first quadratic submatrices, wherein at most one entry in each column of each first submatrix and/or at most one entry in each row of each first submatrix is labelled.

Abstract: A method and apparatus for decoding are disclosed. The method includes receiving a first Forward Error Correction (FEC) block of read values, starting a hard-decode process in which a number of check node failures is identified and, during the hard-decode process comparing the identified number of check node failures to a decode threshold. When the identified number of check node failures is not greater than the decode threshold the hard-decode process is continued. When the identified number of check node failures is greater than the decode threshold, the method includes: stopping the hard-decode process prior to completion of the hard-decode process; generating output indicating that additional reads are required; receiving one or more additional FEC blocks of read values, mapping the first FEC block of read values and the additional FEC blocks of read values into soft-input values; and performing a soft-decode process on the soft-input values.

Abstract: Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, a high voltage version and a low voltage version of a decoder is used.

Abstract: A memory system includes a memory device including memory sets and a controller including a decoder. The decoder receives multiple codewords from the memory sets and decodes the multiple codewords. The decoder determines an inter-set delay for a codeword of a select memory set. When the inter-set delay is greater than a maximum inter-set delay, the decoder determines a total decoding time based on an effective inter-set delay and an effective decoding time. The decoder outputs the decoded codeword at the end of the total decoding time.