Combined With Electrical Contact Or Lead Patents (Class 257/734)
  • Patent number: 9978711
    Abstract: A semiconductor chip includes a semiconductor body having a lower side with a lower chip metallization applied thereto. A first contact metallization layer is produced on the lower chip metallization. A second contact metallization layer is produced on a metal surface of a substrate. The semiconductor chip and the substrate are pressed onto one another for a pressing time so that the first and second contact metallization layers bear directly and extensively on one another. During the pressing time, the first contact metallization layer is kept continuously at temperatures which are lower than the melting temperature of the first contact metallization layer. The second contact metallization layer is kept continuously at temperatures which are lower than the melting temperature of the second contact metallization layer during the pressing time. After the pressing together, the first and second contact metallization layers have a total thickness less than 1000 nm.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: May 22, 2018
    Assignee: Infineon Technologies AG
    Inventors: Gopalakrishnan Trichy Rengarajan, Christian Stahlhut
  • Patent number: 9972556
    Abstract: A system of producing metal cored solder structures on a substrate includes: a decal having a plurality of apertures, the apertures being tapered from a top surface to a bottom surface of the decal; a carrier configured for positioning beneath the bottom of the decal, the carrier having cavities in a top surface and the cavities located in alignment with the apertures of the decal; the decal being configured for positioning on the carrier having the decal bottom surface in contact with the carrier top surface to form feature cavities defined by the decal apertures and the carrier cavities, the feature cavities being shaped to receive a plurality of metal elements therein, the feature cavities configured for receiving molten solder being cooled in the cavities, the decal being separable from the carrier to partially expose metal core solder contacts; and receiving elements of a substrate being configured to receive the metal core solder contacts thereon, and the metal core solder contacts being exposed and pos
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: May 15, 2018
    Assignee: International Business Machines Corporation
    Inventors: Peter A. Gruber, Jae-Woong Nah
  • Patent number: 9966335
    Abstract: A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: May 8, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: NamJu Cho, HeeJo Chi, HanGil Shin
  • Patent number: 9954060
    Abstract: The present invention provides a method for aligning nanowires which can be used to fabricate devices comprising nanowires that has well-defined and controlled orientation independently on what substrate they are arranged on. The method comprises the steps of providing nanowires and applying an electrical field over the population of nanowires, whereby an electrical dipole moment of the nanowires makes them align along the electrical field. Preferably the nanowires are dispersed in a fluid during the steps of providing and aligning. When aligned, the nanowires can be fixated, preferably be deposition on a substrate. The electrical field can be utilized in the deposition. Pn-junctions or any net charge introduced in the nanowires may assist in the aligning and deposition process. The method is suitable for continuous processing, e.g. in a roll-to-roll process, on practically any substrate materials and not limited to substrates suitable for particle assisted growth.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: April 24, 2018
    Assignee: QUNANO AB
    Inventors: Lars Samuelson, Knut Deppert, Jonas Ohlsson, Martin Magnusson
  • Patent number: 9954355
    Abstract: A transient voltage suppressor (TVS) apparatus includes a plurality of input/output (I/O) pins, a plurality of ground pins, and a substrate. The substrate includes a plurality of division parts and a carrier part. The carrier part carries a chip. The division parts are disposed between each of the I/O pins and the ground pins. The chip is electrically connected to the I/O pins and the ground pins, and the division parts are electrically insulated from the I/O pins and the ground pins.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: April 24, 2018
    Assignee: UBIQ Semiconductor Corp.
    Inventor: Chih-Hao Chen
  • Patent number: 9950530
    Abstract: A first sealant for sealing a region under an electrical connection portion and a second sealant for sealing a region on the electrical connection portion are used as sealants for the electrical connection portion for connecting an electric wiring member to an ejection energy generation element of a liquid ejection head, these sealants contain the same base agent and curing agent, and the linear expansion coefficients of the first sealant and the second sealant after curing are adjusted so as to become in a predetermined range.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: April 24, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventor: Isao Imamura
  • Patent number: 9953999
    Abstract: In one embodiment, the semiconductor device includes a stack of alternating first interlayer insulating layers and gate electrode layers on a substrate. At least one of the gate electrode layers has a first portion and a second portion. The second portion forms an end portion of the at least one gate electrode layer, and a bottom surface of the second portion is at a lower level than a bottom surface of the first portion. A contact plug extends from the second portion.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: April 24, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Phil Ouk Nam, Sung Gil Kim, Seulye Kim, Hong Suk Kim, Jae Young Ahn, Ji Hoon Choi
  • Patent number: 9947684
    Abstract: A semiconductor device includes a substrate including a cell region and a connection region. A stack is disposed on the substrate. A vertical channel structure penetrates the stack in the cell region. The stack includes electrode patterns and insulating patterns which are alternatingly and repeatedly stacked on the substrate. Each of the electrode patterns may extend in a first direction and include a pad portion. The pad portion is positioned in the connection region. The pad portion includes a first sidewall and a second sidewall that extend in the first direction on opposite sides of the pad portion. The first sidewall has a recessed portion that is recessed in a second direction crossing the first direction toward the second sidewall.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: April 17, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joyoung Park, Yong-Hyun Kwon, Jeongsoo Kim, Seok-Won Lee, Jinwoo Park, Oik Kwon, Seungpil Chung
  • Patent number: 9947553
    Abstract: The present invention provides a semiconductor device and a method for manufacturing a semiconductor device. The method comprises: Preparing a semiconductor chip 6 with a first electrode layer 21 formed on an element-forming surface 7. Prepared a support member 30 having a conductor 31 formed on a pattern-forming surface 33. The first electrode layer 21 is bonded to the conductor 31 by a solder, and thus the semiconductor chip 6 is fixed on the support member 30. While the semiconductor chip 6 is fixed on the support member 30, the semiconductor chip 6 is coated by the sealing resin 3 to form a sealing structure 46. By removing the support member 30 from the sealing structure 46, the conductor 31 formed on the support member 30 is transferred to the sealing structure 46. The conductor 31 transferred to the sealing structure 46 is an external electrode exposed from the sealing structure 46.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: April 17, 2018
    Assignee: ROHM CO., LTD.
    Inventors: Mamoru Yamagami, Yasuhiro Fuwa
  • Patent number: 9946827
    Abstract: A method includes receiving an integrated circuit design layout that includes first and second layout blocks separated by a first space. The first and second layout blocks include, respectively, first and second line patterns oriented lengthwise in a first direction. The method further includes adding a dummy pattern to the first space, which connects the first and second line patterns. The method further includes outputting a mandrel pattern layout and a cut pattern layout in a computer-readable format. The mandrel pattern layout includes the first and second line patterns and the dummy pattern. The cut pattern layout includes a pattern corresponding to the first space. In embodiments, the method further includes manufacturing a first mask with the mandrel pattern layout and manufacturing a second mask with the cut pattern layout. In embodiments, the method further includes patterning a substrate with the first mask and the second mask.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: April 17, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Ming Wang, Chih-Hsiung Peng, Chi-Kang Chang, Kuei-Shun Chen, Shih-Chi Fu
  • Patent number: 9929098
    Abstract: A semiconductor device includes an insulating interlayer on a first region of a substrate. The insulating interlayer has a recess therein and includes a low-k material having porosity. A damage curing layer is formed on an inner surface of the recess. A barrier pattern is formed on the damage curing layer. A copper structure fills the recess and is disposed on the barrier pattern. The copper structure includes a copper pattern and a copper-manganese capping pattern covering a surface of the copper pattern. A diffusion of metal in a wiring structure of the semiconductor device may be prevented, and thus a resistance of the wiring structure may decrease.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: March 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Jin Yim, Sang-Hoon Ahn, Thomas Oszinda, Jong-Min Baek, Byung Hee Kim, Nae-In Lee, Kee-Young Jun
  • Patent number: 9929020
    Abstract: A method of making a semiconductor device includes disposing a first hard mask (HM), amorphous silicon, and second HM on a substrate; disposing oxide and neutral layers on the second HM; removing a portion of the oxide and neutral layers to expose a portion of the second HM; forming a guiding pattern by selectively backfilling with a polymer; forming a self-assembled block copolymer (BCP) on the guiding pattern; removing a portion of the BCP to form an etch template; transferring the pattern from said template into the substrate and forming uniform silicon fin arrays with two types of HM stacks with different materials and heights; gap-filling with oxide followed by planarization; selectively removing and replacing the taller HM stack with a third HM material; planarizing the surface and exposing both HM stacks; and selectively removing the shorter HM stack and the silicon fins underneath.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: March 27, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Cheng Chi, Fee Li Lie, Chi-Chun Liu, Ruilong Xie
  • Patent number: 9923112
    Abstract: A solar cell receiver for use in a concentrating solar system which concentrates the solar energy onto a solar cell for converting solar energy to electricity. The solar cell receiver may include a solar cell mounted on a support and with one or more III-V compound semiconductor layers. An optical element may be positioned over the solar cell and have an optical channel with an inlet that faces away from the solar cell and an outlet that faces towards the solar cell. A frame may be positioned over the support and extend around the solar cell with the frame having an inner side that extends above the support and faces towards the optical element. An encapsulant may be positioned over the support and contained between the optical element and the frame. The encapsulant may have enlarged heights at contact points with the optical element and the frame and a reduced height between the contact points away from the optical element and the frame. The solar cell receiver may be used in a solar cell module.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: March 20, 2018
    Assignee: SUNCORE PHOTOVOLTAICS, INC.
    Inventors: Lei Yang, Sunil Vaid, Mikhail Kats, Gary Hering, Philip Blumenfeld, Damien Buie, John Nagyvary, James Foresi, Peter Allen Zawadzki
  • Patent number: 9911623
    Abstract: A method includes forming a trench that is partially filled with a first metal material, the trench being formed within a first Interlayer Dielectric (ILD) layer, filling a remaining portion of the trench with a sacrificial material, depositing a buffer layer on the first ILD layer, patterning the buffer layer to form a hole within the buffer layer to expose the sacrificial material, and removing the sacrificial material.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: March 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • Patent number: 9905531
    Abstract: Method for producing a composite structure comprising the direct bonding of at least one first wafer with a second wafer, and comprising a step of initiating the propagation of a bonding wave, where the bonding interface between the first and second wafers after the propagation of the bonding wave has a bonding energy of less than or equal to 0.7 J/m2. The step of initiating the propagation of the bonding wave is performed under one or more of the following conditions: placement of the wafers in an environment at a pressure of less than 20 mbar and/or application to one of the two wafers of a mechanical pressure of between 0.1 MPa and 33.3 MPa.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: February 27, 2018
    Assignee: Soitec
    Inventors: Ionut Radu, Marcel Broekaart, Arnaud Castex, Gweltaz Gaudin, Gregory Riou
  • Patent number: 9903024
    Abstract: A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: February 27, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Po-Yi Wu, Chun-Hung Lu
  • Patent number: 9899287
    Abstract: A fan-out wafer level package structure includes a chip, a molding compound, at least one circuit layer, and at least one dielectric layer. The molding compound encapsulates the chip. The at least one circuit layer is disposed on a surface of the chip and a surface of the molding compound coplanar to the surface of the chip. The at least one circuit layer includes a plurality of traces. Each of the traces includes a first portion and a second portion. The first portion is located at an edge region of a projection of the chip onto the dielectric layer. A width of the first portion is larger than a width of the second portion. The at least one dielectric layer is disposed at a side of the at least one circuit layer.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: February 20, 2018
    Assignee: Powertech Technology Inc.
    Inventors: Ting-Feng Su, Chia-Jen Chou
  • Patent number: 9882202
    Abstract: Provided are a positive electrode for a lithium-sulfur secondary battery and a method of forming the same, the positive electrode being capable of maintaining battery characteristics such as a specific capacity and a cycling characteristic while achieving a high rate characteristic in particular when being applied to a lithium-sulfur secondary battery. A positive electrode of a lithium-sulfur secondary battery includes a positive electrode current collector and carbon nanotubes grown on a surface of the positive electrode current collector and oriented in a direction orthogonal to the surface. At least the surface of each of the carbon nanotubes is covered with sulfur with a certain interstice left between neighboring ones of the carbon nanotubes.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: January 30, 2018
    Assignee: ULVAC, INC.
    Inventors: Tatsuhiro Nozue, Hirohiko Murakami
  • Patent number: 9865788
    Abstract: A thermoelectric device may include a housing that may have a first housing element and a second housing element. The first housing element and the second housing element may each be composed of an electrically conductive material. At least two thermoelectric elements may be arranged between the first housing element and the second housing element. The at least two thermoelectric elements may be arranged at a distance from each other and may be electrically connected via at least one conductor bridge. A first electrical insulator may be arranged between the at least two thermoelectric elements and the first housing element. A second electrical insulator may be arranged between the at least two thermoelectric elements and the second housing element.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: January 9, 2018
    Assignee: Mahle Behr GmbH & Co. KG
    Inventors: Christopher Laemmle, Thomas Himmer
  • Patent number: 9852995
    Abstract: A semiconductor device includes a first semiconductor chip having a first surface with a semiconductor element and a second surface opposing the first surface. A first metal layer has a third surface supporting the first semiconductor chip and a fourth surface opposing the third surface. The third surface is larger than the second surface. A resin layer has a fifth surface facing the first semiconductor chip and a sixth surface facing the first metal layer. A pad is on the first surface of the first semiconductor chip. A first via contact is within the resin layer on the third surface of the first metal layer. A second via contact is within the resin layer on the pad. The first and second via contacts are connected to first and the second interconnects, respectively.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: December 26, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kentaro Mori, Chiaki Takubo
  • Patent number: 9842817
    Abstract: A wafer-level pulling method includes securing a top holder to a plurality of chips; and securing a bottom holder to a wafer, wherein the plurality of chips are bonded to the wafer by a plurality of solder bumps. The wafer-level pulling method further includes softening the plurality of solder bumps; and stretching the plurality of softened solder bumps.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: December 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Su-Chun Yang, Yi-Li Hsiao, Chih-Hang Tung, Chen-Hua Yu
  • Patent number: 9831127
    Abstract: A method of processing a semiconductor substrate is provided. The method may include forming a film over a first side of a semiconductor substrate, forming at least one separation region in the semiconductor substrate between a first region and a second region of the semiconductor substrate, arranging the semiconductor substrate on a breaking device, wherein the breaking device comprises a breaking edge, and wherein the semiconductor substrate is arranged with the film facing the breaking device and in at least one alignment position with the at least one separation region aligned with the breaking edge, and forcing the semiconductor substrate to bend the first region with respect to the second region over the breaking edge until the film separates between the breaking edge and the at least one separation region.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: November 28, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Franco Mariani, Korbinian Kaspar
  • Patent number: 9818713
    Abstract: A method of making an assembly can include forming a first conductive element at a first surface of a substrate of a first component, forming conductive nanoparticles at a surface of the conductive element by exposure to an electroless plating bath, juxtaposing the surface of the first conductive element with a corresponding surface of a second conductive element at a major surface of a substrate of a second component, and elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles cause metallurgical joints to form between the juxtaposed first and second conductive elements. The conductive nanoparticles can be disposed between the surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: November 14, 2017
    Assignee: Invensas Corporation
    Inventor: Cyprian Emeka Uzoh
  • Patent number: 9805928
    Abstract: The present invention provides a method to manufacture nanowires. In various embodiments, a method is provided for producing an oxidized metal layer as a heterogeneous seed layer on arbitrary substrate for controlled nanowire growth is disclosed which comprises depositing a metal layer on a substrate, oxidizing the metal layer in air ambient or in oxidizing agent, and growing nanowires at low temperatures on oxidized metal layers on virtually any substrate.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: October 31, 2017
    Assignee: The Curators of the University of Missouri
    Inventors: Jae Wan Kwon, Baek Hyun Kim
  • Patent number: 9793243
    Abstract: A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: October 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Fa Lu, Cheng-Yuan Tsai, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 9795053
    Abstract: An air vent is formed in a substrate of an electronic device such that air in a cavity of a metal mold can be released through the air vent when a resin is molded. Solder resist is disposed on a second surface of the substrate and has an opening portion at a position corresponding to the air vent. As such, the air can be also released from a clearance between a lower mold and the solder resist resulting from a rough surface of the solder resist. The resin can be held in a space provided between the second surface of the substrate and the lower mold. Therefore, the resin having passed through the air vent can be restricted from flowing out, and the air vent can be restricted from losing its function due to the substrate and the metal mold closely contacting with each other.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: October 17, 2017
    Assignee: DENSO CORPORATION
    Inventors: Yuki Sanada, Atsushi Kashiwazaki
  • Patent number: 9793179
    Abstract: The application relates to a method for determining a bonding connection (1) in a component arrangement (2), wherein the method has the following steps: producing a bonding connection (1) between a bonding section (3) of a bonding wire (4) and a metallic contact point (5), structuring a top-side surface of the bonding wire (4) in the region of the bonding section (3) and determining the bonding connection (1), wherein in this case a test voltage is applied to the bonding wire (4) and the bonding connection (1) so that the bonding connection (1) heats up owing to the current flow, generating a thermogram for the heated bonding connection (1) and determining whether the bonding connection (1) has been produced correctly by evaluating the thermogram. Furthermore, the application relates to a test apparatus for determining a bonding connection (1) in a component arrangement (2).
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: October 17, 2017
    Assignees: Technische Universitat Berlin, Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung E.V.
    Inventors: Andreas Middendorf, Torsten Nowak, Sergei Janzen
  • Patent number: 9786835
    Abstract: A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: October 10, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: James W. Adkisson, Panglijen Candra, Thomas J. Dunbar, Jeffrey P. Gambino, Mark D. Jaffe, Anthony K. Stamper, Randy L. Wolf
  • Patent number: 9786552
    Abstract: A method of forming fine patterns includes forming a partition on a base layer. The partition includes a partition block, a first open region provided to face the partition block, and first lines extending from the partition block to the first open region. A spacer is formed on sidewalls of the partition to define a second open region overlapping with the first open region and to include second lines on sidewalls of the first lines. The partition may be removed to open a third open region occupied by the partition block and spaces between the second lines. A target pattern is formed to include third lines filling the spaces between the second lines, a first pad block filling the second open region, and a second pad block filling the third open region. Each of the first and second pad blocks is separated into a plurality of pads.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: October 10, 2017
    Assignee: SK Hynix Inc.
    Inventor: Do Youn Kim
  • Patent number: 9772359
    Abstract: According to one embodiment, a semiconductor module comprises a substrate, a first wiring, an electrode pad, a junction, an oscillator, and a detector. The first wiring is disposed on the substrate, and has a characteristic impedance Z0. The electrode pad is connected to the first wiring. The junction is disposed on the electrode pad, and has an impedance Z1. The oscillator is disposed in contact with the first wiring, and oscillates a pulse wave of a voltage toward the junction via the first wiring. The detector is disposed in contact with the first wiring, and detects an output wave of the pulse wave from the junction. The characteristic impedance Z0 and the impedance Z1 satisfy a following relationship (1), ? Z ? ? 0 - Z ? ? 1 Z ? ? 0 ? ? 0.05 .
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: September 26, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenji Hirohata, Minoru Mukai, Tomoko Monda
  • Patent number: 9761554
    Abstract: An apparatus, and methods therefor, relates generally to an integrated circuit package. In such an apparatus, a platform substrate has a copper pad. An integrated circuit die is coupled to the platform substrate. A wire bond wire couples a contact of the integrated circuit die and the copper pad. A first end of the wire bond wire is ball bonded with a ball bond for direct contact with an upper surface of the copper pad. A second end of the wire bond wire is stitch bonded with a stitch bond to the contact.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: September 12, 2017
    Assignee: Invensas Corporation
    Inventors: Willmar Subido, Reynaldo Co, Wael Zohni, Ashok S. Prabhu
  • Patent number: 9761464
    Abstract: A power MOSFET includes a substrate, a dielectric layer, solder balls, first and second patterned-metal layers. The substrate includes an active surface, a back surface, a source region and a gate region on the active surface, and a drain region on the back surface. The first patterned-metal layer disposed on the active surface includes a source electrode, a gate electrode, a drain electrode and a connecting trace. The source and gate electrodes electrically connect the source and gate regions. The connecting trace located at an edge of the substrate electrically connects the drain electrode. The dielectric layer disposed on the active surface exposes the first patterned-metal layer. The second patterned-metal layer includes UBM layers covering the source, gate and drain electrodes and a connecting metal layer covering the connecting trace and extending to the edge to electrically connect the drain region. The solder balls are disposed on the UBM layers.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: September 12, 2017
    Assignee: Excelliance MOS Corporation
    Inventor: Yi-Chi Chang
  • Patent number: 9754905
    Abstract: Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: September 5, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ekta Misra, Krishna R. Tunga
  • Patent number: 9754889
    Abstract: An electronic component of integrated circuitry comprises a substrate comprising at least two terminals. Material of one of the terminals has an upper surface. A conductive via extends elevationally into the material of the one terminal. The conductive via extends laterally into the material of the one terminal under the upper surface of the one terminal. Material of the one terminal is above at least some of the laterally extending conductive via. Other embodiments, including method embodiments, are disclosed.
    Type: Grant
    Filed: December 19, 2015
    Date of Patent: September 5, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Deepak Chandra Pandey, Haitao Liu
  • Patent number: 9735122
    Abstract: Disclosed herein are various chip packaging structures and methods of fabrication. In one embodiment, a flip chip package structure can include: (i) a pad on a chip; (ii) an isolation layer on the chip and the pad, where the isolation layer includes a through hole that exposes a portion of an upper surface of the pad; (iii) a metal layer on the pad, where the metal layer fully covers the exposed upper surface portion of the pad; and (iv) a bump on the metal layer, where side edges of the bump do not make contact with the isolation layer.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: August 15, 2017
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventor: Xiaochun Tan
  • Patent number: 9726347
    Abstract: In a light emitting device and system providing white light with various color temperatures are provided, a light emitting device includes a light emitting element (LED) that is operated by a driving bias and emits first light, and a phosphor layer including a phosphor that partially wavelength-converts first light and emits second light, thereby emitting white light using the first light and the second light, wherein the phosphor has a maximum conversion efficiency at a first level of the driving bias, and the LED has a maximum conversion efficiency at a second level of the driving bias, the first level being different from the first level.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: August 8, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yu-Sik Kim
  • Patent number: 9721889
    Abstract: Integrated circuit (IC) structure embodiments and methods of forming them with middle of the line (MOL) contacts that incorporate a protective cap, which provides protection from damage during back end of the line (BEOL) processing. Each MOL contact has a main body in a lower portion of a contact opening. The main body has a liner (e.g., a titanium nitride layer) that lines the lower portion and a metal layer on the liner. The MOL contact also has a protective cap in an upper portion of the contact opening above the first metal layer and extending laterally over the liner to the sidewalls of the contact opening. The protective cap has an optional liner, which is different from the liner in the lower portion, and a metal layer, which is either the same or different than the metal in the main body.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: August 1, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chengyu C. Niu, Vimal K. Kamineni, Mark V. Raymond, Xunyuan Zhang
  • Patent number: 9720101
    Abstract: A system, method and computer program product for determining whether a material meets an alpha particle emissivity specification that includes measuring a background alpha particle emissivity for the counter and measuring a combined alpha particle emissivity from the counter containing a sample of the material. The combined alpha particle emissivity includes the background alpha particle emissivity in combination with a sample alpha particle emissivity. The decision statistic is computed based on the observed data and compared to a threshold value. When the decision statistic is less than the threshold value, the material meets the alpha particle emissivity specification. The testing times are computed based on pre-specified criteria so as to meet the needs of both Producer and Consumer.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: August 1, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Michael S. Gordon, Kenneth P. Rodbell, Emmanuel Yashchin
  • Patent number: 9705057
    Abstract: In a method for producing a laser diode, a number of laser diodes are produced on a wafer. The wafer is broken down into wafer pieces, each wafer piece having a plurality of laser diodes being arranged side by side. One wafer piece is inserted into a first mount that includes a first covering element overlapping a front face of the wafer piece and shadowing a bottom area of the front face of the wafer piece. A minor layer is deposited on an unshadowed upper area of the wafer piece's front face. The wafer piece is inserted into a second mount, which includes a second covering element that shadows the minor layer of the upper area of the front face. An electrically conductive contact layer is deposited on an unshadowed bottom area of the wafer piece's front face. The wafer piece is subsequently broken down into individual laser diodes.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: July 11, 2017
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Roland Enzmann, Stephan Haneder, Tomasz Swietlik, Christoph Walter, Andreas Rozynski, Markus Graul, Karsten Auen, J├╝rgen Dachs
  • Patent number: 9691676
    Abstract: A semiconductor device includes a first semiconductor chip including a first surface and a plurality of first electrodes disposed on the first surface; a second semiconductor chip including a second surface which faces the first surface, a plurality of second electrodes each of which includes at least one end disposed on the second surface, and a plurality of first protrusions each of which surrounds the one end of each of the second electrodes on an electrode by electrode basis; a plurality of conductive joint materials each of which joins a third electrode included in the first electrodes to the one end of an electrode which faces the third electrode among the second electrodes; and a plurality of first underfill resins each of which is disposed inside one of the first protrusions and covers one of the conductive joint materials on a material by material basis.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: June 27, 2017
    Assignee: SOCIONEXT INC.
    Inventor: Takeshi Kodama
  • Patent number: 9691729
    Abstract: A first substrate may be bonded to a second substrate in a method that may include providing the first substrate, providing a second substrate, providing a bonding layer precursor, positioning the bonding layer precursor between the first substrate and the second substrate, and bonding the first substrate to the second substrate by heating the bonding layer precursor to form a bonding layer. The first substrate may include a bonding surface, and a geometry of the bonding surface of the first substrate may include a plurality of microchannels. The second substrate may include a complementary bonding surface and the bonding layer precursor may include a metal. The bonding layer may fill the microchannels of the first substrate and may contact substantially the entire bonding surface of the first substrate.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: June 27, 2017
    Assignee: Tpyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Shailesh N. Joshi, Masao Noguchi
  • Patent number: 9673159
    Abstract: A semiconductor device according to the present invention includes a semiconductor substrate, a pad formed on the semiconductor substrate, a rewiring that is electrically connected to the pad and led to a region outside the pad, a resin layer formed on the rewiring, and an external terminal electrically connected to the rewiring via the resin layer, and the resin layer is formed so as to enter the inside of a slit formed in a region along the periphery of the external terminal in the rewiring.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: June 6, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Hiroshi Okumura
  • Patent number: 9653431
    Abstract: The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: May 16, 2017
    Assignee: International Business Machines Corporation
    Inventors: Tien-Jen Cheng, Mukta G. Farooq, John A. Fitzsimmons
  • Patent number: 9653418
    Abstract: A method of manufacturing a packaging device may include: forming a plurality of through-substrate vias (TSVs) in a substrate, wherein each of the plurality of TSVs has a protruding portion extending away from a major surface of the substrate. A seed layer may be forming over the protruding portions of the plurality of TSVs, and a conductive ball may be coupled to the seed layer and the protruding portion of each of the plurality of TSVs. The seed layer and the protruding portion of each of the plurality of TSVs may extend into an interior region of the conductive ball.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: May 16, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Shih-Wei Liang, Kai-Chiang Wu, Ming-Che Ho, Yi-Wen Wu
  • Patent number: 9653432
    Abstract: The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: May 16, 2017
    Assignee: International Business Machines Corporation
    Inventors: Tien-Jen Cheng, Mukta G. Farooq, John A. Fitzsimmons
  • Patent number: 9646758
    Abstract: Methods of coupling inductors in an IC device using interconnecting elements with solder caps and the resulting device are disclosed. Embodiments include forming a top inductor structure, in a top inductor area on a lower surface of a top substrate, the top inductor structure having first and second top terminals at its opposite ends; forming a bottom inductor structure, in a bottom inductor area on an upper surface of a bottom substrate, the bottom inductor structure having first and second bottom terminals at its opposite ends; forming top interconnecting elements on the lower surface of the top substrate around the top inductor area; forming bottom interconnecting elements on the upper surface of the bottom substrate around the bottom inductor area; forming solder bumps on lower and upper surfaces, respectively, of the top and bottom interconnecting elements; and connecting the top and bottom interconnecting elements to each other.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: May 9, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Tak Ming Mak, Ajit M. Dubey
  • Patent number: 9633882
    Abstract: Methods of producing integrated circuits with interposers and integrated circuits produced from such methods are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a base layer overlying a substrate, and forming an alignment mark overlying the base layer. A first layer is formed overlying the base layer and the alignment mark, and the first layer has a first layer thickness. A second layer is formed overlying the first layer, where the second layer has a second layer thickness and where a combined thickness of the first and second layer thicknesses is from about 2 to about 50 micrometers. A second component is formed from the second layer.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: April 25, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Ying Yu, Jianbo Sun, Derui Yin, Yelehanka Ramachandramurthy Pradeep, Rakesh Kumar
  • Patent number: 9627261
    Abstract: An integrated circuit (IC) combines a first IC chip (die) having a first on-chip interconnect structure and a second IC chip having a second on-chip interconnect structure on a reconstructed wafer base. The second IC chip is edge-bonded to the first IC chip with oxide-to-oxide edge bonding. A chip-to-chip interconnect structure electrically couples the first IC chip and the second IC chip.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: April 18, 2017
    Assignee: XILINX, INC.
    Inventors: Arifur Rahman, Venkatesan Murali
  • Patent number: 9620413
    Abstract: A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: April 11, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Thomas J. Strothmann, Damien M. Pricolo, Il Kwon Shim, Yaojian Lin, Heinz-Peter Wirtz, Seung Wook Yoon, Pandi C. Marimuthu
  • Patent number: 9601412
    Abstract: The present invention discloses a three-dimensional package structure. The first conductive element comprises a top surface, a bottom surface and a lateral surface. The conductive pattern disposed on the top surface of the first conductive element. A second conductive element is disposed on the conductive pattern. The first conductive element is electrically connected to the conductive pattern, and the second conductive element is electrically connected to the conductive pattern. In one embodiment, the shielding layer is a portion of the patterned conductive layer.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: March 21, 2017
    Assignee: CYNTEC CO., LTD.
    Inventors: Da-Jung Chen, Chun-Tiao Liu, Chau-Chun Wen