Abstract: An apparatus and a method for producing three-dimensional integrated circuit packages. In one embodiment, an electronics package with at least two dice are stacked one atop another is disclosed. A top die is of smaller size compared with a bottom die such that after a die attach operation, wire-bond pads of the bottom die will be exposed for a subsequent wire bonding operation. The bottom die contains contact pads on the front side that couple with one or more passive components fabricated on the back side of the top die to complete the circuit. In another exemplary embodiment, a method to form one or more three-dimensional passive components in a stacked-die package is disclosed wherein partial inductor elements are fabricated on the front side of the bottom die and the back side of the top die. The top and bottom elements are coupled together completing the passive component.

Abstract: A pixel structure includes a scan line, a data line, a gate electrode, a semiconductor layer, a source electrode, a drain electrode including a comb-shaped part surrounding the source electrode and a connecting part, and a pixel electrode electrically connected to the drain electrode. The scan line and the data line are arranged intersectedly and electrically insulated from each other. At least a portion of the source electrode and the drain electrode are disposed on the semiconductor layer. At least one branch of the comb-shaped part extends outside one side of the gate electrode to form a protrusion part. The connecting part extends from the comb-shaped part beyond the other side of the gate electrode. The protrusion part and the connecting part aligned with the margin of the gate electrode have a first width and a third width respectively, wherein the first width substantially equals to the third width.

Abstract: A stacked semiconductor package may include a wiring substrate. A first semiconductor chip may be disposed on the wiring substrate and wire-bonded to the wiring substrate. An interposer chip may be disposed on the wiring substrate and sire bonded to the wiring substrate. The interposer chip may include a circuit element and a bonding pad being electrically connected. A second semiconductor chip may be disposed on the interposer chip and wire-bonded to the interposer chip. The second semiconductor chip may be electrically connected to the wiring substrate through the interposer chip.

Abstract: A semiconductor device has a first substrate with a central region. A plurality of bumps is formed around a periphery of the central region of the first substrate. A first semiconductor die is mounted to the central region of the first substrate. A second semiconductor die is mounted to the first semiconductor die over the central region of the first substrate. A height of the first and second die is less than or equal to a height of the bumps. A second substrate has a thermal conduction channel. A surface of the second semiconductor die opposite the first die is mounted to the thermal conductive channel of the second substrate. A thermal interface layer is formed over the surface of the second die. The bumps are electrically connected to contact pads on the second substrate. A conductive plane is formed over a surface of the second substrate.

Abstract: An electronic circuit arrangement includes a heat sink and a first circuit carrier which is thermally coupled to the heat sink, lies flat on the latter and is intended to wire electronic components of the circuit arrangement. Provided for at least one electronic component is a special arrangement which is associated with a considerably increased heat dissipation capability for the relevant component and, in addition, also affords further advantages in connection with changes in the population and/or line routing which might occur in practice. The important factor for this is that the component is arranged under a second circuit carrier which is held in a recess in the first circuit carrier. The recess passes through to the top side of the heat sink.

Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

Abstract: In a CMOS implemented free or parasitic pnp transistor, triggering is controlled by introducing a low side zener reference voltage.

Abstract: A method of making a semiconductor chip assembly includes providing a bump and a ledge, wherein the bump includes first, second and third bent corners that shape a cavity, mounting an adhesive on the ledge including inserting the bump into an opening in the adhesive, mounting a conductive layer on the adhesive including aligning the bump with an aperture in the conductive layer, then flowing the adhesive between the bump and the conductive layer, solidifying the adhesive, then providing a conductive trace that includes a pad, a terminal and a selected portion of the ledge, providing a heat spreader that includes the bump, then mounting a semiconductor device on the bump within the cavity, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.

Abstract: An electronic component package includes: a base having a top surface and a side surface; and a plurality of layer portions stacked on the top surface of the base, each of the layer portions including at least one electronic component chip. The base includes a plurality of external connecting terminals, and a retainer for retaining the plurality of external connecting terminals. Each of the external connecting terminals has an end face located at the side surface of the base. At least one of a plurality of electronic component chips that the plurality of layer portions include is electrically connected to at least one of the external connecting terminals.

Abstract: Overmolded lenses and certain fabrication techniques are described for LED structures. In one embodiment, thin YAG phosphor plates are formed and affixed over blue LEDs mounted on a submount wafer. A clear lens is then molded over each LED structure during a single molding process. The LEDs are then separated from the wafer. The molded lens may include red phosphor to generate a warmer white light. In another embodiment, the phosphor plates are first temporarily mounted on a backplate, and a lens containing a red phosphor is molded over the phosphor plates. The plates with overmolded lenses are removed from the backplate and affixed to the top of an energizing LED. A clear lens is then molded over each LED structure. The shape of the molded phosphor-loaded lenses may be designed to improve the color vs. angle uniformity. Multiple dies may be encapsulated by a single lens. In another embodiment, a prefabricated collimating lens is glued to the flat top of an overmolded lens.

Abstract: Disclosed are a semiconductor package and semiconductor system in package using the same. The semiconductor package includes: a printed circuit board (PCB); a semiconductor die disposed on the PCB and having conductive posts formed on an upper surface of the semiconductor die; and a molding formed on the PCB to cover the semiconductor die, wherein the conductive posts have a surface exposed out of an upper surface of the molding. The semiconductor system in package includes: a first semiconductor package having a semiconductor die on which conductive posts are formed, and a molding formed so that upper surfaces of the conductive posts are exposed; and a second semiconductor package disposed on the first semiconductor package and electrically connected to the conductive posts.

Abstract: According to one embodiment, a semiconductor device having a multilayer wiring structure includes a function block and a test pad. The function block contains a DFT circuit. The test pad is formed in an intermediate wiring layer, and connected to the DFT circuit of the function block. A functional operation test of the function block is executed by using the test pad.

Abstract: A semiconductor package is provided. The semiconductor package includes a carrier, a die, a metal sheet and a molding compound. The die is disposed on the carrier. The metal sheet has a first portion and a second portion, wherein a receiving space is defined by the first portion and the second portion, and the second portion is electrically connected to the carrier. The molding compound covers the die and the receiving space is filled by at least part of the molding compound.

Abstract: An apparatus for housing a micromechanical system includes a substrate with a surface on which the micromechanical system is formed, a transparent cover and a dry film layer arrangement between the surface of the substrate and the transparent cover. The dry film layer arrangement has an opening, so that the micromechanical system adjoins the opening.

Abstract: A device with a solder joint made of a copper contact pad (210) of certain area (202) and an alloy layer (301) metallurgically attached to the copper pad across the pad area. The alloy layer contains copper/tin alloys, which include Cu6Sn5 intermetallic compound, and nickel/copper/tin alloys, which include (Ni,Cu)6Sn5 intermetallic compound. A solder element (308) including tin is metallurgically attached to the alloy layer across the pad area. No fraction of the original thin nickel layer is left after the reflow process. Copper/tin alloys help to improve the drop test performance, nickel/copper/tin alloys help to improve the life test performance.

Abstract: One embodiment of the invention is a semiconductor system (1400) of arrays (1401, 1402, etc.) of packaged devices. Each array includes a sheet-like substrate (1411, 1412, etc.) made of insulating material integral with conductive horizontal lines and vertical vias, and terminals on the surfaces. Semiconductor components, which may include more than one active or passive chips, or chips of different sizes, are attached to the substrate; the electrical connections may include flip-chip, wire bond, or combination techniques. Encapsulation compound (1412, 1422, etc.), which adheres to the substrate, embeds the connected components. Metal posts (1431, 1432, etc.) traverse the encapsulation compound vertically, connecting the substrate vias with pads on the encapsulation surface. The pads are covered with solder bodies used to connect to the next-level device array so that a 3-dimensional system of packaged devices is formed.

Abstract: A semiconductor package has first and second semiconductor die mounted to a substrate. The first semiconductor die includes a first inductor coil electrically coupled to the substrate. The second semiconductor die is mounted over the first semiconductor die. The second semiconductor die includes a second inductor coil electrically coupled to the substrate. A center of the second inductor coil has a vertical and lateral separation with respect to a center of the first inductor coil which are each selectable to minimize mutual inductive coupling between the first and second inductor coils. A spacer is disposed between the first and second semiconductor die to adjust the vertical separation. The center of the second inductor is positioned laterally within the second semiconductor die with respect to the center of the first inductor to adjust the lateral separation. The mutual inductive coupling decreases with increasing vertical and lateral separation.

Abstract: A method for fabricating MEMS package structure includes the following steps. Firstly, a substrate is provided. Next, a plurality of lower metallic layers and first oxide layers are formed to compose a MEMS structure and an interconnecting structure. Next, an upper metallic layer is formed on the MEMS structure and the interconnecting structure. The upper metallic layer has a first opening and a second opening. Next, the first opening and the second opening are employed as etching channels to remove a portion of the first oxide layers so as to form a first cavity surrounding the MEMS structure and form a second cavity above the interconnecting structure. The first cavity communicates with the second cavity. Next, the second opening is sealed in a vacuum environment. Next, a packaging element is formed on the upper metallic layer in a non-vacuum environment to seal the first opening.

Abstract: There are provided a method of manufacturing a semiconductor device, a substrate processing apparatus, and a semiconductor device. The method allows rapid formation of a conductive film, which has a low concentration of impurities permeated from a source owing to its dense structure, and a low resistivity. The method is performed by simultaneously supplying two or more kinds of sources into a processing chamber to form a film on a substrate placed in the processing chamber. The method comprises: performing a first source supply process by supplying at least one kind of source into the processing chamber at a first supply flow rate; and performing a second source supply process by supplying the at least one kind of source into the processing chamber at a second supply flow rate different from the first supply flow rate.

Abstract: A semiconductor device and method. One embodiment provides an integral array of first carriers and an integral array of second carries connected to the integral array of first carriers. First semiconductor chips are arranged on the integral array of first carriers. The integral array of second carriers is arranged over the first semiconductor chips.

Abstract: The invention relates to electronic components on thinned substrates, for example image sensors. Preferably, connection pads are connected through the thinned substrate to underlying layers and notably to a test pad by way of openings through which the metal of the pad passes. The openings are elongate openings extending along one edge of the pad of rectangular shape and a circular area of at least 50% (and preferably 65 to 75%) of the area of the pad contains no opening for connection with the underlying layers. This circular area is intended for bonding an external connection wire. The connection pads are testable from the back side by test probes and the front side may be tested (before bonding and thinning) by test probes with the same geometric configuration.

Abstract: An electronic component has at least two semiconductor devices, a contact clip and a leadframe with a device carrier portion and a plurality of leads. The contact clip extends between the first side of at least two semiconductor devices and at least one lead of the leadframe to electrically connect a load electrode of the at least two semiconductor devices to at least one lead.

Abstract: With embodiments disclosed herein, the distribution of gated power is done using on-die layers without having to come back out and use package layers.

Abstract: A multi-chip module suitable for use in a battery protection circuit. The multi-chip module includes an integrated circuit chip, a first power transistor, a second power transistor, a first connection structure electrically coupling the integrated circuit chip to the first power transistor, a second connection structure electrically coupling the integrated circuit chip to the second power transistor, and a leadframe structure comprising a first lead, a second lead, a third lead and a fourth lead, wherein the integrated circuit chip, the first power transistor, and the second power transistor are mounted on the leadframe structure. A molding material covers at least part of the integrated circuit chip, the first power transistor, the second power transistor, the first connection structure, and the second connection structure.

Abstract: A dielectric layer is provided. The dielectric layer includes a photo-sensitive polymer or a non-photo-sensitive polymer and an amorphous metal oxide disposed in the photo-sensitive polymer or a non-photo-sensitive polymer.

Abstract: A bonded semiconductor structure includes a support substrate which carries a first electronic circuit, and an interconnect region carried by the support substrate. The interconnect region includes a capacitor and conductive line in communication with the first electronic circuit. The circuit includes a bonding layer carried by the interconnect region, and a bonded substrate coupled to the interconnect region through the bonding layer.

Abstract: It is an object to provide a laser beam machining method which can easily cut a machining target. The laser beam machining method irradiates laser light while positioning a focus point at the inside of a machining target to thereby form a treated area based on multiphoton absorption along a planned cutting line of the machining target inside the machining target and also form a minute cavity at a predetermined position corresponding to the treated area in the machining target.

Abstract: In a circuit module for a high frequency, a resistance film is formed on a side of a semiconductor circuit chip, mounted above a dielectric substrate through ground metal layers, opposite to the dielectric substrate. A distance from the ground metal layer to the resistance film is a ¼ wavelength at a predetermined frequency, and the resistance film has a sheet resistance equal to a characteristic impedance of air. A second dielectric substrate with the metal layer formed on a side opposite to the resistance film can be mounted. When being adhered to the second dielectric substrate, the resistance film has a characteristic impedance determined by a permittivity of a material of the semiconductor circuit chip. When being formed in space from the semiconductor circuit chip, the resistance film has a sheet resistance equal to a characteristic impedance of air. The thickness of the second dielectric substrate is a ¼ wavelength in a desired frequency.

Abstract: A mountable integrated circuit package system includes: providing a substrate having an opening provided therein; providing an encapsulated integrated circuit package having an external leadfinger; mounting the encapsulated integrated circuit package by the external leadfinger proximate to the opening in the substrate; and connecting the external leadfinger and the substrate.

Abstract: One aspect includes a sensor chip module including a sensor chip and a module housing accommodating the sensor chip. The module housing defines a mounting plane of the sensor chip module. In one case, an active surface of the sensor chip is inclined with respect to the mounting plane of the sensor chip module.

Abstract: A semiconductor device includes a semiconductor chip having at a center area thereof first and second pad rows which include a plurality of first pads and a plurality of second pads, respectively. A package substrate is bonded to the semiconductor chip. The package substrate includes a substrate opening corresponding to a region including the first and second pad rows, first and second wiring positioned at opposite sides of the substrate opening, respectively, and a ball land disposed in the first wiring area. A bridge section is provided over the substrate opening to mutually connect the first and second wiring areas. The ball land is electrically connected to at least one of the second pads through the bridge section by a lead.

Abstract: A disclosed semiconductor fabrication process includes forming a first bonding structure on a first surface of a cap wafer, forming a second bonding structure on a first surface of a device wafer, and forming a device structure on the device wafer. One or more eutectic flow containment structures are formed on the cap wafer, the device wafer, or both. The flow containment structures may include flow containment micro-cavities (FCMCs) and flow containment micro-levee (FCMLs). The FCMLs may be elongated ridges overlying the first surface of the device wafer and extending substantially parallel to the bonding structure. The FCMLs may include interior FCMLs lying within a perimeter of the bonding structure, exterior FCMLs lying outside of the bonding structure perimeter, or both. When the two wafers are bonded, the FCMLs and FCMCs confine flow of the eutectic material to the region of the bonding structure.

Abstract: An inverter, a logic circuit including the inverter and method of fabricating the same are provided. The inverter includes a load transistor of a depletion mode, and a driving transistor of an enhancement mode, which is connected to the load transistor. The load transistor may have a first oxide layer as a first channel layer. The driving transistor may have a second oxide layer as a second channel layer.

Abstract: This application relates to a semiconductor device, the semiconductor device comprising a metal carrier, an insulating foil partially covering the metal carrier, a first chip attached to the metal carrier over the insulating foil, and a second chip attached to the metal carrier over a region not covered by the insulating foil.

Abstract: A field-effect transistor according to the present invention includes a silicon substrate that has a resistivity of not more than 0.02 ?•cm, a channel layer that is formed on the silicon substrate and has a thickness of at least 5 ?m, a barrier layer that is formed on the channel layer and supplies the channel layer with electrons, a two dimensional electron gas layer that is formed by a hetero junction between the channel layer and the barrier layer, a source electrode and a drain electrode that each form an ohmic contact with the barrier layer, and a gate electrode that is formed between the source electrode and the drain electrode, and forms a Schottky barrier junction with the barrier layer.

Abstract: A photosensitive adhesive composition comprising (A) an alkali-soluble polymer, (B) a thermosetting resin, (C) one or more radiation-polymerizable compounds and (D) a photoinitiator, wherein the 5% weight reduction temperature of the mixture of all of the radiation-polymerizable compounds in the composition is 200° C. or higher.

Abstract: This invention discloses an electronic package for containing a vertical semiconductor chip that includes a laminated board having a via connector and conductive traces distributed on multiple layers of the laminated board connected to the via connector. The semiconductor chip having at least one electrode connected to the conductive traces for electrically connected to the conductive traces at a different layer on the laminated board and the via connector dissipating heat generated from the vertical semiconductor. A ball grid array (BGA) connected to the via connector functioning as contact at a bottom surface of the package for mounting on electrical terminals disposed on a printed circuit board (PCB) wherein the laminated board having a thermal expansion coefficient in substantially a same range the PCB whereby the BGA having a reliable electrical contact with the electrical terminals.

Abstract: An adhesive tape 101 electrically connecting conductive components includes a resin layer 132 containing a thermosetting resin, a solder powder 103 and a curing agent. The solder powder 103 and the curing agent reside in the resin layer 132, the curing temperature T1 of the resin layer 132 and the melting point T2 of the solder powder 103 satisfy T1?T2+20° C., wherein the resin layer 132 shows a melt viscosity of 50 Pa·s or above and 5000 Pa·s or below, at the melting point T2 of the solder powder 103.

Abstract: An electronic package for containing at least a top packaging module vertically stacked on a bottom packaging module. Each of the packaging modules includes a semiconductor chip packaged and connected by via connectors and connectors disposed on a laminated board fabricated with a standard printed-circuit board process wherein the top and bottom packaging module further configured as a surface mountable modules for conveniently stacking and mounting to prearranged electrical contacts without using a leadframe. At least one of the top and bottom packaging modules is a multi-chip module (MCM) containing at least two semiconductor chips. At least one of the top and bottom packaging modules includes a ball grid array (BGA) for surface mounting onto the prearranged electrical contacts. At least one of the top and bottom packaging modules includes a plurality of solder bumps on one of the semiconductor chips for surface mounting onto the prearranged electrical contacts.

Abstract: A method of laser-marking a semiconductor device involves providing a semiconductor wafer having a plurality of solder bumps formed on contact pads disposed on its active surface. The solder bumps have a diameter of about 250-280 ?m. A backgrinding tape is applied over the solder bumps. The tape is translucent to optical images. A backside of the semiconductor wafer, opposite the active surface, undergoes grinding to reduce wafer thickness. The backside of the semiconductor wafer is laser-marked while the tape remains applied to the solder bumps. The laser-marking system including an optical recognition device, control system, and laser. The optical recognition device reads patterns on the active surface through the tape to control the laser. The tape reduces wafer warpage during laser-marking to about 0.3-0.5 mm. The tape is removed after laser-marking the backside of the semiconductor wafer.

Abstract: An image capturing apparatus has a plurality of solid-state image capturing devices each having light receiving sections laminated in a depth direction of a semiconductor substrate. The devices are sequentially arranged in a direction along a substrate surface. Incident light waves having wavelength bands corresponding to depths of respective light receiving sections are detected there and generate signal charges. Bands are associated with light receiving sections by the wavelength dependence of the optical absorption. Trench sections each reach from a light incident surface or an opposite substrate surface to respective light receiving sections that do not overlap each other in a plane view. Electric charge transfer sections transfer electric charges independently from the light receiving sections via side wall portions of their respective trenches to the light incident surface side or the opposite substrate surface side at the time of driving readout gate electrodes at each trench section.

Abstract: A packaged integrated circuit device includes a substrate including a conductive pad thereon, and a chip stack including a plurality of chips on the substrate. A primary conductive line electrically connects the pad on the substrate to a conductive pad on one of the plurality of chips in the chip stack. Secondary conductive lines electrically connect the pad on the one of the plurality of chips to respective conductive pads on ones of the plurality of chips above and below the one of the plurality of chips in the chip stack. The primary conductive line may be configured to transmit a signal from the pad on the substrate to the pad on the one of the plurality of chips in the chip stack. After receiving the signal at the one of the plurality of chips, the secondary conductive lines may be configured to transmit the signal from the one of the plurality of chips to the ones of the plurality of chips above and below the one of the plurality of chips in the chip stack at a same time.

Abstract: A method for forming deep lithographic interconnects between a first metal and a second metal is provided. The method comprises depositing a first insulator layer on a semiconductor substrate; etching the first insulator layer at a selected location to provide at least a first via to the semiconductor substrate; depositing the first metal on the semiconductor substrate to form at least a first metal contact plug in the first via in contact with the semiconductor substrate; treating the semiconductor substrate with an in-situ plasma of a nitrogen containing gas wherein the plasma forms a nitride layer of the first metal at least capping a top surface of the first metal plug in the first via; and forming a second metal contact to the metal nitride layer capping at least the top surface of the first metal plug.

Abstract: A recess (5a) in the corner direction and recesses (5b) in side directions are formed in each connecting pad (5A) located at a corner of a lower surface-side of an insulating base 2 having groove-shaped recesses (6) in the periphery, and groove-shaped recesses (6a and 6b) in the corner and side directions are formed in each corner portion (2A) of the insulating base 2 corresponding to the connecting pad (5A). Connecting pads (5) of an electronic apparatus in which an electronic component is mounted on the insulating base 2 are mounted on an external electrical circuit board by using a solder. A solder (31) melted during the solder-mounting adheres onto the groove-shaped recesses (6a and 6b) in the corner and side directions of the corner portion (2A) of the insulating base 2 and thus solder fillets are formed in the groove-shaped recesses (6a and 6b).

Abstract: Provided is a technology capable of obtaining a fluorine-containing carbon film having a good leakage property, coefficient of thermal expansion and mechanical strength. The fluorine-containing carbon film is formed by using active species obtained by activating a C5F8 gas and a hydrogen gas. Fluorine in the fluorine-containing carbon film comes off together with H so that the amount of F decreases, thereby accelerating the polymerization. As a result, a C-dangling bond in the fluorine-containing carbon is decreased and a leakage current is reduced. Further, as the polymerization accelerates, the film gets stronger, so that the fluorine-containing carbon film having a high mechanical strength such as a high elasticity or a high hardness can be obtained.

Abstract: A semiconductor device contains an interposer having a square planar geometry, with length X for a first edge and length Y for a second edge orthogonal to the first edge, and a semiconductor chip and a dummy component disposed over the interposer, wherein the center of a first outer circumferential region, which surrounds the semiconductor chip over the interposer, and has length “a” for a third edge, and length “b” for a fourth edge, does not coincide with the center of the interposer, or equation X:Y=a:b is not satisfied, and the center of a second outer circumferential region, which surrounds the first outer circumferential region and the dummy components disposed over the interposer, and has length “x” for a fifth edge, and length “y” for a sixth edge, coincides with the center of the interposer, and equation X:Y=x:y is satisfied.

Abstract: A redistributed lead frame for use in molded plastic semiconductor package (38) is formed from an electrically conductive substrate by a sequential metal removal process. The process includes: (a) patterning a first side of an electrically conductive substrate to form an array of lands separated by channels, (b) disposing a first molding compound (18) within these channels, (c) patterning a second side of the electrically conductive substrate to form an array of chip attach sites (24) and routing circuits (26) electrically interconnecting the array of lands and the array of chip attached sites (24), (d) directly electrically interconnecting input/output pads on the at least one semiconductor device (28) to chip attach site members (24) of the array of chip attach sites (24), and (e) encapsulating the at least one semiconductor device (28), the array of chip attach sites (24) and the routing circuits (26) with a second molding compound (36).

Abstract: The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.

Abstract: A composite interconnect system includes a plurality of carbon nanotubes, a plurality of solder balls and standoff balls disposed on a first device to provide a connection to a second device. A die-attached substrate includes a substrate and one or more die disposed on the substrate by a die-attach composite interconnect. The die-attach composite interconnect includes a plurality of carbon nanotubes, solder bumps, and standoff balls disposed on the die to provide one or more connections to the substrate. A PCB-attached substrate package includes a substrate package and one or more die disposed on the substrate package. The substrate package is disposed on a PCB by a PCB-attach composite interconnect. The PCB-attach composite interconnect includes a plurality of carbon nanotubes, solder balls, and standoff balls disposed on the substrate package to provide one or more connections to the PCB.

Abstract: According to the invention, a process for producing a semiconductor device using an adhesive sheet for a spacer, comprising preparing an adhesive sheet having a spacer layer provided with an adhesive layer on at least one surface thereof as the adhesive sheet for a spacer, a step of sticking the adhesive sheet for a spacer onto a dicing sheet with the adhesive layer as a sticking surface, a step of dicing the adhesive sheet for a spacer to form a chip-shaped spacer provided with the adhesive layer, a step of peeling the spacer from the dicing sheet together with the adhesive layer, and a step of fixing the spacer onto an adherend with the adhesive layer interposed therebetween.