Abstract: The electronic device includes a first interconnect layer and a second interconnect layer. The second interconnect layer is provided on the lower surface of the first interconnect layer. The first interconnect layer includes a via plug (first conductive plug). An end face of the via plug on the side of the second interconnect layer is smaller in area than the opposite end face. The via plug is exposed on the surface of the first interconnect layer facing the second interconnect layer. An insulating resin forming the first interconnect layer is higher in thermal decomposition temperature than an insulating resin forming the second interconnect layer.

Abstract: A microelectronic assembly can include a first microelectronic device and a second microelectronic device. Each microelectronic device has a die structure including at least one semiconductor die and each of the microelectronic devices has a first surface, a second surface remote from the first surface and at least one edge surface extending at angles other than a right angle away from the first and second surfaces. At least one electrically conductive element extends along the first surface onto at least one of the edge surfaces and onto the second surface. At least one conductive element of the first microelectronic device can be conductively bonded to the at least one conductive element of the second microelectronic device to provide an electrically conductive path therebetween.

Abstract: A wire bond free power module assembly consists of a plurality of individual thin packages each consisting of two DBC wafers which sandwich one or more semiconductor die. The die electrodes and terminals extend through one insulation covered end of the wafer sandwich and the outer sides of the sandwiches are the outer copper plates of the DBC wafers which are in good thermal communication with the semiconductor die but are electrically insulated therefrom. The plural packages may be connected in parallel by lead frames on the terminals and the packages are stacked with a space between them to expose both sides of all packages to a cooling medium, either the fingers of a conductive comb or a fluid heat exchange medium.

Abstract: A vertically conducting LED comprising, in a layered arrangement: a highly thermally conductive submount wherein the highly conductive submount has a thermal conductivity of at least 100 W/m0K; a p-type layer comprising Al1-x-yInyGax N wherein 0?x?1 and 0?y?1; a quantum well layer comprising Al1-x-yInyGaxN wherein 0?x?1 and 0?y?1; an n-type layer comprising Al1-x-yInyGaxN wherein 0?x?1 and 0?y?1; and an n-type contact layer wherein the LED has a peak emission at 200-365 nm.

Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

Abstract: The mechanisms of forming a semiconductor device package described above provide a low-cost manufacturing process due to the relative simple process flow. By forming an interconnecting structure with a redistribution layer(s) to enable bonding of one or more dies underneath a package structure, the warpage of the overall package is greatly reduced. In addition, interconnecting structure is formed without using a molding compound, which reduces particle contamination. The reduction of warpage and particle contamination improves yield. Further, the semiconductor device package formed has low form factor with one or more dies fit underneath a space between a package structure and an interconnecting structure.

Abstract: In a method for fabricating a semiconductor device, first, a first metal interconnect is formed in an interconnect formation region, and a second metal interconnect is formed in a seal ring region. Subsequently, by chemical mechanical polishing or etching, the upper portions of the first metal interconnect and the second metal interconnect are recessed to form recesses. A second insulating film filling the recesses is then formed above a substrate, and the upper portion of the second insulating film is planarized. Next, a hole and a trench are formed to extend halfway through the second insulating film, and ashing and polymer removal are performed. Subsequently to this, the hole and the trench are allowed to reach the first metal interconnect and the second metal interconnect.

Abstract: A semiconductor package and testing method is disclosed. The package includes a substrate having top and bottom surfaces, a semiconductor chip mounted in a centrally located semiconductor chip mounting area of the substrate, and a plurality of test pads disposed on top and bottom surfaces of the substrate and comprising a first group of test pads configured on the top and bottom surfaces of the substrate and having a first height above the respective top and bottom surface of the substrate, and a second group of test pads disposed on the lower surface of the substrate and having a second height greater than the first, wherein each one of the second group of test pads includes a solder ball attached thereto.

Abstract: A semiconductor device is provided. The semiconductor device includes: a substrate; device isolation regions formed in the substrate; an impurity region formed in a region of the substrate between every two adjacent ones of the device isolation regions; a gate electrode formed on the substrate; first and second interlayer insulating films sequentially formed on the substrate; a metal interlayer insulating film formed on the second interlayer insulating film and comprising metal wiring layers; a first contact plug electrically connecting each of the metal wiring layers and the impurity region; and a second contact plug electrically connecting each of the metal wiring layers and the gate electrode, wherein the first contact plug is formed in the first and second interlayer insulating films, and the second contact plug is formed in the second interlayer insulating film.

Abstract: A test system for testing a plurality of semiconductor chips formed on a semiconductor wafer includes: a test wafer on which a plurality of test circuits corresponding to the plurality of semiconductor chips are formed, each test circuit testing a corresponding one of the plurality of semiconductor chips based on test data provided to the test circuit; where each of the plurality of test circuits includes a nonvolatile and rewritable pattern memory for storing the test data such as pattern data and sequence data, and the test system writes the same test data to all the plurality of test circuits in parallel.

Abstract: A combination substrate includes a first substrate having multiple wiring board mounting pads for installing a printed wiring board and multiple connection pads on the opposite side of the wiring board mounting pads, a second substrate having multiple package substrate mounting pads for loading one or more package substrates and multiple connection pads on the opposite side of the package substrate mounting pads, a resin component filling a space between the first substrate and the second substrate, and multiple component loading pads positioned to load an electronic component between the first substrate and the second substrate and formed on one of the first substrate and the second substrate. The connection pads of the second substrate are electrically connected to the connection pads of the first substrate.

Abstract: A semiconductor apparatus includes first and second vias, a first circuit unit, a second circuit unit and a third circuit unit. The first and second vias electrically connect a first chip and a second chip with each other. The first circuit unit is disposed in the first chip, receives test data, and is connected with the first via. The second circuit unit is disposed in the first chip, and is connected with the second via and the first circuit unit. The third circuit unit is disposed in the second chip, and is connected with the first via. The first circuit unit outputs an output signal thereof to one of the first via and the second circuit unit in response to a first control signal.

Abstract: A semiconductor device (5) for radio frequency applications has a semiconductor chip (1) with an integrated circuit accommodated in a radio frequency package. Inside bumps (2) comprise inside contacts between the semiconductor chip (1) and a redistribution substrate (3). The inside bumps (2) have a metallic or plastic core (6) and a coating layer (7) of a noble metal.

Abstract: The transparent photodetector includes a substrate; a waveguide on the substrate; a displaceable structure that can be displaced with respect to the substrate, the displaceable structure in proximity to the waveguide; and a silicon nanowire array suspended with respect to the substrate and mechanically linked to the displaceable structure, the silicon nanowire array comprising a plurality of silicon nanowires having piezoresistance. In operation, a light source propagating through the waveguide results in an optical force on the displaceable structure which further results in a strain on the nanowires to cause a change in electrical resistance of the nanowires. The substrate may be a semiconductor on insulator substrate.

Abstract: A method for manufacturing a plurality of holders each being for an LED package structure includes steps: providing a base, pluralities of through holes being defined in the base to divide the base into a plurality of basic units; etching the base to form a dam at an upper surface of each of the basic units of the base; forming a first electrical portion and a second electrical portion on each basic unit of the base, the first electrical portion and the second electrical portion being separated and insulated from each other by the dam; providing a plurality of reflective cups each on a corresponding basic unit of the base, each of the reflective cups surrounding the corresponding dam; and cutting the base into the plurality of basic units along the through holes to form the plurality of holders.

Abstract: A method of integrating benzocyclobutene (BCB) layers with a substrate is provided along with a corresponding device. A method includes forming a first BCB layer on the substrate and depositing a first metal layer on the first BCB layer and within vias defined by the first metal layer. The method also forms a second BCB layer on the first metal layer and deposits a second metal layer on the second BCB layer and within vias defined by the second metal layer. The second metal layer extends through the vias defined by the second metal layer to establish an operable connection with the first metal layer. The first and second metal layers are independent of an electrical connection to any circuit element carried by the substrate, but the first and second metal layers secure the second BCB layer to the underlying structure and reduce the likelihood of delamination.

Abstract: A semiconductor device includes a first semiconductor chip, a buffer body, and a terminal lead. The first semiconductor chip includes a first electrode and a second electrode provided on a side opposite to the first electrode. The first semiconductor chip is configured to allow a current to flow between the first electrode and the second electrode. The buffer body includes a lower metal foil, a ceramic piece, and an upper metal foil. The lower metal foil is electrically connected to the second electrode. The ceramic piece is provided on the second electrode with the lower metal foil interposed. The upper metal foil is provided on a side of the ceramic piece opposite to the lower metal foil to be electrically connected to the lower metal foil. The terminal lead has one end provided on the upper metal foil and electrically connected to the upper metal foil.

Abstract: A method of manufacturing is provided that includes providing a semiconductor chip device that has a circuit board and a first semiconductor chip coupled thereto. A lid is placed on the circuit board. The lid includes an opening and an internal cavity. A liquid thermal interface material is placed in the internal cavity for thermal contact with the first semiconductor chip and the circuit board.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a bottom integrated circuit over the substrate; connecting a bottom interconnect between the bottom integrated circuit and the substrate; and mounting a bottom shield-spacer above the bottom integrated circuit and the bottom shield-spacer includes a bottom shield plate above the bottom integrated circuit, a bottom shield pillar extending from a bottom shield foot and connected to the bottom shield plate, and a protuberance extending vertically above the bottom shield pillar and directly above the bottom shield foot.

Abstract: A monitoring method of a semiconductor process includes the following steps. A semiconductor substrate is provided, and a test structure is formed thereon. The method of forming the test structure includes the following steps. A first doped region and a second doped region are formed in the semiconductor substrate, and an insulating layer is formed on the semiconductor substrate. Subsequently, a conductive layer is directly formed on the insulating layer to complete the formation of the test structure, in which the conductive layer in a floating state partially overlaps the first doped region and partially overlaps the second doped region. Then, a voltage signal is applied to the test structure and the breakdown voltage (Vbd) between the first doped region and the second doped region is measured.

Abstract: The present power converter includes a power conversion semiconductor device, an electrode connection conductor which electrically connects multiple electrodes having the same potential, and also has a generally flat upper surface for electrically connecting to an exterior portion, and a sealing material provided so as to cover the power conversion semiconductor device, and also to expose the generally flat upper surface of the electrode connection conductor.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor element, a package body and a conductive part. The substrate has an electrical contact. The semiconductor element is disposed on the substrate. The package body covers the semiconductor element and defines a through hole from which the electrical contact is exposed. Wherein, the package body includes a resin body and a plurality of fiber layers. The fiber layers are disposed in the resin body and define a plurality of fiber apertures which is arranged as an array. The conductive part is electrically connected to the substrate through the through hole.

Abstract: Packaged microelectronic elements are provided which include a dielectric element, a cavity, a plurality of chip contacts and a plurality of package contacts, and microelectronic elements having a plurality of bond pads connected to the chip contacts.

Abstract: The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.

Abstract: In order to provide a method of manufacturing a multilayer wiring substrate, a base member having a copper foil separably laminated thereon is prepared, and a solder resist layer is formed on the copper foil. Openings are formed in the solder resist layer, and a metal conductor portion is formed in each of the openings. By means of sputtering, a dissimilar metal layer is formed over the surface of the metal conductor portion and the entire surface of the solder resist layer. Copper electroplating is performed so as to form connection terminals and a conductor layer on the dissimilar metal layer. After a build-up step, the base material is removed, whereby the copper foil is exposed, and the exposed copper foil and the metal conductor portion are removed through etching, whereby the surfaces of the external connection terminals are exposed from the openings.

Abstract: A semiconductor device having a structure that can reduce stress due to difference in coefficients of thermal expansion and prevent or suppress generation of cracks, and a semiconductor device manufacturing method, are provided. The semiconductor device includes a single crystal silicon substrate having a main face on which semiconductor elements are formed and a side face intersecting with the main face, and a sealing resin provided covering at least a portion of the side face. The side face covered by the sealing resin is equipped with a first face with a plane direction forming an angle of ?5° to +5° to the plane direction of the main face.

Abstract: A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.

Abstract: The disclosure relates to a power device package structure. By employing the metal substrate of the power device package structure serve as a bottom electrode of a capacitor, the capacitor is integrated into the power device package structure. A dielectric material layer and a upper metal layer sequentially disposed on the metal substrate.

Abstract: A method and apparatus for alignment are disclosed. An exemplary apparatus includes a substrate having an alignment region; an alignment feature in the alignment region of the substrate; and a dummy feature disposed within the alignment feature. A dimension of the dummy feature is less than a resolution of an alignment mark detector.

Abstract: An electronic device includes a wiring board; a semiconductor device arranged at an upper side of the wiring board with an electrically conductive member being arranged therebetween; a covering member arranged at an upper side of the semiconductor device; and a supporting member arranged at a lower side of the wiring board, the supporting member having a convex portion facing the wiring board, the supporting member being connected to the covering member and supporting the wiring board at the convex portion.

Abstract: The present invention provides a MEMS structure comprising confined sacrificial oxide layer and a bonded Si layer. Polysilicon stack is used to fill aligned oxide openings and MEMS vias on the sacrificial layer and the bonded Si layer respectively. To increase the design flexibility, some conductive polysilicon layer can be further deployed underneath the bonded Si layer to form the functional sensing electrodes or wiring interconnects. The MEMS structure can be further bonded to a metallic layer on top of the Si layer and the polysilicon stack.

Abstract: In a semiconductor module, a first heat sink is disposed on a rear surface of a first semiconductor chip constituting an upper arm, and a second heat sink is disposed on a front surface of the first semiconductor chip through a first terminal. A third heat sink is disposed on a rear surface of a second semiconductor chip constituting a lower arm, and a fourth heat sink is disposed on a front surface of the second semiconductor chip through a second terminal. A connecting part for connecting between the upper arm and the lower arm is integral with the first terminal, and is connected to the third heat sink while being inclined relative to the first terminal.

Abstract: A method of manufacturing a package module structure of a high power device using a metal substrate that can improve reliability by minimizing stress due to a thermal expansion coefficient difference between a metal substrate and a semiconductor device includes: preparing a metal substrate; forming an oxide layer by selectively anodizing the metal substrate; forming a mounting groove for mounting a semiconductor device by etching a portion of the oxide layer; installing a shock-absorbing substrate that is made of a material having a thermal expansion coefficient in a range similar to a material of a semiconductor device to expose the entirety or a portion of a bottom portion of the mounting groove; mounting the semiconductor device in the shock-absorbing substrate exposed to the mounting groove; and electrically connecting an electrode terminal of the semiconductor device and an electrode line formed in an upper surface of the oxide layer.

Abstract: A trench MOSFET layout with multiple trenched floating gates and at least one trenched channel stop gate in termination area shorted with drain region is disclosed to make it feasibly achieved after die sawing. The layout consisted of dual trench MOSFETs connected together with multiple sawing trenched gates across a space between the two trench MOSFETs having a width same as scribe line.

Abstract: A method for producing chip packages is disclosed. In one embodiment, a plurality of chips is provided. The chips each have first pads. Second connection pads are applied on the wafer, wherein each second pad is electrically connected to a first pad.

Abstract: An apparatus comprising connecting IDVMON monitors with through silicon vias (TSV) to allow the monitors to be connected to probe pads located on the backside of the wafer. Because the backside of the wafer have significantly more space than the front side, the probe pads for IDVMON can be accommodated without sacrificing the silicon area.

Abstract: A graphene-on-oxide substrate according to the present invention includes: a substrate having a metal oxide layer formed on its surface; and, formed on the metal oxide layer, a graphene layer including at least one atomic layer of the graphene. The graphene layer is grown generally parallel to the surface of the metal oxide layer, and the inter-atomic-layer distance between the graphene atomic layer adjacent to the surface of the metal oxide layer and the surface atomic layer of the metal oxide layer is 0.34 nm or less. Preferably, the arithmetic mean surface roughness Ra of the metal oxide layer is 1 nm or less.

Abstract: A method of assembling a magnetoresistive random access memory (MRAM) device includes providing a substrate having an opening. A tape is applied to a surface of the substrate and a first magnetic shield is placed onto the tape and within the substrate opening. An adhesive is applied between the first magnetic shield and the substrate to attach the first magnetic shield to the substrate. An MRAM die is attached to the first magnetic shield and bond pads of the MRAM die are connected to pads on the substrate with wires. A second magnetic shield is attached to a top surface of the MRAM die. An encapsulating material is dispensed onto the substrate, the MRAM die, the second magnetic shield and part of the first magnetic shield, cured, and then the tape is removed. Solder balls then may be attached to the substrate.

Abstract: A semiconductor device includes a main current external electrode for connecting a high-voltage main current electrode of a power semiconductor element to the outside, and a resin case into which the main current external electrode is press fitted. The main current external electrode has a press-fitted fixing portion and a claw fixing portion for fixation to the resin case. The claw fixing portion includes a projection passing through a through hole defined in the resin case, and having a bendable claw portion at its tip end.

Abstract: A miniature packaging for a discrete circuit component that comprises a core dice for the circuit component fabricated on a semiconductor substrate. The core dice has at least a pair of metallization electrodes formed on the same or different surfaces of the semiconductor substrate. An end electrode covers a corresponding side surface of the core dice and electrically connects to a corresponding one of the pair of metallization electrodes. The end electrode extends toward the center of the core dice on both the top and bottom surface of the core dice.

Abstract: A three-dimensional semiconductor module and an electronic system including the same are provided. The semiconductor module includes a module substrate, a logic device formed on a part of the module substrate, and a plurality of memory devices formed on another part of the module substrate, wherein the plurality of memory devices are disposed perpendicular to the logic device, and the module substrate on which the plurality of memory devices are formed is supported by a supporter. The electronic system includes the semiconductor module.

Abstract: The present invention discloses a wafer level packaging method and a packaging structure for packaging a first wafer and a second wafer. The first wafer has a back side and an active side, and further, the active side of the first wafer has a MEMS element. The step of forming two through silicon vias is performed first. A first electrical interconnect and a first bonding ring are formed on the active side of the first wafer. The former connects with one of the through silicon vias, the later surrounds the MEMS element and connects with the other of the through silicon vias. The step of forming a second bonding ring and a second electrical interconnect is then performed. And then, a voltage will be applied to the through silicon vias through the back side of the first wafer.

Abstract: The present invention relates to a dicing tape-integrated film for semiconductor back surface including: a dicing tape including a base material and a pressure-sensitive adhesive layer laminated in this order, and a film for semiconductor back surface provided on the pressure-sensitive adhesive layer of the dicing tape, where the pressure-sensitive adhesive layer has a thickness of from 20 ?m to 40 ?m.

Abstract: An optoelectronic interface includes an optically transparent substrate; and an alignment layer comprising a pattern of alignment features disposed on said optically transparent substrate.

Abstract: A semiconductor die includes a group of spacer cells within the semiconductor die. The spacer cells include fiducial markings therein. The fiducial markings can be located within a metal layer, a diffusion layer, a polysilicon layer, and/or a Shallow Trench Isolation (STI) structure.

Abstract: A connecting terminal, a semiconductor package, a wiring board, a connector, and a microcontactor that can achieve a stable contact with a contact target are provided. To achieve the object and to establish an electrical connection to a contact target by making a physical contact with the contact target, there are provided a plurality of conductive terminal-forming members each having a terminal portion, which is extended in a band shape and at least a part of a surface of which forms a curved surface. Each terminal portion is configured so that a part of which is laminated on a part of at least one terminal portion in a thickness direction. All the terminal portions may be laminated at respective tip portions in the thickness direction.

Abstract: An inter-stacking module system is provided by mounting an integrated circuit on a first substrate, the first substrate having a first bond pad, mounting an inter-stacking module substrate over the integrated circuit, forming an inter-stacking module bonding pad on the inter-stacking module substrate, and connecting bond wires between the inter-stacking module bonding pad and the first bond pad.

Abstract: The present invention relates to a dicing tape-integrated film for semiconductor back surface including: a dicing tape including a base material and a pressure-sensitive adhesive layer laminated in this order, and a film for semiconductor back surface provided on the pressure-sensitive adhesive layer of the dicing tape, where the pressure-sensitive adhesive layer has a thickness of from 20 ?m to 40 ?m.

Abstract: An integrated circuit package to package stacking system is provided including providing a first integrated circuit package, having a configured leadframe, providing a second integrated circuit package, having the configured leadframe, and forming an integrated circuit package pair by electrically connecting the configured leadframe of the first integrated circuit package to the configured leadframe of the second integrated circuit package.

Abstract: In order to easily inject underfill resin and perform molding with reliability, groove sections are formed on a surface of a circuit board such that the ends of the groove sections extend to semiconductor elements. Low-viscosity underfill resin applied dropwise is guided by the groove sections and flows between the circuit board and the semiconductor elements. The underfill resin hardly expands to regions outside the semiconductor elements.