Abstract: A system and method for forming a semiconductor device is provided. An embodiment comprises forming a silicide region on a substrate along with a transition region between the silicide region and the substrate. The thickness of the silicide precursor material layer along with the annealing conditions are controlled such that there is a larger ratio of one atomic species within the transition region than another atomic species, thereby increasing the hole mobility within the transition region.

Abstract: A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.

Abstract: A device with improved device performance, and method of manufacturing the same, are disclosed. An exemplary device includes a group III-V compound semiconductor substrate that includes a surface having a (110) crystallographic orientation, and a gate stack disposed over the group III-V compound semiconductor substrate. The gate stack includes a high-k dielectric layer disposed on the surface having the (110) crystallographic orientation, and a gate electrode disposed over the high-k dielectric layer.

Abstract: When patterning metal-containing material layers, such as titanium nitride, in critical manufacturing stages, for instance upon forming sophisticated high-k metal gate electrode structures or providing hard mask materials for patterning a metallization system, the surface adhesion of a resist material on the titanium nitride material may be improved by applying a controlled oxidation process.

Abstract: A strained structure of a semiconductor device is disclosed. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a gate stack on the major surface of the substrate; a shallow trench isolation (STI) disposed on one side of the gate stack, wherein the STI is within the substrate; and a cavity filled with a strained structure distributed between the gate stack and the STI, wherein the cavity comprises one sidewall formed by the STI, one sidewall formed by the substrate, and a bottom surface formed by the substrate, wherein the strained structure comprises a SiGe layer and a first strained film adjoining the sidewall of the STI.

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. The disclosed method comprises forming a wedge-shaped recess with an initial bottom surface in the substrate; transforming the wedge-shaped recess into an enlarged recess with a height greater than the height of the wedge-shaped recess; and epitaxially growing a strained material in the enlarged recess.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate. The semiconductor device includes a gate that is disposed over the substrate. The substrate has a recess. The semiconductor device includes a trench liner that is coated along the recess. The trench liner contains a semiconductor crystal material. The trench liner directly abuts the source/drain stressor device. The semiconductor device also includes a dielectric trench component that is disposed on the trench liner and filling the recess. The semiconductor device includes a source/drain stressor device that is disposed in the substrate. The source/drain stressor device is disposed between the gate and the trench liner.

Abstract: A semiconductor device includes a substrate including an isolation region, and a resistor disposed over the isolation region, wherein the resistor includes an implant with an inverse box-like dopant profile that minimizes resistance variation from subsequent planarization variation. A contact is disposed over the resistor. A method of fabricating such a semiconductor device is also provided.

Abstract: A biosensor with a microfluidic structure surrounded by an electrode and methods of forming the electrode around the microfluidic structure of the biosensor are provided. A method includes forming a gate or electrode in a first layer. The method further includes forming a trench in a second layer. The method further includes forming a first metal layer in the trench such that the first metal layer is in electrical contact with the gate or the electrode. The method further includes forming a sacrificial material in the trench. The method further includes forming a second metal layer over the sacrificial material and in contact with the first metal layer. The method further includes removing the sacrificial material such that a microfluidic channel is formed surrounded by the first and the second metal layers.

Abstract: There is provided a semiconductor device and a method of fabricating the same. The method comprises: providing a semiconductor substrate; forming a transistor structure on the semiconductor substrate, wherein the transistor structure comprises a gate region and a source/drain region, and the gate region comprises a gate dielectric layer provided on the semiconductor substrate and a sacrificial gate formed on the gate dielectric layer; depositing a first interlayer dielectric layer, and planarizing the first interlayer dielectric layer to expose the sacrificial gate; removing the sacrificial gate to form a replacement gate hole; forming first contact holes at positions corresponding to the source/drain region in the first interlayer dielectric layer; and filling a first conductive material in the first contact holes and the replacement gate hole respectively to form first contacts and a replacement gate, wherein the first contacts come into contact with the source/drain region.

Abstract: A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers.

Abstract: The present disclosure provides for methods of fabricating a semiconductor device and such a device. A method includes providing a substrate including at least two isolation features, forming a fin substrate above the substrate and between the at least two isolation features, forming a silicon liner over the fin substrate, and oxidizing the silicon liner to form a silicon oxide liner over the fin substrate.

Abstract: A method for forming a field effect transistor device includes forming a nanowire suspended above a substrate, forming a dummy gate stack on a portion of the substrate and around a portion of the nanowire, removing exposed portions of the nanowire, epitaxially growing nanowire extension portions from exposed portions of the nanowire, depositing a layer of semiconductor material over exposed portions of the substrate, the dummy gate stack and the nanowire extension portions, and removing portions of the semiconductor material to form sidewall contact regions arranged adjacent to the dummy gate stack and contacting the nanowire extension portions.

Abstract: The present invention provides a MOS transistor, including a substrate, a gate oxide, a gate, a source/drain region and a silicide layer. The gate oxide is disposed on the substrate and the gate is disposed on the gate oxide. The source/drain region is disposed in the substrate at two sides of the gate. The silicide layer is disposed on the source/drain region, wherein the silicide layer includes a curved bottom surface. The present invention further provides a manufacturing method of the MOS transistor.

Abstract: In an SOI semiconductor device, substrate diodes may be formed on the basis of a superior design of the contact level and the metallization layer, thereby avoiding the presence of metal lines connecting to both diode electrodes in the critical substrate diode area. To this end, contact trenches may be provided so as to locally connect one type of diode electrodes within the contact level. Consequently, additional process steps for planarizing the surface topography upon forming the contact level may be avoided.

Abstract: A circuit structure includes a first isolation region, and a first dummy gate electrode over and vertically overlapping the first isolation region. First pickup regions of a diode are formed on opposite sides of the first isolation region, wherein sidewalls of the first pickup regions contact opposite sidewalls of the first isolation region. Second pickup regions of the diode are formed on opposite sides of a combined region of the first pickup regions and the first isolation region, wherein the first and the second pickup regions are of opposite conductive types. A well region is under the first and the second pickup regions and the first isolation region, wherein the well region is of a same conductivity type as the second pickup regions.

Abstract: Transistor devices having a self-aligned gate structure on transparent substrates and techniques for fabrication thereof are provided. In one aspect, a method of fabricating a transistor device includes the following steps. A channel material is formed on a transparent substrate. Source and drain electrodes are formed in contact with the channel material. A dielectric layer is deposited on the channel material. A photoresist is deposited on the dielectric layer and developed using UV light exposure through the transparent substrate. A gate metal(s) is deposited on the exposed portions of the dielectric layer and the undeveloped portions of the photoresist. The undeveloped portions of the photoresist are removed along with portions of the gate metal over the source and drain regions to form a gate of the device on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes.

Abstract: Disclosed herein are various methods of epitaxially forming materials on transistor devices. In one example, the method includes forming an isolation region in a semiconducting substrate that defines an active area, performing a heating process on the active area to cause an upper surface of the active area to become a curved surface and performing an etching process on the active area to define a recess having a curved bottom surface. The method further includes the steps of forming a channel semiconductor material in the recess with a curved upper surface and forming a gate structure for a transistor above the curved upper surface of the channel semiconductor material.

Abstract: A method for fabricating a field effect transistor with fin structure includes the following steps. A substrate having an ion well with a first conductivity type is provided, wherein the ion well has a first doping concentration. At least a fin structure disposed on the substrate is formed. At least a first ion implantation is performed to form an anti-punch doped region with first conductivity type between the substrate and the channel layer, wherein the anti-punch doped region has a third doping concentration higher than the first doping concentration. At least a channel layer disposed along at least one surface of the fin structure is formed after the first ion implantation is performed. A gate covering part of the fin structure is formed. A source and a drain disposed in the fin structure beside the gate are formed, wherein the source and the drain have a second conductivity type.

Abstract: A semiconductor device includes a gate stacked structure including a gate dielectric layer over a semiconductor substrate, a metal layer formed over the gate dielectric layer, and a capping layer formed over the metal layer, where the capping layer includes a chemical element with a higher concentration at an interface between the capping layer and the metal layer than another region of the capping layer and the chemical element is operable to control an effective work function (eWF) of the gate stacked structure.

Abstract: The invention relates to an electronic device, comprising a field effect transistor and a resistive switch electrically coupled with each other, wherein the resistive switch is configured to be switched between a state of low resistance and a state of high resistance.

Abstract: Semiconductor devices and related fabrication methods are provided. An exemplary fabrication method involves forming a pair of gate structures having a dielectric region disposed between a first gate structure of the pair and a second gate structure of the pair, and forming a voided region in the dielectric region between the first gate structure and the second gate structure. The first and second gate structures each include a first gate electrode material, wherein the method continues by removing the first gate electrode material to provide second and third voided regions corresponding to the gate structures and forming a second gate electrode material in the first voided region, the second voided region, and the third voided region.

Abstract: The present disclosure provides a method including providing a substrate having a first opening and a second opening on the substrate. A blocking layer is formed in the first opening. A second metal gate electrode is formed the second opening while the blocking layer is in the first opening. The blocking layer is then removed from the first opening, and a first metal gate electrode formed. In embodiments, this provides for a device having a second gate electrode that includes a second work function layer and not a first work function layer, and the first gate electrode includes the first work function layer and not the second work function layer.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure including one or more fins disposed on the substrate. The semiconductor device further includes a dielectric layer disposed on a central portion of the fin structure and traversing each of the one or more fins. The semiconductor device further includes a work function metal disposed on the dielectric layer and traversing each of the one or more fins. The semiconductor device further includes a strained material disposed on the work function metal and interposed between each of the one or more fins. The semiconductor device further includes a signal metal disposed on the work function metal and on the strained material and traversing each of the one or more fins.

Abstract: In some embodiments, a metal insulator semiconductor heterostructure field effect transistor (MISHFET) is disclosed that has a source, a drain, an insulation layer, a gate dielectric, and a gate. The source and drain are on opposing sides of a channel region of a channel layer. The channel region is an upper portion of the channel layer. The channel layer comprises gallium nitride. The insulation layer is over the channel layer and has a first portion and a second portion. The first portion is nearer the drain than the source and has a first thickness. The second portion is nearer the source than drain and has the first thickness. The insulation layer has an opening through the insulation layer. The opening is between the first portion and the second portion.

Abstract: A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.

Abstract: The present invention relates to a method of manufacturing a semiconductor device, and the method uses the mode of thermal annealing the source/drain regions and performing Halo ion implantation to form a Halo ion-implanted region by: first removing the dummy gate to expose the gate dielectric layer to form an opening; then performing a tilted Halo ion implantation to the device from the opening to form a Halo ion-implanted region on both sides of the channel of the semiconductor device; and then annealing to activate the dopants in the Halo ion-implanted region; finally performing subsequent process to the device according to the requirement of the manufacture process.

Abstract: Power MOS device of the type comprising a plurality of elementary power MOS transistors having respective gate structures and comprising a gate oxide with double thickness having a thick central part and lateral portions of reduced thickness. Such device exhibiting gate structures comprising first gate conductive portions overlapped onto said lateral portions of reduced thickness to define, for the elementary MOS transistors, the gate electrodes, as well as a conductive structure or mesh. Such conductive structure comprising a plurality of second conductive portions overlapped onto the thick central part of gate oxide and interconnected to each other and to the first gate conductive portions by means of a plurality of conducive bridges.

Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.

Abstract: In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided.

Abstract: A compound semiconductor device includes an electron transit layer having a first polarity, a p-type cap layer which is formed above the electron transit layer and has a second polarity, and an n-type cap layer which is formed on the p-type cap layer and has the first polarity. The n-type cap layer includes portions having different thicknesses.

Abstract: The present invention discloses a thin film transistor (TFT), a manufacturing method thereof, an array substrate, and a liquid crystal display (LCD) device. The TFT comprises a gate electrode and a source electrode. The gate electrode comprises a first metal layer block and a second metal layer block positioned on the first metal layer block. The thermal expansion coefficient of the second metal layer block is less than that of the first metal layer block. The top surface of the first metal layer block is in contact with the bottom surface of the second metal layer block, and the width of the top surface of the first metal layer block accords with that of the bottom surface of the second metal layer block. The present invention can prevent hillocks from being produced, and can effectively avoid the phenomenon of electricity leakage.

Abstract: A method for fabricating a semiconductor device is disclosed. A strained material is formed in a cavity of a substrate and adjacent to an isolation structure in the substrate. The strained material has a corner above the surface of the substrate. The disclosed method provides an improved method for forming the strained material adjacent to the isolation structure with an increased portion in the cavity of the substrate to enhance carrier mobility and upgrade the device performance. The improved formation method is achieved by providing a treatment to redistribute at least a portion of the corner in the cavity.

Abstract: Transistor devices and methods of their fabrication are disclosed. In one method, a dummy gate structure is formed on a substrate. Bottom portions of the dummy gate structure are undercut. In addition, stair-shaped, raised source and drain regions are formed on the substrate and within at least one undercut formed by the undercutting. The dummy gate structure is removed and a replacement gate is formed on the substrate.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure disposed over the substrate. The fin structure includes one or more fins. The semiconductor device further includes an insulation material disposed on the substrate. The semiconductor device further includes a gate structure disposed on a portion of the fin structure and on a portion of the insulation material. The gate structure traverses each fin of the fin structure. The semiconductor device further includes a source and drain feature formed from a material having a continuous and uninterrupted surface area. The source and drain feature includes a surface in a plane that is in direct contact with a surface in a parallel plane of the insulation material, each of the one or more fins of the fin structure, and the gate structure.

Abstract: A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer. Methods for forming a device with reduced gate resistance are also provided.

Abstract: Transistor devices including stressors are disclosed. One such transistor device includes a channel region, a dielectric layer and a semiconductor substrate. The channel region is configured to provide a conductive channel between a source region and a drain region. In addition, the dielectric layer is below the channel region and is configured to electrically insulate the channel region. Further, the semiconductor substrate, which is below the channel region and below the dielectric layer, includes dislocation defects at a top surface of the semiconductor substrate, where the dislocation defects are collectively oriented to impose a compressive strain on the channel region such that charge carrier mobility is enhanced in the channel region.

Abstract: A transistor includes a semiconductor layer, and a gate dielectric is formed on the semiconductor layer. A gate conductor is formed on the gate dielectric and an active area is located in the semiconductor layer underneath the gate dielectric. The active area includes a graded dopant region that has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer. This graded dopant region has a gradual decrease in the doping concentration. The transistor also includes source and drain regions that are adjacent to the active region. The source and drain regions and the active area have the same conductivity type.

Abstract: A circuit board assembly includes a circuit board, a chip attached to the circuit board and a dielectric layer. The chip has a circuit facing the circuit board and spaced from it. The dielectric layer includes an aerogel. In one embodiment, the aerogel has a dielectric constant of approximately 2.0 or less and a compression strength of at least approximately 100 psi.

Abstract: A multi-layer scavenging metal gate stack, and methods of manufacturing the same, are disclosed. In an example, a gate stack disposed over a semiconductor substrate includes an interfacial dielectric layer disposed over the semiconductor substrate, a high-k dielectric layer disposed over the interfacial dielectric layer, a first conductive layer disposed over the high-k dielectric layer, and a second conductive layer disposed over the first conductive layer. The first conductive layer includes a first metal layer disposed over the high-k dielectric layer, a second metal layer disposed over the first metal layer, and a third metal layer disposed over the second metal layer. The first metal layer includes a material that scavenges oxygen impurities from the interfacial dielectric layer, and the second metal layer includes a material that adsorbs oxygen impurities from the third metal layer and prevents oxygen impurities from diffusing into the first metal layer.

Abstract: According to example embodiments, an electrode structure includes a graphene layer on a semiconductor layer and an electrode containing metal on the graphene layer. A field effect transistor (FET) may include the electrode structure.

Abstract: The present invention discloses a nanowire fabrication method and a semiconductor element using a nanowire fabricated thereby. The method of the present invention comprises steps: providing a substrate; sequentially depositing a silicon dioxide layer and a silicon nitride layer on the substrate; forming a patterned photoresist layer on the silicon nitride layer; using the patterned photoresist layer as a mask to etch the silicon nitride layer and the silicon dioxide layer with the substrate partly etched away to form a protrusion; removing the patterned photoresist layer to form an isolation layer; removing the silicon nitride and the silicon dioxide layer, sequentially depositing a dielectric layer and a polysilicon layer; and anisotropically etching the polysilicon layer to form nanowires on a region of the dielectric layer, which is around sidewalls of the protrusion.

Abstract: The present invention provides an ion sensor with which an ion concentration in a sample in which both ions are mixed can be measured with high accuracy, a display device, a method for driving the ion sensor, and a method for calculating an ion concentration. The present invention is an ion sensor that includes a field effect transistor. The ion sensor detects one of negative ions and positive ions using the field effect transistor, and consecutively thereafter detects the other of the negative ions and positive ions using the field effect transistor.

Abstract: Embodiments of a strained semiconductor device are provided, as are embodiments of a method for fabricating such a strained semiconductor device. In one embodiment, the method includes providing a partially-fabricated semiconductor device including a semiconductor substrate having a source side and a drain side, a gate stack formed on the semiconductor substrate, and a channel region formed within the semiconductor substrate beneath the gate stack and extending from the source side to the drain side of the semiconductor substrate. A cavity is produced in only one of the source side and the drain side of the semiconductor substrate, and a strain-inducing material is formed within the cavity to create an asymmetric heterojunction structure within the semiconductor substrate.

Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.

Abstract: An electronic module includes a first semiconductor chip and a passive component, wherein the first semiconductor chip is arranged on a surface of the passive component.

Abstract: A ferro-electric random access memory (FRAM) chip, including a substrate; a first dielectric layer over the substrate; a gate over the first dielectric layer; a first aluminum oxide layer over the first dielectric layer and the gate; a second dielectric layer over the first aluminum oxide layer; a trench through the second dielectric layer and the first aluminum oxide layer to the gate; a hydrogen barrier liner over the second dielectric layer and lining the trench, and contacting the gate; and a silicon dioxide plug over the hydrogen barrier liner substantially filling the trench.

Abstract: A MOS transistor has a first stress layer formed over a silicon substrate on a first side of a channel region defined by a gate electrode, and a second stress layer formed over the silicon substrate on a second side of the channel region, the first and second stress layers accumulating a tensile stress or a compressive stress depending on a conductivity type of the MOS transistor. The first stress layer has a first extending part rising upward from the silicon substrate near the channel region along a first sidewall of the gate electrode but separated from the first sidewall of the gate electrode, and the second stress layer has a second extending part rising upward from the silicon substrate near the channel region along a second sidewall of the gate electrode but separated from the second sidewall of the gate electrode. The accumulated stress is the tensile stress if the conductivity type is an n-type, and is a compressive stress if the conductivity type is a p-type.

Abstract: A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.

Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.