Contacting Multiple Semiconductive Regions (i.e., Interconnects) Patents (Class 438/618)
  • Patent number: 9153484
    Abstract: A method of forming an integrated circuit comprises forming a gate of a transistor over a substrate. The method further comprises forming a connecting line over the substrate, the connecting line being coupled with an active area of the transistor. The method also comprises forming a dielectric layer surrounding the gate and the connecting line. The method additionally comprises forming an etch stop layer over the dielectric layer and covering a portion of a top surface of the connecting line. The method further comprises forming a via structure comprising a via in physical contact with a top surface of the gate and another portion of the top surface of the connecting line. The method also comprises forming a metallic line structure being coupled with the via structure.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: October 6, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chii-Ping Chen, Dian-Hau Chen
  • Patent number: 9136206
    Abstract: A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: September 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Lin Su, Ching-Hua Hsieh, Huang-Ming Chen, Hsueh Wen Tsau
  • Patent number: 9123781
    Abstract: Semiconductor devices and methods for forming the same in which damages to a low-k dielectric layer therein can be reduced or even prevented are provided. A semiconductor device is provided, comprising a substrate. A dielectric layer with at least one conductive feature therein overlies the substrate. An insulating cap layer overlies the top surface of the low-k dielectric layer adjacent to the conductive feature, wherein the insulating cap layer comprises metal ions.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: September 1, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Hung-Wen Su, Shih-Wei Chou, Ming-Hsing Tsai
  • Patent number: 9111907
    Abstract: A semiconductor transistor has a structure including a semiconductor substrate, a source region, a drain region and a channel region in between the source region and the drain region. A metal gate, having a top conductive portion of tungsten is provided above the channel region. A first silicon nitride protective layer over the source region and the drain region and a second silicon nitride protective layer over the gate region are provided. The first silicon nitride protective layer and the second silicon nitride protective layer are configured to allow punch-through of the first silicon nitride protective layer while preventing etching through the second silicon nitride protective layer. Source and drain silicide is protected by avoiding fully etching a gate opening unless either the etching used would not harm the silicide, or the silicide and source and drain contacts are created prior to fully etching an opening to the gate for a gate contact.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: August 18, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vimal K. Kamineni, Ruilong Xie, Robert Miller
  • Patent number: 9087771
    Abstract: A method for manufacturing a semiconductor device includes: forming a structure including a substrate, a device layer formed on the substrate, a pair of through-hole electrodes penetrating through the substrate in the thickness direction of the substrate, a pair of vertical electrodes extending in the thickness direction of the substrate and reaching to one surface of the substrate, and a shared wiring connecting the pair of vertical electrodes in the device layer; forming a connection wiring connecting one of the through-hole electrodes and one of the vertical electrodes; and stacking the structure and a second substrate such that an electrode of the second substrate is connected to a through-hole electrode which is not connected to the connection wiring among the pair of through-hole electrodes.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: July 21, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Haruo Iwatsu, Toshiyuki Matsumoto
  • Patent number: 9082829
    Abstract: Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed patterns of crossing elongate features with pillars at the intersections. Spacers are simultaneously applied to sidewalls of both sets of crossing lines to produce a pitch-doubled grid pattern. The pillars facilitate rows of spacers bridging columns of spacers.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: July 14, 2015
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: David H. Wells
  • Patent number: 9082824
    Abstract: A method of making a semiconductor device having a substrate includes forming a first interconnect layer over the substrate, wherein a first metal portion of a first metal type is within the first interconnect layer and has a first via interface location. An interlayer dielectric is formed over the first interconnect layer. An opening in the interlayer dielectric is formed over the via interface location of the first metal portion. A second interconnect layer is formed over the interlayer dielectric. A second metal portion and a via of the first metal type is within the second interconnect layer. The via is formed in the opening to form an electrical contact between the first metal portion and the second metal portion. The via is over the first via interface location. A first implant of the first metal type is aligned to the first via interface location.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: July 14, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Douglas M. Reber, Mehul D. Shroff, Edward O. Travis
  • Patent number: 9082885
    Abstract: A method of manufacturing a semiconductor device includes: providing a first substrate that includes internal wiring, the first substrate including an array of chip mounting regions that includes a first chip mounting region; placing the first substrate on a first carrier line; providing a first semiconductor chip; placing the first semiconductor chip on a first moveable tray; vertically aligning the first chip mounting region of the first substrate with the first semiconductor chip, and performing initial bonding of the first semiconductor chip to the first chip mounting region of the first substrate; and performing subsequent bonding on the initially-bonded first semiconductor chip and first mounting region of the first substrate, thereby more strongly bonding the first semiconductor chip to the first substrate at the first mounting region. The initial bonding occurs after performing a subsequent bonding of at least one other semiconductor chip on the first substrate.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: July 14, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoshiaki Yukimori, Shinji Ueyama, Masato Kajinami
  • Patent number: 9054068
    Abstract: Capacitor structures for integrated circuit devices are provided. Capacitors include proximate dense or highly dense etchstop layers. The dense or highly dense etchstop layer is, for example, a high-k material. Capacitors are, for example, metal-insulator-metal (MIM) capacitors and are useful in DRAM (dynamic random access memory) and eDRAM (embedded dynamic random access memory) structures.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: June 9, 2015
    Assignee: Intel Corporation
    Inventor: Ruth A. Brain
  • Patent number: 9048147
    Abstract: A display device of which frame can be narrowed and of which display characteristics are excellent is provided. In a display device including a switch portion or a buffer portion, a logic circuit portion, and a pixel portion, the pixel portion includes a first inverted staggered TFT and a pixel electrode which is connected to a wiring of the first inverted staggered TFT, the switch portion or the buffer portion includes a second inverted staggered TFT in which a first insulating layer, a semiconductor layer, and a second insulating layer are interposed between a first gate electrode and a second gate electrode, the logic circuit portion includes an inverter circuit including a third inverted staggered thin film transistor and a fourth inverted staggered thin film transistor, and the first to the fourth inverted staggered thin film transistors have the same polarity. The inverter circuit may be an EDMOS circuit.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 2, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takeshi Osada, Hidekazu Miyairi, Yasuhiro Jinbo
  • Patent number: 9048182
    Abstract: A semiconductor device manufacturing method, the method including: forming an insulation layer having a protruding portion, the insulation layer having a surface and a rising surface that protrudes upward from the surface, on a semiconductor substrate; forming a conductive layer to cover the insulation layer having the protruding portion; and removing a predetermined region of the conductive layer by patterning the predetermined region according to an etching process using microwave plasma, which uses a microwave as a plasma source, while applying bias power of 70 mW/cm2 or above on the semiconductor substrate, under a high pressure condition of 85 mTorr or above.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: June 2, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tetsuya Nishizuka, Masahiko Takahashi
  • Publication number: 20150145055
    Abstract: Disclosed is a high voltage device including a substrate structure having a high voltage transistor and a lower wiring connected to the high voltage transistor, a linker structure having a supplemental insulation pattern on the substrate structure and an interconnecting linker penetrating through the supplemental insulation pattern and connected to the lower wiring, an insulation interlayer pattern on the supplemental insulation pattern, and an upper wiring structure penetrating through insulation interlayer pattern and connected to the interconnecting linker. The thickness of the inter-metal dielectric layer between the upper and the lower wirings is increased to thereby improve the insulation characteristics of the inter-metal dielectric layer. As a result, the breakdown voltage and the current leakage characteristics of the high voltage device are improved.
    Type: Application
    Filed: October 9, 2014
    Publication date: May 28, 2015
    Inventor: Jong-Sam KIM
  • Patent number: 9039940
    Abstract: A conductive paste may include a conductive component and an organic vehicle. The conductive component may include an amorphous metal. The amorphous metal may have a lower resistivity after a crystallization process than before the crystallization process, and at least one of a weight gain of about 4 mg/cm2 or less and a thickness increase of about 30 ?m or less after being heated in a process furnace at a firing temperature.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: May 26, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Suk Jun Kim, Eun Sung Lee, Se Yun Kim, Sang Soo Jee, Jeong Na Heo
  • Patent number: 9040415
    Abstract: A method for forming a trench includes etching an oxide layer to form a trench therein, conformally forming a first reaction layer along a surface of the trench, the first reaction layer including a first region on an upper portion of the trench and a second region on a lower portion of the trench, forming a barrier layer by reacting a first amount of etching gas with the first region of the first reaction layer, and etching the oxide layer on a lower portion of the second region by reacting a second amount of etching gas with the second region of the first reaction layer, the second amount of etching gas being greater than the first amount of etching gas.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: May 26, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Bo-Un Yoon, Young-Sang Youn, Jeong-Nam Han, Kee-Sang Kwon, Doo-Sung Yun, Byung-Kwon Cho, Ji-Hoon Cha
  • Patent number: 9040414
    Abstract: A semiconductor device and methods directed toward preventing a leakage current between a contact plug and a line adjacent to the contact plug, and minimizing capacitance between adjacent lines.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: May 26, 2015
    Assignee: SK Hynix Inc.
    Inventor: Young Jin Lee
  • Publication number: 20150137380
    Abstract: An electronic device incorporating a randomized interconnection layer. In one example, the device includes a randomized interconnection layer having a randomized conductive pattern formed by etching of a heterogeneous layer; and a sensing circuit, electrically coupled to the randomized interconnection layer to detect the randomized conductive pattern. In another example, a method of fabricating the device includes forming a set of electrodes proximate to a silicon substrate; depositing a heterogeneous layer of elements onto the substrate; etching the heterogeneous layer to form a randomized conductive pattern; and electrically coupling the electrodes to a sensing circuit and the randomized conductive pattern.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 21, 2015
    Applicant: NXP B.V.
    Inventors: Michael Antoine Armand in 't Zandt, Viet Hoang Nguyen
  • Publication number: 20150140803
    Abstract: Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such methods may include filling a plurality of trenches in a substrate with a dielectric material and removing portions of the substrate between the dielectric material to form a plurality of openings. In some embodiments, portions of the substrate may be undercut to form a continuous void underlying the bodies and the continuous void may be filled with a conductive material. In other embodiments, portions of the substrate exposed within the openings may be converted to a silicide material to form a conductive material under the bodies. For example, the conductive material may be used as a conductive line to electrically interconnect memory device components. Semiconductor structures and devices formed by such methods are also disclosed.
    Type: Application
    Filed: January 28, 2015
    Publication date: May 21, 2015
    Inventors: David H. Wells, Gurtej S. Sandhu
  • Publication number: 20150137371
    Abstract: The invention provides a fast, scalable, room temperature process for fabricating metallic nanorods from nanoparticles or fabricating metallic or semiconducting nanorods from carbon nanotubes suspended in an aqueous solution. The assembled nanorods are suitable for use as nanoscale interconnects in CMOS-based devices and sensors. Metallic nanoparticles or carbon nanotubes are assembled into lithographically patterned vias by applying an external electric field. Since the dimensions of nanorods are controlled by the dimensions of vias, the nanorod dimensions can be scaled down to the low nanometer range. The aqueous assembly process is environmentally friendly and can be used to make nanorods using different types of metallic particles as well as semiconducting and metallic nanotubes.
    Type: Application
    Filed: December 15, 2014
    Publication date: May 21, 2015
    Inventors: Ahmed Busnaina, Cihan Yilmaz, TaeHoon Kim, Sivasubramanian Somu
  • Patent number: 9034664
    Abstract: A method of repairing hollow metal void defects in interconnects and resulting structures. After polishing interconnects, hollow metal void defects become visible. The locations of the defects are largely predictable. A repair method patterns a mask material to have openings over the interconnects (and, sometimes, the adjacent dielectric layer) where defects are likely to appear. A local metal cap is formed in the mask openings to repair the defect. A dielectric cap covers the local metal cap and any recesses formed in the adjacent dielectric layer.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Griselda Bonilla, Junjing Bao, Samuel S. Choi, Ronald G. Filippi, Naftali E. Lustig, Andrew H. Simon
  • Publication number: 20150130062
    Abstract: Method for forming an interconnect structure, comprising the steps of: forming a recessed structure in a dielectric material on a substrate; at least partially filling said recessed structure with a metal chosen from the group consisting of copper, nickel and cobalt; introducing the substrate in a CVD reactor; bringing the substrate in the CVD reactor to a soak temperature and subsequently performing a soak treatment by supplying a germanium precursor gas to the CVD reactor at the soak temperature, thereby substantially completely converting the metal in the recessed structure to a germanide.
    Type: Application
    Filed: May 14, 2013
    Publication date: May 14, 2015
    Applicant: IMEC VZW
    Inventors: Laure Elisa Carbonell, Antony Premkumar Peter, Marc Schaekers, Sven Van Elshocht, Zsolt Tokei
  • Publication number: 20150132943
    Abstract: Provided is a method of manufacturing a semiconductor device. The method includes forming isolated contact filling portions and an etch control portion, the isolated contact filling portions filling contact holes defined in a support layer and are spaced apart from each other in a first direction and a second direction perpendicular to the first direction and the etch control layer surrounding the isolated contact filling portions, forming an interconnection layer on the isolated contact filling portions and the etch control portion, and forming interconnection patterns by photo-etching the interconnection layer, the isolated contact patterns, and the etch control portion, the interconnection patterns being relatively narrow in the first direction and relatively wide in the second direction.
    Type: Application
    Filed: November 12, 2014
    Publication date: May 14, 2015
    Inventors: Dae-ik KIM, Hyoung-sub KIM, Yoo-sang HWANG
  • Publication number: 20150132942
    Abstract: Provided is a method of manufacturing a semiconductor device. The method includes: forming bit line structures spaced apart from each other by first groove disposed in first direction, extending in first direction, and spaced apart from each other in second direction perpendicular to first direction, on substrate in which word line is buried; forming multilayer spacer on both sidewalls of bit line structure; forming sacrificial layer to fill first groove; forming second grooves spaced apart from each other in first direction and second direction, by patterning sacrificial layer; etching outermost spacer of multilayer spacer located in second groove; forming first supplementary spacer in second groove; forming insulating layer to fill second groove; and forming third grooves spaced apart from each other in first direction and second direction, on both sides of first supplementary spacer, by removing sacrificial layer and insulating layer.
    Type: Application
    Filed: November 12, 2014
    Publication date: May 14, 2015
    Inventors: Dae-ik Kim, Hyoung-sub Kim, Yoo-sang Hwang, Ji-young Kim
  • Patent number: 9029193
    Abstract: A semiconductor device has a first interconnect structure formed over a first side of a substrate. A semiconductor die is mounted to the first interconnect structure. An encapsulant is deposited over the semiconductor die and first interconnect structure for structural support. A portion of a second side of the substrate, opposite the first side of the substrate, is removed to reduce its thickness. The encapsulant maintains substrate robustness during thinning process. A TSV is formed through the second side of the substrate to the first interconnect structure. A second interconnect structure is formed in the TSV. The TSV has a first insulating layer formed over the second side of the substrate and first conductive layer formed over the first insulating layer and into the TSV. The second interconnect structure has a second conductive layer formed over the first conductive layer in an area away from the TSV.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: May 12, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Pandi Chelvam Marimuthu, Nathapong Suthiwongsunthorn, Kock Liang Heng
  • Publication number: 20150123192
    Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines.
    Type: Application
    Filed: January 6, 2015
    Publication date: May 7, 2015
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Hsiung Hung, Shin-Jang Shen, Hang-Ting Lue
  • Publication number: 20150118837
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.
    Type: Application
    Filed: October 30, 2013
    Publication date: April 30, 2015
    Inventors: Ming-Feng Shieh, Wen-Hung Tseng, Hung-Chang Hsieh
  • Publication number: 20150115442
    Abstract: A redistribution layer for a chip is provided, wherein the redistribution layer comprises at least one electrical conductor path connecting two connection points with each other, wherein the at least one electrical conductor path is arranged on a planar supporting layer and wherein the electrical conductor path comprises copper and at least one other further electrical conductive material in an amount of more than 0.04 mass percent.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Applicant: Infineon Technologies AG
    Inventors: Georg MEYER-BERG, Reinhard Pufall
  • Patent number: 9018090
    Abstract: Borderless self-aligned metal contacts to high density complementary metal oxide semiconductor (CMOS) circuits and methods for constructing the same. An example method includes creating an enclosed region for metal deposition defined by the gates of the adjacent transistors and an opposing pair of dielectric walls adjacent to source regions and drain regions of the adjacent transistors. The method further includes depositing a metal layer within the enclosed region. The metal contacts thus formed are self-aligned to the enclosed regions.
    Type: Grant
    Filed: October 10, 2011
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Sebastian U. Engelmann, Nicholas C. M. Fuller, Michael A. Guillorn, Eric A. Joseph, Adam M. Pyzyna
  • Patent number: 9018092
    Abstract: A plurality of metal tracks are formed in an integrated circuit die in three metal layers stacked within the die. A protective dielectric layer is formed around metal tracks of an intermediate metal layer. The protective dielectric layer acts as a hard mask to define contact vias between metal tracks in the metal layers above and below the intermediate metal layer.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: April 28, 2015
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu
  • Patent number: 9018089
    Abstract: A method of annealing a semiconductor and a semiconductor. The method of annealing including heating the semiconductor to a first temperature for a first period of time sufficient to remove physically-adsorbed water from the semiconductor and heating the semiconductor to a second temperature, the second temperature being greater than the first temperature, for a period of time sufficient to remove chemically-adsorbed water from the semiconductor. A semiconductor device including a plurality of metal conductors, and a dielectric including regions separating the plurality of metal conductors, the regions including an upper interface and a lower bulk region, the upper interface having a density greater than a density of the lower bulk region.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Eric G. Liniger, Griselda Bonilla, Pak Leung, Stephen A. Cohen, Stephen M. Gates, Thomas M. Shaw
  • Publication number: 20150111376
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides multiple interconnect wires in the form of a ribbon between the bond pads, and then subsequently separates the ribbon into multiple individual interconnect wires.
    Type: Application
    Filed: December 30, 2014
    Publication date: April 23, 2015
    Inventor: Jayna Sheats
  • Patent number: 9006039
    Abstract: A fabrication method of a packaging substrate includes: providing a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; forming a first encapsulant in the first openings; forming a second encapsulant in the second openings; and forming a surface circuit layer on the first encapsulant and the first core circuit layer.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: April 14, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chi-Ching Ho, Yu-Chih Yu, Ying-Chou Tsai
  • Publication number: 20150097295
    Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A first conductive layer having first and second segments is formed over a surface of the substrate with a first vent separating an end of the first segment and the second segment and a second vent separating an end of the second segment and the first segment. A second conductive layer is formed over the surface of the substrate to electrically connect the first segment and second segment. The thickness of the second conductive layer can be less than a thickness of the first conductive layer to form the first vent and second vent. The semiconductor die is mounted to the substrate with the bumps aligned to the first segment and second segment. Bump material from reflow of the bumps is channeled into the first vent and second vent.
    Type: Application
    Filed: December 16, 2014
    Publication date: April 9, 2015
    Applicant: STATS CHIPPAC, LTD.
    Inventors: JaeHyun Lee, SunJae Kim, JoongGi Kim
  • Publication number: 20150097292
    Abstract: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.
    Type: Application
    Filed: December 12, 2014
    Publication date: April 9, 2015
    Inventors: Jun HE, Kevin J. FISCHER, Ying ZHOU, Peter K. MOON
  • Patent number: 8999740
    Abstract: A solar cell according to an embodiment of the invention includes a substrate configured to have a plurality of via holes and a first conductive type, an emitter layer placed in the substrate and configured to have a second conductive type opposite to the first conductive type, a plurality of first electrodes electrically coupled to the emitter layer, a plurality of current collectors electrically coupled to the first electrodes through the plurality of via holes, and a plurality of second electrodes electrically coupled to the substrate. The plurality of via holes includes at least two via holes having different angles.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 7, 2015
    Assignee: LG Electronics Inc.
    Inventors: Daehee Jang, Jihoon Ko, Juwan Kang, Jonghwan Kim
  • Patent number: 8999827
    Abstract: A method of manufacturing a semiconductor device, includes: forming a first and second interconnect trenches adjacent to each other in an interlayer insulating film; providing a first interconnect and a space thereon within the first interconnect trench, and a second interconnect and a space thereon within the second interconnect trench; forming a first trench larger in width from the first interconnect trench and a second trench larger in width from the second interconnect trench, by conducting isotropic-etching; and forming a first insulating film within the first trench and a second insulating film within the second trench by filling an insulating material in the first trench and the second trench.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: April 7, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Toshiyuki Hirota
  • Patent number: 9000594
    Abstract: A contiguous layer of graphene is formed on exposed sidewall surfaces and a topmost surface of a copper-containing structure that is present on a surface of a substrate. The presence of the contiguous layer of graphene on the copper-containing structure reduces copper oxidation and surface diffusion of copper ions and thus improves the electromigration resistance of the structure. These benefits can be obtained using graphene without increasing the resistance of copper-containing structure.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: John A. Ott, Ageeth A. Bol
  • Publication number: 20150093891
    Abstract: Methods for depositing a metal layer in a feature definition of a semiconductor device are provided. In one implementation, a method for depositing a metal layer for forming a semiconductor device is provided. The method comprises performing a cyclic metal deposition process to deposit a metal layer on a substrate and annealing the metal layer disposed on the substrate. The cyclic metal deposition process comprises exposing the substrate to a deposition precursor gas mixture to deposit a portion of the metal layer on the substrate, exposing the portion of the metal layer to either a plasma treatment process or hydrogen annealing process and repeating the exposing the substrate to a deposition precursor gas mixture and exposing the portion of the metal layer to either a plasma treatment process or hydrogen annealing process until a predetermined thickness of the metal layer is achieved.
    Type: Application
    Filed: September 10, 2014
    Publication date: April 2, 2015
    Inventors: Bhushan N. ZOPE, Avgerinos V. GELATOS, Bo ZHENG, Yu LEI, Xinyu FU, Srinivas GANDIKOTA, Sang Ho YU, Mathew ABRAHAM
  • Publication number: 20150091062
    Abstract: According to one embodiment, a semiconductor element includes a first semiconductor layer, a second semiconductor layer, a first electrode, a second electrode, a control electrode, a pad unit, an insulating layer, and a conductor. The second semiconductor layer is provided on the first semiconductor layer. The first electrode is provided on the second semiconductor layer. The second electrode is provided on the second semiconductor layer. The control electrode is provided on the second semiconductor layer. The pad unit is provided on the second semiconductor layer. The pad unit is electrically connected to the control electrode. The insulating layer is provided on the second semiconductor layer. The insulating layer has an opening. The conductor is provided on the insulating layer. The conductor covers at least a part of the opening.
    Type: Application
    Filed: September 3, 2014
    Publication date: April 2, 2015
    Inventor: Takako Motai
  • Publication number: 20150091191
    Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer and/or polymer layer disposed over the substrate and a portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to an exposed portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes a stepped region.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventors: Jie Chen, Hsien-Wei Chen, Ying-Ju Chen
  • Patent number: 8993439
    Abstract: A method of manufacturing a semiconductor device, including forming a molding layer; forming a damascene mask layer and mask layer on the molding layer; forming a mask layer pattern by etching the mask layer; forming a damascene pattern by partially etching the damascene mask layer; forming a damascene mask layer on the mask layer pattern to bury the damascene pattern; forming a damascene pattern partially overlapping the damascene pattern by etching the damascene mask layer and the mask layer pattern; connecting the damascene pattern and the damascene pattern by removing a portion of the mask layer pattern exposed by the damascene pattern; forming a damascene mask layer on the damascene mask layer to bury the damascene pattern; and forming a trench under the damascene patterns by etching the damascene mask layers and the molding layer using remaining portions of the mask layer pattern.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: March 31, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Jun Kim, Kil-Ho Lee, Ki-Joon Kim, Myoung-Su Son
  • Publication number: 20150084204
    Abstract: Provided are a semiconductor device and a method of fabricating the same. The device may include a substrate including a cell array region and a peripheral circuit region, stacks on the cell array region of the substrate, the stacks having a first height and extending along a direction, a common source structure disposed between adjacent ones of the stacks, a peripheral logic structure disposed on the peripheral circuit region of the substrate and having a second height smaller than the first height, a plurality of upper interconnection lines disposed on the peripheral logic structure and extending parallel to each other, and a interconnection structure disposed between the peripheral logic structure and the upper interconnection lines, when viewed in vertical section, and electrically connected to at least two of the upper interconnection lines.
    Type: Application
    Filed: June 24, 2014
    Publication date: March 26, 2015
    Inventors: Jang-Gn Yun, Jaesun Yun, Hoosung Cho
  • Patent number: 8987131
    Abstract: To form a through-silicon via (TSV) in a silicon substrate without using plating equipment or using sputtering equipment or small metal particles, and form an interlayer connection by stacking a plurality of such silicon substrates, a through hole of a silicon substrate is filled using molten solder itself. In detail, solid solder placed above the through hole of the silicon substrate is molten and the molten solder is guided to and filled in the internal space. A metal layer can be deposited on an internal surface of the through hole beforehand, and also an intermetallic compound (IMC) can be formed in a portion other than the metal layer.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventor: Katsuyuki Sakuma
  • Patent number: 8987079
    Abstract: A method for developing a custom device, the method including: programming a programmable device, where the programmable device includes a layer of monocrystalline first transistors and alignment marks, the first layer of monocrystalline first transistors is overlaid by interconnection layers, the interconnection layers are overlaid by a second layer of monocrystalline second transistors, where the interconnection layers include copper or aluminum, where the programming includes use of the second transistors, where the programming includes use of N type transistors and P type transistors, and where the programmable device includes at least one programmable connection; and then a step of producing a volume device according to a specific programmed design of the programmable device, where the volume device includes the at least one programmable connection replaced with a lithography defined connection, and where the volume device does not have the second layer.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: March 24, 2015
    Assignee: Monolithic 3D Inc.
    Inventor: Zvi Or-Bach
  • Patent number: 8987923
    Abstract: Among other things, a semiconductor seal ring and method for forming the same are provided. The semiconductor seal ring comprises a plurality of dielectric layers formed over a semiconductor substrate upon which a semiconductor device is formed. A plurality of conductive layers is arranged among at least some of the plurality of dielectric layers. An upper conductive layer is formed over the plurality of dielectric layers. An upper passivation layer is formed over the upper conductive layer to isolate the upper conductive layer from conductive debris resulting from a die saw process along a die saw cut line. In an example, a first columnar region comprising a first portion of the conductive layers is electrically isolated from the semiconductor device because the first columnar region is disposed relatively close to the die saw cut line and thus can be exposed to conductive debris which can cause undesired short circuits.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Chih Chou, Huei-Ru Liou, Kong-Beng Thei
  • Publication number: 20150079783
    Abstract: Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. A step is performed to selectively etch through the semiconductor active layer and the sacrificial layer in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. A step can be performed to selectively etch through the capping layer and the first portion of the semiconductor active layer to thereby expose the sacrificial layer.
    Type: Application
    Filed: July 17, 2014
    Publication date: March 19, 2015
    Inventors: Christopher Bower, Etienne Menard, Matthew Meitl, Joseph Carr
  • Publication number: 20150076683
    Abstract: An integrated circuit device package may include a flexible substrate having a first wiring, an integrated circuit device having a second wiring, a flexible insulation structure having a first opening and a second opening exposing the first wiring and the second wiring, respectively, a third wiring electrically connecting the first wiring to the second wiring, and a flexible protection member covering the third wiring. A stacked flexible integrated circuit device package may include a flexible substrate, a first flexible integrated circuit device including a first connection pad, a second flexible integrated circuit device including a second connection pad, a connection wiring electrically connecting the first and the second connection pads to an external device, and a flexible protection member disposed on the second flexible integrated circuit device.
    Type: Application
    Filed: March 18, 2013
    Publication date: March 19, 2015
    Applicant: HANA MICRON CO., LTD.
    Inventors: Jae-Sung Lim, Ju-Hyung Kim, Jin-Wook Jeong, Hyun-Joo Kim, Hyouk Lee
  • Publication number: 20150076694
    Abstract: An interposer structure including a semiconductor substrate, a plurality of shallow trenches, a plurality of deep trenches and a plurality of metal damascene structures is provided. The semiconductor substrate has a first surface and a second surface opposite to each other. The shallow trenches are formed on the first surface in both of a first area and a second area of the semiconductor substrate and correspondingly a plurality of respective openings are formed on the first surface. The deep trenches extend from at least one of the shallow trenches toward the second surface in the second area and correspondingly a plurality of respective openings are formed on the second surface. The metal damascene structures are filled in both of the shallow trenches and the deep trenches. A manufacturing method for the aforementioned interposer structure is also provided.
    Type: Application
    Filed: September 13, 2013
    Publication date: March 19, 2015
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventor: Chien-Li KUO
  • Publication number: 20150076709
    Abstract: A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.
    Type: Application
    Filed: November 8, 2014
    Publication date: March 19, 2015
    Inventors: Ryo Mori, Kazuki Fukuoka, Naozumi Morino, Yoshinori Deguchi
  • Publication number: 20150076668
    Abstract: Conductors in a 3D circuit that include horizontal lines with a plurality of vertical extensions in high aspect ratio trenches can be formed using a two-step etching procedure. The procedure can comprise providing a substrate having a plurality of spaced-apart stacks; forming a pattern of vertical pillars in a body of conductor material between stacks; and forming a pattern of horizontal lines in the body of conductor material over stacks, the horizontal lines connecting vertical pillars in the pattern of vertical pillars. The body of conductor material can be deposited over the plurality of spaced-apart stacks. A first etch process can be used to form the pattern of vertical pillars. A second etch process can be used to form the pattern of horizontal lines. The conductors can be used as word lines or as bit lines in 3D memory.
    Type: Application
    Filed: September 17, 2013
    Publication date: March 19, 2015
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: YEN-HAO SHIH, HANG-TING LUE
  • Publication number: 20150076704
    Abstract: In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a semiconductor device. A top portion of the mandrel is exposed prior to formation of the second hardmask layer. The method further includes removing the first sidewall structure to expose a first portion of a first hardmask layer. The method also includes etching the first portion of the first hardmask layer to expose a second portion of a dielectric material. The method also includes etching the second portion of the dielectric material to form a first trench. The method also includes forming a first metal structure within the first trench.
    Type: Application
    Filed: September 13, 2013
    Publication date: March 19, 2015
    Applicant: QUALCOMM Incorporatd
    Inventors: Stanley Seungchul Song, Choh Fei Yeap, Zhongze Wang, John Jianhong Zhu