Forward Correction By Block Code Patents (Class 714/752)
  • Patent number: 10348334
    Abstract: A decoder performs iterative decoding of a codeword encoded by a binary symmetry-invariant product code, such as a half product code or quarter product code. In response to the iterative decoding reaching a stopping set, the decoder determines by reference to an ambient error graph formed from the stopping set whether or not the stopping set is correctable by post-processing. If not, the decoder outputs the uncorrected codeword and signals a decoding failure. In response to determining that the stopping set is correctable by post-processing, the decoder inverts all bits of the codeword corresponding to edges of the ambient error graph, applies an additional round of iterative decoding to the codeword to obtain a corrected codeword, and outputs the corrected codeword. Post-processing in this manner substantially lowers an error floor associated with the binary symmetry-invariant product code.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Tobias Blaettler, Thomas Mittelholzer, Nikolaos Papandreou, Thomas Parnell, Charalampos Pozidis
  • Patent number: 10340950
    Abstract: Certain aspects of the present disclosure generally relate to techniques for encoding, generally including obtaining a payload, determining a set of internal nodes to distribute one or more non-payload bits to based, at least in part, on a target maximum likelihood (ML) search space size for internal nodes in a polar decoding tree, a search space size of each of the internal nodes, and an available number of the non-payload bits left to distribute, forming an information stream by interleaving the non-payload bits with bits of the payload by, for each internal node in the set of internal nodes, assigning one or more non-payload bits to one or more leaf nodes in a subtree rooted at that internal node in the set of internal nodes, and generating a codeword by encoding the information stream using a Polar code.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: July 2, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Aaron Klein, Abhinav Sridhar
  • Patent number: 10341051
    Abstract: A transmitter and receiver of a broadcasting signal and a method of processing the broadcasting signal are provided. The transmitter includes: a segmenter configured to segment an L1 signaling of a frame into a plurality of segmented L1 signalings such that each of the segmented L1 signalings has bits a number of which is equal to or smaller than a predetermined number; and an encoder configured to perform a Bose, Chaudhuri, Hocquenghem (BCH) and a low density parity check (LDPC) encoding, or the LDPC encoding without the BCH encoding, with respect to the segmented L1 signalings.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: July 2, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-sil Jeong, Se-ho Myung, Kyung-joong Kim
  • Patent number: 10341053
    Abstract: Embodiments described herein provide a system for dynamically selecting a pre-processing scheme for an LDPC decoder. The system includes a receiver configured to detect transmission of a first data packet and receive a first set of data bits corresponding to a first portion of the first data packet. The system further includes a histogram generator configured to calculate log-likelihood ratios for each data bit from the first set of data bits, and generate a histogram based on the calculated log-likelihood ratios. The receiver is configured to continue receiving a second set of data bits corresponding to a second portion of the first data packet. The system further includes a selector configured to activate or inactivate a log-likelihood ratio pre-processing scheme on the received second set of data bits based on characteristics of the histogram.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: July 2, 2019
    Assignee: Marvell World Trade Ltd.
    Inventors: Vijay Ahirwar, Sri Varsha Rottela
  • Patent number: 10333618
    Abstract: Aspects of the present disclosure describe systems, methods, and structures for physical layer security using hybrid free-space optical and terahertz transmission technologies that advantageously overcome atmospheric characteristics that infirmed the prior art.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: June 25, 2019
    Assignee: NEC Corporation
    Inventors: Ivan Djordjevic, Shaoliang Zhang, Ting Wang
  • Patent number: 10333553
    Abstract: A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: June 25, 2019
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim
  • Patent number: 10333560
    Abstract: A node (110, 115) receives (804) transmissions associated with a given set of information bits, wherein each of the transmissions use a different polar code and share one or more information bits of the given set of information bits. The node determines (808), at each of a plurality of polar decoders (505, 605) of the node, soft information for each information bit included in an associated one of the transmissions, wherein each of the plurality of polar decoders is associated with a different transmission of the transmissions. The node provides (812), from each polar decoder of the plurality to one or more other polar decoders of the plurality, the determined soft information for any information bits shared by their respective associated transmissions, and uses (816) the provided soft information in an iterative decoding process to decode one or more of the received transmissions.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: June 25, 2019
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Dennis Hui, Mattias Andersson, Yufei Blankenship, Ivana Maric
  • Patent number: 10326472
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: June 18, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 10326554
    Abstract: A decoding device includes: a BP decoder that performs BP decoding on an input signal: a maximum likelihood decoder that performs maximum likelihood decoding on a signal subjected to the BP decoding; and a selector that selects one of the input signal, the signal subjected to the BP decoding, and a signal subjected to the maximum likelihood decoding. In a configuration of the decoding device, when a decoder is appropriately operated according to quality of data, a calculation scale can be reduced, and power consumption can be decreased.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: June 18, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Yutaka Murakami, Tomohiro Kimura, Mikihiro Ouchi
  • Patent number: 10324623
    Abstract: A method includes encoding a data segment of a data object into a set of encoded data slices. The set of encoded data slices includes “n” number of encoded data slices. The method further includes generating a set of slice names for the set of encoded data slices. The method further includes selecting “m” encoded data slices of the set of encoded data slices to output for storage in DSN memory. The method further includes selecting “m” storage units of “p” storage units of the DSN memory for storing the “m” encoded data slices. The method further includes mapping “m” slice names of the “m” encoded data slices to DSN addresses of the “m” storage units to create mapped slice names. The method further includes outputting, in accordance with the mapped slice names, the “m” encoded data slices to the “m” storage units for storage therein.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jason K. Resch, Greg Dhuse
  • Patent number: 10327040
    Abstract: Techniques for low latency streaming, for example in a broadcasting environment, are described herein. In some examples, one or more individual renditions may be encoded into multiple rendition versions associated with different respective latencies. Also, in some examples, one or more individual renditions may be encoded into multiple rendition versions having different respective amounts of forward error correction (FEC), for example by an edge node of a video streaming service. Also, in some examples, video may be broadcast using a protocol that does not require retransmission of lost packets, such as Web Real-Time Communication (WebRTC), which is commonly used for point-to-point transmissions. Also, in some examples, one or more servers may receive quality of service feedback information from each player to which video content is transmitted. The one or more servers may use this feedback information to select and switch between appropriate renditions and rendition versions for each player.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: June 18, 2019
    Assignee: Twitch Interactive, Inc.
    Inventors: Yueshi Shen, Martin Hess, Shawn Hsu, Eran Ambar, Abhinav Kapoor, Jorge Arturo Villatoro, Spencer Nelson, Jeffrey Garneau, Cyrus Hall, Jyotindra Vasudeo, Andrew Francis, Yuechuan Li, Chih-Chiang Lu
  • Patent number: 10320553
    Abstract: Methods, systems, and devices for wireless communication are described. A base station may identify a transport block for transmission that includes an information component and an error detection code. The base station may transmit a first encoded message during a first transmission time. The first encoded message may be obtained by encoding the transport block cyclically shifted a first bit length. The base station may transmit a second encoded message during a second transmission time. The second encoded message may be obtained by encoding the transport block cyclically shifted a second bit length. The relative time distance between the first and second transmission times may convey an indication of the difference between the first bit length and the second bit length.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: June 11, 2019
    Assignee: QUALCOMM Incoporated
    Inventors: Bilal Sadiq, Juergen Cezanne, Tao Luo
  • Patent number: 10313089
    Abstract: Embodiments of the present invention provide a method, an apparatus, and a system for transmitting data in the Ethernet, and relate to the field of Ethernet communications, so as to reduce the complexity of data processing while achieving transmission of high-rate data. The method includes: receiving to-be-transmitted data; determining a first integral number according to a data amount of the received to-be-transmitted data and a transmission bandwidth of an electrophysical sub-channel; distributing the to-be-transmitted data to a first integral number of electrophysical sub-channels; performing, by the first integral number of electrophysical sub-channels, coding and scrambling processing on the to-be-transmitted data; and sending after processing, by a second integral number of photophysical sub-channels, data from the first integral number of electrophysical sub-channels.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: June 4, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Wei Su
  • Patent number: 10298268
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: May 21, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 10296215
    Abstract: In one embodiment, a method includes determining a data record partition size based on resources used for transferring data from a higher storage tier to one or more lower storage tiers. The method also includes determining which data records stored to the higher storage tier are suitable for export to the one or more lower storage tiers, determining a distribution mapping of the first memory, the distribution mapping indicating a relative distribution of storage locations for all of the data records that are stored to the higher storage tier, identifying all sets of contiguously stored data records on the higher storage tier that are suitable for export and greater in size than the data record partition size, logically sorting, in a descending order of size, the sets of contiguously stored data records, and sending a list of logically sorted sets of contiguously stored data records to an exporter.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Umesh Deshpande, Paul H. Muench, Mohit Saxena
  • Patent number: 10299136
    Abstract: A transmission apparatus includes: a data-symbol generation unit that generates data symbols for one block in each block; a storage and processing unit that stores therein a data symbol at a first position, among the data symbols for one block, as a copied symbol; a symbol insertion unit that generates a block symbol by putting the data symbols and the copied symbol such that the copied symbol stored in the storage and processing unit are inserted at a second position of the data symbols for one block; a time/frequency conversion unit that converts the block signal into a frequency domain signal; an interpolation unit that performs interpolation processing on the frequency domain symbol; and a CP insertion unit that generates the block signal by inserting a Cyclic Prefix into a signal on which the interpolation processing has been performed.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: May 21, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventor: Fumihiro Hasegawa
  • Patent number: 10291375
    Abstract: A network node, a User Equipment, UE and methods therein, for handling a message transmitted over a radio link. The network node generates a first set of identity check bits for a first part of the message, based on the message and a first check identity, and further generates a second set of identity check bits valid for a second part of the message, based on the message, the first set of identity check bits and a second check identity. The message is then transmitted over the radio link with the first and second sets of identity check bits attached. The UE performs a first verification check using the second set of identity check bits and the second check identity, and performs a second verification check using the first set of identity check bits and the first check identity. The UE then handles the second message part based on the first verification check and the first message part based on the second verification check.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: May 14, 2019
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventors: Jonas Fröberg Olsson, Erik Eriksson, Pål Frenger, Martin Hessler
  • Patent number: 10284234
    Abstract: Although a distributed storage device can recover data from multiple failures this process produces excessive inter-zone network traffic when a chunk with user data is deleted. This disclosure employs an un-encoding erasure coding and partial coding chunks to facilitate data deletes while reducing inter-zone network traffic. Therefore a data chunk representative of partitioned disk space associated with a first zone of a data store can be determined to be marked for deletion. Consequently, the data chunk can be copied, resulting in a copied data chunk, to a second zone of the data store associated with a coding chunk comprising the data chunk. Based on the copied data chunk and the coding chunk, a partial coding chunk can be generated via un-encoding, wherein the partial coding chunk is a subset of the coding chunk.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: May 7, 2019
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mikhail Danilov, Alexander Rakulenko
  • Patent number: 10277251
    Abstract: A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to constitute Low Density Parity Check (LDPC) information bits including the outer-encoded bits and zero bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the LDPC information bits are divided into a plurality of bit groups, and wherein the zero padder pads zero bits to at least some of the plurality of bit groups, each of which is formed of a same number of bits, to constitute the LDPC information bits based on a predetermined shortening pattern which provides that the some of the plurality of bit groups are not sequentially disposed in the LDPC information bits.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: April 30, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-Joong Kim, Se-ho Myung, Hong-sil Jeong
  • Patent number: 10278032
    Abstract: A broadcast signal transmitter includes an encoder configured to perform outer encoding and inner encoding on Physical Layer Pipe (PLP) data, a time interleaver configured to interleave the PLP data on which the outer encoding and the inner encoding are performed, a framer configured to generate a signal frame comprising the interleaved PLP data, the signal frame comprising a preamble and at least one subframe, a frequency interleave configured to interleave data comprised in the generated signal frame, a pilot inserter configured to insert Scattered Pilots (SPs) into the signal frame comprising the interleaved data, and a modulator configured to modulate the SPs inserted signal frame by Orthogonal Frequency Division Multiplexing (OFDM) modulation scheme.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: April 30, 2019
    Assignee: LG ELECTRONICS INC.
    Inventors: Jaehyung Kim, Woosuk Ko, Chulkyu Mun, Sungryong Hong
  • Patent number: 10270467
    Abstract: Provided is a signal interleaving method which includes: interleaving parity bits by encoding input bits based on a low density parity check (LDPC) code according to a code rate of 6/15 and a code length of 64800; splitting a codeword comprising the input bits and the interleaved parity bits into a plurality of bit groups; interleaving the plurality of bit groups according to a specific permutation order to provide an interleaved codeword; de-multiplexing bits of the interleaved codeword to generate data cells; mapping the data cells onto constellation points for 1024-quadrature amplitude modulation (QAM); and transmitting a signal based on the constellation points.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: April 23, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-sil Jeong, Kyung-Joong Kim, Se-ho Myung
  • Patent number: 10256846
    Abstract: A method of processing a signal by non-uniform quantization of log likelihood ratios is disclosed. A method comprising the steps of: receiving a plurality of bits; calculating a log likelihood ratio, known as a LLR, for each bit; providing a LLR value for each bit based on the calculated LLR; quantizing the LLR values into a plurality of quantization bins, each quantization bin having: a width representative of one or more LLR values; and an index value having a bit length; and associating each bit with the index value that corresponds to its LLR value, wherein the width of each quantization bin is non-uniform. This compresses the LLR values in a more efficient manner, requiring lower memory usage and/or lower bandwidth. A chip for a receiver and a communication system comprising one or more receivers are also disclosed.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: April 9, 2019
    Assignee: NXP B.V.
    Inventors: Semih Serbetli, Marinus van Splunter
  • Patent number: 10243585
    Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: March 26, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-sil Jeong, Se-ho Myung, Kyung-joong Kim
  • Patent number: 10243730
    Abstract: A method for encrypting data in a near field communication system is provided. The method includes generating encrypted data based on first data input in a current state and second data input in a state immediately preceding the current state, and encoding the encrypted data through a predetermined error correcting code.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: March 26, 2019
    Assignees: Samsung Electronics Co., Ltd., Korea University Research and Business Foundation
    Inventors: Jun Heo, Kyoung-Hoon Kwon
  • Patent number: 10236912
    Abstract: Provided is an LDPC (Low Density Parity Check) code for terrestrial cloud broadcast. A method of encoding input information based on an LDPC (Low Density Parity Check) includes receiving information and encoding the input information with an LDPC codeword using a parity check matrix, wherein the parity check matrix may have a structure obtained by combining a first parity check matrix for an LDPC code having a higher code rate than a reference value with a second parity check matrix for an LDPC code having a lower code rate than the reference value.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: March 19, 2019
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung Ik Park, Heung Mook Kim, Nam Ho Hur
  • Patent number: 10229742
    Abstract: A flash memory controller is configured to hold a read pattern defining an order of selection of read options specifying a parameter value for a read from the flash memory chip. The flash memory controller is configured to execute error correction on data read from the flash memory chip in accordance with the read command. The flash memory controller is configured to designate a next read option specified in the read pattern to read the data from the flash memory chip in a case where all errors in the read data are not corrected by the error correction.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: March 12, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Yohei Hazama, Junji Ogawa, Kenta Ninose
  • Patent number: 10230698
    Abstract: Examples disclose a system comprising an integrated circuit to determine whether a data packet should be processed by a shared security engine associated with a secure link. Additionally, the examples disclose a first media access control (MAC), associated with the shared security engine, to receive the data packet for transmission on the secure link based on the determination the data packet should be processed by the shared security engine.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: March 12, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Shaun Wakumoto, Craig Joseph Mills, Parvez Syed Mohamed
  • Patent number: 10230404
    Abstract: A system and method for providing error control coding for backhaul applications are disclosed. Data is first encoded using Reed-Solomon (RS) coding. The output RS blocks are then turbo coded. The size of the output RS blocks is selected to match the input of the turbo encoder. The bits from the RS blocks may be interleaved to create the input turbo blocks. Cyclic Redundancy Check (CRC) parity bits may be added to the data prior to RS coding.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: March 12, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mohamed Farouk Mansour, June Chul Roh, Srinath Hosur
  • Patent number: 10224962
    Abstract: A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to constitute Low Density Parity Check (LDPC) information bits including the outer-encoded bits and zero bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the LDPC information bits are divided into a plurality of bit groups, and wherein the zero padder pads zero bits to at least some of the plurality of bit groups, each of which is formed of a same number of bits, to constitute the LDPC information bits based on a predetermined shortening pattern which provides that the some of the plurality of bit groups are not sequentially disposed in the LDPC information bits.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: March 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-Joong Kim, Se-ho Myung, Hong-sil Jeong
  • Patent number: 10218386
    Abstract: A Reed-Solomon encoder that supports multiple code words is provided. The encoder circuit may include partial syndrome calculation circuitry, three matrix multiplication circuits, and two adder circuits. The partial syndrome calculation circuitry may receive a message and generate partial syndromes. The first matrix multiplication circuit may multiply a lower portion of the partial syndromes by a small Lagrange matrix to produce a small parity symbol vector. The second matrix multiplication circuit may multiply the small parity symbol vector by a Vandermonde matrix to produce a product vector. The first adder circuit may add the product vector to an upper portion of the partial syndromes to produce a sum vector. The third matrix multiplication circuit may multiply the sum vector by a large Lagrange matrix to produce a large product vector. The large product vector may be selectively combined with the small parity symbol vector to generate final parity check symbols.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: February 26, 2019
    Assignee: Intel Corporation
    Inventors: Martin Langhammer, Simon Finn, Sami Mumtaz
  • Patent number: 10216573
    Abstract: In various embodiments, a method of correcting and/or detecting an error in a memory device is provided. The method may include, in a first operations mode, applying a first code to detect and/or correct an error, and in a second operations mode after an inactive mode and before entering the first operations mode, applying a second code for correcting and/or detecting an error, wherein the first code and the second code have different code words.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: February 26, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kern, Michael Goessel, Karl Hofmann
  • Patent number: 10216577
    Abstract: The present invention introduces a specific form of parity protection chunk (PPC) that allows for distributed creation of coordinated PPCs that can reliably provide protection against the concurrent loss of two or more storage servers of devices. Coordinated PPCs can protect against the concurrent loss of multiple lost chunks by ensuring that the PPCSs protecting any specific chunk have at most a single overlapping failure domain. This is done without requiring full centralized control over the assignment of protected chunks to specific PPCs. The PPCs are created as part of the put transaction for a chunk. The chunk itself is stored as a whole replica, and the PPCs provide parity protection for the chunk.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: February 26, 2019
    Assignee: Nexenta Systems, Inc.
    Inventors: Caitlin Bestler, Alexander Aizman
  • Patent number: 10203934
    Abstract: Technologies for executing a serial data processing algorithm on a single variable-length data buffer includes padding data segments of the buffer, streaming the data segments into a data register and executing the serial data processing algorithm on each of the segments in parallel.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: Sean M. Gulley, Wajdi K. Feghali, Vinodh Gopal, James D. Guilford, Gilbert Wolrich, Kirk S. Yap
  • Patent number: 10205468
    Abstract: Provided is a method for decoding a non-binary (NB) low density parity check (LDPC) code at a user equipment (UE) that implements at least one variable nodes that receive a received signal of a wireless channel and deliver an input message to a check node and the check node that checks the input message and outputs an output message. The method includes receiving at least one input messages, generating a temporary vector by using the at least one input messages, searching for an element having a dominant value by checking the temporary vector, generating a configuration set, which is a check target, by using the element having the dominant value, and generating the output message by performing comparison with respect to the generated configuration set.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: February 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Ki Ahn, Kyeong-Cheol Yang, Sang-Min Kim, Woo-Myoung Park, Min Sagong, Chi-Woo Lim, Sung-Nam Hong
  • Patent number: 10200152
    Abstract: The present disclosure provides a method and a device for transmitting data using a LDPC code. The method for transmitting data using a LDPC code includes: determining a check code length according to a current LDPC code rate; informing a receiving end about the current LDPC code rate and the check code length, adding a check code with the check code length to data to be sent, and implementing a LDPC encoding using the current LDPC code rate, so as to obtain LDPC code data; and sending the LDPC code data to a receiving end. The method and the device of the present disclosure can improve spectrum effectiveness of transmitting data using LDPC code.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: February 5, 2019
    Assignee: BEIJING SPREADTRUM HI-TECH COMMUNICATIONS TECHNOLOGY CO., LTD.
    Inventors: Zhikun Xu, Su Huang, Zhengang Pan
  • Patent number: 10198248
    Abstract: Technologies for executing a serial data processing algorithm on a single variable length data buffer includes streaming segments of the buffer into a data register, executing the algorithm on each of the segments in parallel, and combining the results of executing the algorithm on each of the segments to form the output of the serial data processing algorithm.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: February 5, 2019
    Assignee: Intel Corporation
    Inventors: Sean M. Gulley, Wajdi K. Feghali, Vinodh Gopal, James D. Guilford, Gilbert M. Wolrich, Kirk S. Yap
  • Patent number: 10191804
    Abstract: The present disclosure includes apparatuses and methods related to updating reliability data. A number of methods can include receiving, at a variable node, either a first reliability data value with a first hard data value or a second reliability data value with a second hard data value, sending the first hard data value or the second hard data value to each check node coupled to the variable node according to a parity check code, and updating the reliability data based on input from less than all of the check nodes.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: January 29, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Saeed Sharifi Tehrani, Nicholas J. Richardson
  • Patent number: 10193657
    Abstract: A system and method for filtering code blocks to maintain high throughput thru a Forward Error Correcting (FEC) decoder is disclosed. The method includes: monitoring a Signal-to-Noise Ratio (SNR) for an incoming link; selecting a rank table including a rank, Modulation and Coding Rate (MODCOD), and a minimum SNR; determining a threshold MODCOD range from the rank table based on the SNR; demodulating an incoming frame; identifying, in the incoming frame, the code blocks and an associated MODCOD for each of the code blocks; selecting a code block from the code blocks when the respective MODCOD for the code block is in the rank table and within the threshold MODCOD range; and decoding the selected code block with the associated MODCOD.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: January 29, 2019
    Assignee: Hughes Network Systems, LLC
    Inventors: Bala Subramaniam, Alexei Duhovich
  • Patent number: 10187086
    Abstract: Techniques for reducing the latency for decoding product codewords with minimal hardware architecture changes are described. In an example, multiple decoding procedures are available a system. The system maintains decoding states. Each decoding state corresponds to a constituent codeword of a product codeword and to a decoding procedure. For instance, a BCH decoding state indicates whether the decoding of the respective BCH constituent codeword has previously failed. The decoding of the product codeword depends on the various decoding state. For instance, in a BCH decoding iteration, if a BCH decoding state of a constitutent codeword is set to “failed,” the BCH decoding of that codeword is skipped.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: January 22, 2019
    Assignee: SK Hynix Inc.
    Inventors: Aman Bhatia, Naveen Kumar, Yi-Min Lin, Fan Zhang
  • Patent number: 10177790
    Abstract: A bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: January 8, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 10177787
    Abstract: An apparatus having an interface and a control circuit is disclosed. The interface may be configured to process a plurality of read/write operations to/from a memory. The control circuit may be configured to (i) access information that characterizes a plurality of trapping sets of a low-density parity check code in response to receiving data, (ii) encode the data using the low-density parity check code to generate a codeword and (iii) write the codeword in the memory. The generation of the codeword may include at least one of a shortening and a puncturing of a plurality of bits in the codeword. The plurality of bits may be selected based on the information that characterizes the plurality of trapping sets. The bits selected generally reduce a probability that an error correction of the codeword after the codeword is read from the memory fails due to the plurality of trapping sets.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: January 8, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Ludovic Danjean, Sundararajan Sankaranarayanan, Ivana Djurdjevic, AbdelHakim Alhussien, Erich F. Haratsch
  • Patent number: 10169424
    Abstract: The apparatus, systems and methods dynamically provide the reliability of multimedia documents by applying a series of intrinsic criteria and extrinsic criteria by pre-calculating a reliability score for at least a set of multimedia documents of at least one pre-selected source of multimedia documents, and by providing, in response to a request, the multimedia documents from the pre-selected sources associated with the score and the multimedia documents from the other sources associated with a score conditionally calculated.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: January 1, 2019
    Inventor: Lucas J. Myslinski
  • Patent number: 10169147
    Abstract: A method includes a first computing device generating a set of encryption keys and encrypting a data matrix based on the set of encryption keys to produce an encrypted data matrix. The method further includes the first computing device sending the encrypted data matrix to a second computing device. The method further includes the second computing device dispersed storage error encoding the data matrix to produce a set of encrypted encoded data slices. The method further includes the second computing device sending the set of encrypted encoded data slices to a set of storage units of the DSN for storage therein.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Greg R. Dhuse, Jason K. Resch, Trevor J. Vossberg
  • Patent number: 10164733
    Abstract: Method and apparatus for receiving data at a physical coding sublayer (PCS) transmit structure from a media access control (MAC) sublayer. The method includes performing a first forward error-correcting (FEC) sub-function on the data in the PCS transmit structure. The method further includes transmitting the data on one or more physical medium attachment (PMA) lanes to a PCS receive structure. The method also includes performing a second FEC sub-function on the data in the PCS receive structure.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: December 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Claude Basso, Cheng Wei Song, Fabrice Jean Verplanken
  • Patent number: 10164734
    Abstract: Method and apparatus for receiving data at a physical coding sublayer (PCS) transmit structure from a media access control (MAC) sublayer. The method includes performing a first forward error-correcting (FEC) sub-function on the data in the PCS transmit structure. The method further includes transmitting the data on one or more physical medium attachment (PMA) lanes to a PCS receive structure. The method also includes performing a second FEC sub-function on the data in the PCS receive structure.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: December 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Claude Basso, Cheng Wei Song, Fabrice Jean Verplanken
  • Patent number: 10153787
    Abstract: An apparatus and a method. The apparatus includes a receiver to receive a polar codeword of length mj; a processor configured to determine a decoding node tree structure with mj leaf nodes for the received codeword, and receive i indicating a level at which parallelism of order m is applied to the decoding node tree structure, wherein i indicates levels of the decoding node tree structure, and wherein the mj leaf nodes are at level j; and m successive cancellation list decoders (SCLDs) applied to each child node of each node in the decoding node tree structure at level i?1, wherein each of the m SCLDs executes in parallel to determine log likelihood ratios (LLRs) for a codeword of length mj-i, and wherein each of the m SCLDs uses LLRs of an associated parent node without using a hard decision or a soft reliability estimate of any other node of the other m SCLDs.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: December 11, 2018
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Mostafa El-Khamy, Hsien-Ping Lin, Jungwon Lee
  • Patent number: 10152601
    Abstract: A method begins by storage units of a dispersed storage network (DSN) receiving a retrieval request for a data object, where each storage unit stores a unique group of encoded data slices of the data object and a local set of encoded recovery data slices. The method continues with some storage units sending the unique group of encoded data slices to a requesting computing device and with one storage unit sending an encoded recovery data slice to the requesting computing device. The method continues with the requesting computing device identifying an errant unique group encoded data slice, correcting the errant encoded data slice based on received data slices to produce an updated unique group of encoded data slices, and dispersed storage error decoding the updated unique group of encoded data slices and the unique groups of encoded data slices from other storage units to recover the data object.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: December 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ilya Volvovski, Bruno Hennig Cabral, Manish Motwani, Thomas Darrel Cocagne, Timothy W. Markison, Gary W. Grube, Wesley Leggette, Jason K. Resch, Michael Colin Storm, Greg Dhuse, Yogesh Ramesh Vedpathak, Ravi Khadiwala
  • Patent number: 10148326
    Abstract: Methods and apparatus for single and multi-user signal extensions or padding are provided. In various aspects, a number of symbols required to transmit a plurality of data bits to each of a plurality of wireless communication devices and a fraction of useful bits in a final symbol of each of the plurality of data bits is determined. A signaling extension length may also be determined based at least in part on the fraction of useful bits and a modulation and coding scheme (MCS) of each of the plurality of wireless communication devices. A plurality of data packets for each of the plurality of wireless communication devices are generated, with each data packet comprising the corresponding data bits and the signaling extension after the final symbol of each of the plurality of data packets.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: December 4, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Arjun Bharadwaj, Bin Tian
  • Patent number: 10141952
    Abstract: A memory system includes a memory device; and a controller suitable for encoding a message, storing the encoded message in the memory device and decoding the encoded message, wherein the controller is suitable for generating a message matrix including predetermined row codes and predetermined column codes symmetrical to the predetermined row codes, with the message or the encoded message using a block-wise concatenated Bose-Chadhuri-Hocquenghem (BCH) code with a symmetrical structure.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: November 27, 2018
    Assignees: SK Hynix Inc., Korea Advanced Institute of Science and Technology
    Inventors: Jeong-Seok Ha, Su-Hwang Jeong, Dae-Sung Kim
  • Patent number: 10141951
    Abstract: A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to constitute Low Density Parity Check (LDPC) information bits including the outer-encoded bits and zero bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the LDPC information bits are divided into a plurality of bit groups, and wherein the zero padder pads zero bits to at least some of the plurality of bit groups, each of which is formed of a same number of bits, to constitute the LDPC information bits based on a predetermined shortening pattern which provides that the some of the plurality of bit groups are not sequentially disposed in the LDPC information bits.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: November 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-Joong Kim, Se-ho Myung, Hong-sil Jeong