Abstract: A first channel for carrying Layer 2 messages carries data that will not be retransmitted and for which decoding-related information need not be retained by the receiving node in the event of an unsuccessful decoding of the data, while a second channel carries data that will be retransmitted in the event that a negative acknowledgement is received by the transmitting node. In an example method, first and second subsets of Layer 2 messages are received on first and second physical data channels, respectively. Decoding-related information for unsuccessfully decoded messages in the first subset is retained for use with subsequent retransmissions, while decoding-related information for unsuccessfully decoded messages in the second subset is discarded without waiting for retransmissions. Acknowledgements or negative acknowledgements are sent for messages in the first subset, but may or may not be sent for messages in the second subset, in various embodiments.

Abstract: Disclosed herein are memory devices, systems, and methods of encoding and decoding data. In one aspect, an encoded data chunk is received and segmented into data segments with similar features. Each segment can be decoded based on its features. Data can also be rearranged and partitioned so as to minimize an entropy score that is based on the size and entropy of the data partitions. The approach is capable of enhancing performance, reducing decoding latency, and reducing power consumption.

Abstract: There are provided a communication apparatus, method and system, and the communication apparatus, comprises: a transmitter configured to transmit a first data to a terminal and retransmit a second data to the terminal under a retransmission condition after transmitting the first data; and a circuitry configured to control a retransmission scheme for the retransmission of the second data based on at least one of a systematic bit degree and a preempted resource degree for the transmission of the first data.

Abstract: An error correction device includes a bit reliability value determination circuit configured to determine bit reliability values corresponding to hard decision bits, based on soft decision bit sets corresponding to the hard decision bits; and a decoder including a variable node configured to receive and store the hard decision bits and the bit reliability values, and perform a decoding operation for the hard decision bits by restoring reliability values from the bit reliability values. The reliability values correspond to elements except a decision symbol configured by the hard decision bits, in a Galois field (GF) defined in the variable node. All necessary reliability values are not transmitted to each variable node, instead, compressed reliability values are transmitted to the variable node. The variable node receives and retains the compressed reliability values, restores necessary reliability values, and uses them in a decoding operation.

Abstract: A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process.

Abstract: A low-density parity-check code scaling method is disclosed. The method includes following steps: obtaining the original low-density parity-check matrix; forming the permutation matrices with the random row shift or the random column shift to the identity matrix; replacing the component codes by the permutation matrices and the all-zero matrix to form the extended low-density parity-check matrix; adjusting the code length and the code rate to form the global coupled low-density parity-check matrix; and outputting the global coupled low-density parity-check code.

Abstract: A receiver is configured for receiving a signal including a training field and a payload over a communication channel. The receiver includes a channel estimator, a scaling factor calculator, a metric calculator and a decoder. The channel estimator is configured to estimate values of a parameter of the communication channel based on the training field of the received signal. The scaling factor calculator is configured to calculate a scaling factor based on the values of the parameter of the communication channel. The metric calculator is configured to calculate soft decoding metrics for use in decoding data carried by the payload of the received signal, including scaling the soft decoding metrics by the scaling factor. The decoder is configured to decode the data carried by the payload of the received signal using the scaled soft decoding metrics.

Abstract: The present disclosure relates to methods and apparatuses for generating a low-density parity-check code basis matrix. One example method includes obtaining a low-density parity-check code mother matrix, and generating a 1st matrix to a qth matrix one by one, where q is a preset positive integer. A Pth matrix in the 1st matrix to the qth matrix is generated in the following manner: selecting a to-be-replaced matrix element in a (P?1)th matrix, where the to-be-replaced matrix element is a matrix element having a value that is not ?1 in the (P?1)th matrix, determining a Pth shift factor corresponding to the to-be-replaced matrix element, and replacing the to-be-replaced matrix element in the (P?1)th matrix with the Pth shift factor to obtain the Pth matrix whose cycle length property is better than a cycle length property of the (P?1)th matrix.

Abstract: The present disclosure relates to decoding methods and devices. One example method includes receiving N LLRs corresponding to a to-be-decoded signal, where N is a code length, classifying K decoded bits into reliable bits and unreliable bits based on at least one of a prior LLR or a posterior LLR, generating M decoding paths based on the N LLRs and a preset rule, and selecting each stage of target decoding path based on PM values of the M decoding paths to obtain a decoding result of each stage of decoded bit.

Abstract: Overhead associated with data re-protection during scaling out and/or scaling up of a distributed cloud storage system can be reduced. A coding matrix that is to be utilized for erasure coding in a potential final configuration of the distributed cloud storage can be determined. During initial data protection, a portion of the coding matrix can be utilized to determine coding chunks for protecting data chunks stored within different geographical zones of the distributed cloud storage system. When additional zones are added to the distributed cloud storage system, a larger portion of the coding matrix can be utilized to erasure code the new configuration and accordingly, the existing coding chunks are considered as partially complete. Further, the partially complete coding chunks can be combined with data chunks stored within the newly added zones and coefficients of the larger portion of the coding matrix to generate complete coding chunks.

Abstract: A semiconductor memory system includes: a semiconductor memory device for storing a code word; a decoder for decoding stored the code word based on a parity check matrix formed of sub-matrices to generate decoded data; and a channel for coupling the semiconductor memory device to the decoder and providing the decoder with the stored code word, wherein the decoder includes: a variable node selecting device for sequentially selecting sub-matrices sharing the same layer of the parity check matrix and sequentially selecting variable nodes respectively corresponding to columns forming the selected sub-matrices; a variable node updating device for updating the selected variable nodes based on a channel message and check node messages provided to the selected variable nodes; and a check node updating device for updating the check nodes based on variable node messages provided to the check nodes coupled to the selected variable nodes.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Abstract: Methods and devices are disclosed for encoding source words and decoding codewords with LDPC matrices. The Methods and devices use a LDPC matrix Hn of lifting factor Z. The LDPC matrix Hn comprises a plurality of submatrices, each submatrix having a size of Z×Z, and at least one submatrix has m1 diagonals of “1” m1 is an integer>=2.

Abstract: An error correction device includes a low density parity check (LDPC) decoder and an adaptive decoding controller. The LDPC decoder iteratively performs LDPC decoding on data by using a decoding parameter. The adaptive decoding controller calculates an error rate depending on a result of the LDPC decoding and adjusts the decoding parameter depending on the error rate.

Abstract: Methods and devices are disclosed for encoding source words and decoding codewords with LDPC matrices. Example embodiments of a modulation and coding scheme (MCS) for generating a rate 1/2 length 1344 LDPC codeword are described. The method includes segmenting a stream of data bits into 336 bit size segments, adding 336 padding bits to each 336 bit size segment to generate corresponding 672 bit size source words, applying a 1/2 rate low density parity check (LDPC) coding to each 672 bit size source word to generate a corresponding 1344 bit size codeword that includes 672 parity bits; and for each codeword, substituting the 336 padding bits with 336 bits derived from the data bits included in the codeword, to provide a 1344 bit size codeword that includes a concatenation of the 336 data bits, the 336 bits derived from the data bits, and 672 parity bits.

Abstract: A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to constitute Low Density Parity Check (LDPC) information bits including the outer-encoded bits and zero bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the LDPC information bits are divided into a plurality of bit groups, and wherein the zero padder pads zero bits to at least some of the plurality of bit groups, each of which is formed of a same number of bits, to constitute the LDPC information bits based on a predetermined shortening pattern which provides that the some of the plurality of bit groups are not sequentially disposed in the LDPC information bits.

Abstract: Techniques are described for wireless communication. One method includes segmenting a payload into a plurality of code blocks; generating, for each code block, a cyclic redundancy check (CRC); encoding each code block and associated CRC in one or more codewords of a plurality of codewords; and transmitting the codewords. The encoding is based at least in part on a low density parity check code (LDPCC) encoding type. Another method includes receiving a plurality of codewords associated with a payload encoded using a LDPCC encoding type; decoding a set of the codewords associated with the first payload and a CRC; and transmitting one of an acknowledgement (ACK) or a non-acknowledgement (NAK) for the set of the codewords.

Abstract: Methods and apparatus deduplicate and erasure code a message in a data storage system. One example apparatus includes a first chunking circuit that generates a set of data chunks from a message, an outer precoding circuit that generates a set of precoded data chunks and a set of parity symbols from the set of data chunks, a second chunking circuit that generates a set of chunked parity symbols from the set of parity symbols, a deduplication circuit that generates a set of deduplicated data chunks by deduplicating the set of precoded chunks or the set of chunked parity symbols, an unequal error protection (UEP) circuit that generates an encoded message from the set of deduplicated data chunks, and a storage circuit that controls the data storage system to store the set of deduplicated data chunks, the set of parity symbols, or the encoded message.

Abstract: In an example, an audio signal may be routed to an audio device based on an indication of audio device historical usage, a measure of audio quality of the audio device, or a combination thereof.

Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method.

Abstract: Apparatus and methods are disclosed, including using a memory controller to monitor at least one parameter related to power level of a host processor of a host device, and dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device.

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 10/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

Abstract: A receiver is provided. The receiver includes: a first decoder configured to decode a superposition-coded signal by using a parity check matrix to generate Low Density Parity Check (LDPC) information word bits and first parity bits corresponding to a first layer signal; an encoder configured to encode the LDPC information word bits and the first parity bits to generate second parity bits, or encode the LDPC information word bits to generate the first parity bits and the second parity bits, by using the parity check matrix; and a second decoder configured to decode a signal which is generated by removing the first layer signal, corresponding to the LDPC information word bits, the first parity bits, and the second parity bits, from the superposition-coded signal, to reconstruct bits transmitted through the second layer signal.

Abstract: Provided herein may be an error correction circuit. An error correction circuit for performing error correction decoding based on an iterative decoding scheme using a NB-LDPC code may include a symbol configuration circuit for configuring an initial symbol to be assigned as a variable node value to a variable node, a reliability value initialization circuit for initializing first reliability values of candidate symbols corresponding to the variable node based on the initial symbol assigned to the variable node, and a symbol correction circuit updating the first reliability values of the candidate symbols based on communications received from a check node coupled to the variable node, the candidate symbols having updated first reliability values, respectively, and adjusting the variable node value to one of the candidate symbols based on a comparison with the updated first reliability value of one of the candidate symbols with a first threshold value.

Abstract: A decoder for decoding a binary symmetry-invariant product code includes a data array having orthogonal first and second dimensions. The data array is configured to access a binary symmetry-invariant product code buffered therein along only the first dimension. The decoder also includes an error storage array for storing error locations and a first correction circuit configured to detect and correct errors in data accessed from the data array along the first dimension and to store error locations along the second dimension in the error storage array. The first correction circuit determines the error locations based on data symmetry of the symmetry-invariant product code. The decoder also includes a second correction circuit that, prior to receipt by the first correction circuit of data accessed from the data array along the first dimension, corrects the data accessed from the data array based on the error locations stored in the error storage array.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.

Abstract: The present technology relates to a data processing device and a data processing method so that an LDPC code with a good bit error rate is provided. An LDPC encoder encodes by an LDPC code whose code length is 16200 bits and code rate is 10/15. The LDPC code includes information bits and parity bits. A parity check matrix H includes an information matrix part corresponding to the information bits of the LDPC code and a parity matrix part corresponding to the parity bits. The information matrix part of the parity check matrix H is represented by a parity check matrix initial value table that indicates a position of an element 1 of the information matrix part for each 360 columns. The present technology is applicable to a case in which LDPC encoding and LDPC decoding are performed.

Abstract: A method includes the following. A first communications device obtains an ith data packet, divides the ith data packet into N data blocks, performs fountain-code encoding on the N data blocks to generate K fountain-code codewords, generates K protocol data units (PDUs) based on the K fountain-code codewords, and sends the K PDUs to a second communications device; and after the first communications device receives first acknowledgement information sent by the second communications device, the first communications device stops, based on the first acknowledgement information, sending a to-be-sent PDU in the K PDUs to the second communications device.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.

Abstract: In a memory controller for performing error correction decoding, using an iterative decoding scheme, the memory controller includes a variable node update module for allocating the initial LLR values to variable nodes, and updating values of the variable nodes, using the initial LLR values and Check to Variable (C2V) messages corresponding to the variable nodes in an ith iteration, a syndrome checker for performing a syndrome check, using the values of the variable nodes updated in the ith iteration, and a reversal determiner for determining whether to reverse the sign of an initial LLR value of a target variable node based on a ratio of signs of C2V messages corresponding to the target variable node, when the syndrome check corresponding to the ith iteration fails.

Abstract: The invention relates to methods of interleaving payload data and integrity control data in an external memory interfaced with a microcontroller to improve data integrity check, enhance data confidentiality and save internal memory. Data words are received for storing in the external memory. Each data word is used to generate a respective integrity word, while an associated logic address is translated to two physical addresses in the external memory, one for the data word and the other for the integrity word. The two physical addresses for the data and integrity words are interleaved in the external memory, and sometimes, in a periodic scheme. In particular, each data word may be associated to an integrity sub-word included in an integrity word having the same length with that of a data word. The external memory may have dedicated regions for the data words and the integrity words, respectively.

Abstract: Generating loosely coupled parts by forming couplings between partial nodes in a hierarchical neural network in accordance with a check matrix of an error correcting code.

Abstract: A low density parity check (LDPC) channel encoding method for use in a wireless communications system includes a communication device encoding an input bit sequence by using a LDPC matrix to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. The encoding method can be used in various communications systems including the fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths.

Abstract: Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low density parity check (LDPC) codes. A method for wireless communications by wireless node is provided. The method generally includes encoding a set of information bits based on a LDPC code to produce a code word, the LDPC code defined by a matrix having a first number of variable nodes and a second number of check nodes, puncturing the code word to produce a punctured code word, wherein the puncturing is performed according to a first puncturing pattern designed to puncture bits corresponding to one or more of the variable nodes having a certain degree of connectivity to the check nodes, and transmitting the punctured code word.

Abstract: A method includes sending a read threshold number of access requests to storage units regarding a set of encoded data slices. The method further includes receiving access responses from at least some of the storage units in response to the read threshold number of access requests. The method further includes determining, from the access responses, that writing of the set of encoded data slices to a set of storage units has not been finalized. The method further includes determining whether the computing device can finalize the writing of the set of encoded data slices on behalf of a source that initiated the writing. When the computing device can finalize the writing, the method further includes determining one or more finalization steps for completing the writing and executing the one or more finalization steps to complete the writing of the set of encoded data slices.

Abstract: Data from a communications channel is decoded by receiving data bits corresponding to encoded data, determining a set of data representations from the data bits, distributing the set of data representations into bins across a dynamic range to generate a distribution of the data representations, assigning a respective intermediate scale factor to each bin, deriving a set of moments from the intermediate scale factors, combining the moments into a scaling factor, scaling the data representations by the scaling factor, and sending the scaled data representations to a decoder. The data representations may be a histogram or cumulative distribution function of log-likelihood ratios (LLRs) or values based on channel estimates. In an iterative implementation performed until a stopping condition is met, the data representations may be scaled down on later iterations to avoid saturation. A correction factor may be applied to update the scaling factor for later data bits.

Abstract: Erasure coding is utilized to facilitate data protection in several high-end storage systems. After a failure, the system commences the process of data recovery. Typically, the system can detect data portions impacted by the failure. In one aspect, the system can trigger recovery of the impacted data portions in a sequence that reduces a probability of data losses and a probability of temporary read failures.

Abstract: Embodiments of this application disclose provides a low density parity check (LDPC) channel encoding method for use in a wireless communications system. A communication device encodes an input bit sequence by using a LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. Embodiments of the application provide eight particular designs of the base matrix. The encoding method provided in the embodiments of the application can be used in various communications systems including the fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths.

Abstract: A method and a system for monitoring conditions of offline storage devices is disclosed. Predetermined environmental conditions are monitored to determine whether a storage device should be brought online to perform a data integrity check process. The process receives a triggering event that corresponds with the storage device, powers on the storage devices, selects a page from the storage device, and determines a bit error rate. Once the bit error rate is determined, error-correcting code runs to correct the errors. Any uncorrectable errors are reported, and the storage device is brought back offline.

Abstract: Provided is a method for correcting errors in a data transmission network, comprising: transmitting a plurality of uncoded information packets across a network path; transmitting a plurality of coded packets for recovering information packets lost in transmission across said network path, the coded packets being temporally interspersed among said uncoded information packets, wherein the coded packets are encoded based on information packets transmitted prior to a previously transmitted coded packet; and determining the interspersion of the coded packets according to a packet loss rate.

Abstract: There are included an error signal generation unit that generates an error signal for adding a burst error to each of an MSB and an LSB of the PAM4 signal in units of clock cycles, an error addition unit that performs an exclusive OR operation on the MSB and the LSB and the error signal and outputs bit strings obtained as a result of the operation, and a calculation unit that calculates the minimum number of clock cycles required for realizing a bit error rate of a desired test signal and the number of burst errors to be added to the MSB and the LSB during a period of the minimum number of the clock cycles.

Abstract: A polar code decoding method in which a first decoding attempt by successive cancellation is performed and in the case where the decoded frame is erroneous, an ordered list of bit positions to be tested in the frame is generated, the order relation being given by a metric of first error, the value of this metric depending on the reliability of the decision about the bit as well as on the reliability of the decisions about the bits preceding it in the frame. For each of the positions of the list, an inversion of the bit and a decoding of the subsequent bits are undertaken, doing so as long as the list has not been exhausted or the frame has not been decoded without error. In case of failure, a new decoding attempt based on a double-inversion of bits can be envisaged.

Abstract: Wireless communication devices are adapted to facilitate transmission and reception of non-orthogonal communications. In one example, wireless communication devices can encode an amount of data in accordance with information that at least some of the data will be transmitted as part of a non-orthogonal transmission. The wireless communication device may further transmit the encoded data, and the encoded data can be non-orthogonally combined as part of a non-orthogonal transmission. In another example, wireless communication devices can receive a wireless transmission including a plurality of data streams non-orthogonally combined together. The wireless communication device may decode at least one of the data streams. Other aspects, embodiments, and features are also included.

Abstract: A storage system and method for handling a burst of errors is provided. In one embodiment, the method comprises generating a protograph using an error code generation method; generating a first partially-lifted protograph based on the generated protograph that avoids a first burst of errors; generating a fully-lifted protograph based on the generated protograph and the generated first partially-lifted protograph; and providing the fully-lifted protograph to a storage system comprising a memory.

Abstract: A transmitting apparatus encodes information bits using a low density parity check (LDPC) encoder, which is configured to encode information bits to generate parity bits based on a parity check matrix. In some embodiments, the code rate is 8/15 and the code length is 64800. The transmitting apparatus also includes an interleaver configured to interleave an LDPC codeword including the information bits and parity bits and a mapper configured to map the interleaved LDPC codeword onto constellation points. In some embodiments, the parity check matrix comprises an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits. In some embodiments, the information matrix part is defined by a specific table indicating indices of rows at which a value “1” is positioned in a 0-th column of an i-th column group in the parity check matrix.

Abstract: A data storage device may include: a storage configured to store user data, firmware and a boot code; and a controller configured to control data exchange with the storage, and comprising an error correction code (ECC) engine configured to perform error correction during the data exchange, wherein the ECC engine stores a first parity check matrix, performs error correction on data exchanged with the storage based on the first parity check matrix during a first operation mode, and performs error correction on data exchanged with the storage based on a second parity check matrix extracted from the firmware during a second operation mode.

Abstract: A method is proposed for operating a solid state storage device. The method comprises: encoding information and frozen bits into polar encoded bits; storing the polar encoded bits; reading the polar encoded bits, wherein the read polar encoded bits include the frozen bits and unfrozen bits, and performing a SCL decoding. The SCL decoding comprises: providing a list of candidate decoding paths; duplicating the candidate decoding paths; determining a maximum list size indicative of an allowed maximum number of candidate decoding paths that can be contained in the list of candidate decoding paths; pruning at least one duplicated candidate decoding path according to the maximum list size, and including in the list of candidate decoding paths a number of non-pruned duplicated candidate decoding paths not higher than the maximum list size; and selecting a decoding path from the list of candidate decoding paths.

Abstract: Embodiments of the present invention provide a signal processing method and device. The method includes: receiving soft information corresponding to encoded signals sent by at least two base stations and CRC check results of decoding results of first subflows in the encoded signals, where the soft information includes first soft information corresponding to the first subflows; obtaining a selective combining result of the first subflows by performing selective combining according to the at least two CRC check results of the decoding results of the first subflows; and if the selective combining result of the first subflows is that CRC check is incorrect, determining a soft combining result of the first subflows according to at least two pieces of the first soft information. The signal processing method and device provided in the embodiments can increase a signal gain.