Abstract: The inventive concept provides a security device capable of reducing an area of a die required for implementation of a stable PUF by increasing the value of entropy from a predefined number of entropy sources and/or minimizing a blind zone of a validity checking module. The security device uses an asynchronous configuration to minimize a blind zone. In various embodiments of the inventive concept, the blind zone is generated only in a period when a reset signal is at a first logic level. Therefore, it is possible to minimize the blind zone by minimizing a period in which the reset signal is at such logic level. A semiconductor device, semiconductor package, and/or smart card can be provided with such security device, as well as a method for determining a validity of a random signal using a semiconductor security device.

Abstract: A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme.

Abstract: The disclosure relates to a first wireless node for a wireless communication system, the wireless node comprising processing means operative to obtain input data, a set of target parity encoding properties for the input data and a set of predetermined parity encoding codes each having a set of offered parity encoding properties, obtain a candidate parity encoding code from the set of predetermined parity encoding codes by evaluating a set of criteria on the set of target parity encoding properties and the sets of offered parity encoding properties, wherein evaluating the set of criteria comprises comparing a target information block length and a target number of encoding parity bits, comprised in the target parity encoding properties, to an offered information block length and an offered number of encoding parity bits, comprised in the offered parity encoding properties, and generate transmission data by encoding the input data using the candidate parity encoding code.

Abstract: Wearable audio recorder and retrieval software applications for long term audio and related data recording, visualization, filtering, search, and proof of provenance, providing a record-all and find-later methodology capable of finding audio in multi-year audio data streams. System default state is to record permanently, allowing the user to decide when not to record instead of when to record. User interfaces enable users to retrieve desired recorded audio data by querying other types of recorded data which are related to the desired recorded audio data by way of time and spatial domains.

Abstract: Coding for bursty interference is discussed in which a base station receives data bits for transmission. The base station may generate code blocks including information bits and parity bits. The base station may also generate parity check code blocks including information bits corresponding to information bits of the generated code blocks. The base station may transmit the code blocks and the parity check code blocks to a mobile device to improve decoding. When errors are detected, the mobile device may decode the received code blocks using hard or soft parity checks and the parity check code blocks.

Abstract: Decoding method includes calculating cyclic redundancy check (CRC) parity bits for data on-the-fly; performing a low-density parity-check (LDPC) decoding for the data; if it is determined that an iteration of is finished, updating the calculated CRC parity bits to generate CRC parity bits; comparing the generated CRC parity bits with CRC bits included in the data; and terminating the LDPC decoding based on the comparison result.

Abstract: A system and method are provided for verifying and reconstructing a file using cyclic redundancy checks (CRCs). A writer client sends a file, which includes data chunks including one or more data blocks, and code chunks including one or more code blocks. One or more storage devices store the packets underlying the one or more data blocks and their respective packet CRCs. A curator server stores a first CRC for each complete data chunk and each complete code chunk and determines that an incomplete code chunk has one or more missing code blocks. The curator server generates a second CRC for each of the complete data chunks and the complete code chunks using the packet CRCs, and compares the generated second CRCs with the respective stored first CRCs. The curator server generates a missing chunk CRC for the incomplete code chunk using the packet CRCs.

Abstract: A decoder circuit includes an input configured to receive an encoded message generated based on a QC-LDPC code. A first layer process unit is configured to process a first layer of a parity check matrix to generate a plurality of log-likelihood ratio (LLR) values corresponding to a plurality of variable nodes associated with the encoded message respectively. The first layer process unit includes a plurality of row process units configured to process a first plurality of rows of the first layer in parallel to generate a plurality of row update values. A layer update unit is configured to generate a first LLR value for a first variable node using first and second row update values for the first variable node. An output is configured to provide a decoded message generated based the plurality of LLR values.

Abstract: A decoding method and a decoder for a low-density parity-check (LDPC) code, where the method includes dividing, by a decoder, an LDPC code C whose bit length is n into k LDPC codes D={D1,D2,K,Dk-1,Dk}, arranging, by the decoder, Di, i=1,2,K,k?1,k by column to obtain transpose codes DT={D1T,D2T,K,Dk-1T,DkT} of the LDPC codes D, performing cyclic shift on DiT,i=1,2,K,k?1,k by row according to values of corresponding elements in a target check matrix to obtain shift codes E={E1,E2,K,Et-1,Et}, where t is equal to a quantity of rows of the target check matrix, obtaining, by the decoder, t*m groups of LDPC subcodes F1,F2,K,Ftm-1,Ftm according to the shift codes E and a bit length d of the decoder, where Ej is divided into m groups, Ej={(Ej)1d,(Ej)d+12d,K,(Ej)(m-2)d+1(m-1)d,(Ej)(m-1)d+1md}={F(j-1)m+1,F(j-1)m+2,K,Fjm-1,Fjm}, and m=?l/d?, and decoding, by the decoder, the m groups of LDPC subcodes to obtain a decoding result of the LDPC code C.

Abstract: An operating method of a controller includes generating a square message matrix of k×k; and generating an encoded message by encoding the square message matrix row by row through a Bose-Chadhuri-Hocquenghem (BCH) code, wherein the square message matrix includes an upper triangular matrix and a lower triangular matrix, which are symmetrical to each other with reference to zero-padding blocks included in a diagonal direction in the square message matrix, wherein the upper triangular matrix includes “?” numbers of message blocks, each of which has a size of “?+1”, and “(N??)” numbers of message blocks, each of which has a size of “?”, and wherein “?”, “?” and N have relationships represented by equations 1 and 2: ? = ? M N ? [ Equation ? ? 1 ] ? = M ? ? mod ? ? N [ Equation ? ? 2 ] where “M” represents a size of a message input from a host and “N” represents a number of message blocks forming the upper triangular matrix.

Abstract: One example includes an ACM transceiver system. An ACM transceiver system includes an ACM controller configured to receive a reported signal-to-noise ratio (SNR) via each of a plurality of return signals corresponding to a respective plurality of transmit signals that were each sequentially previously transmitted from the ACM transceiver system in a respective modulation and coding scheme (MODCOD). The reported SNR via a given one of the plurality of return signals corresponds to the respective one of the plurality of transmit signals. The ACM controller continuously generates an adaptive SNR threshold associated with each of the plurality of MODCODS based on the reported SNR delivered by the received plurality of return signals, and compares the reported SNR with the adaptive SNR threshold of each of the plurality of MODCODS to select one of the plurality of MODCODS for transmission of a next transmit signal.

Abstract: The present invention concerns a method and device for demodulating received symbols using a turbo-demodulation scheme comprising an iterative MIMO decoder and wherein an iterative channel decoder is used in the turbo-demodulation scheme, wherein the iterative channel decoder performs a first iterative process named iterative decoding process, the turbo-demodulation performing a second iterative process named iterative demodulation and decoding process, at each iteration of the second iterative process, the iterative channel decoder executing plural iterations in order to decode bits from which symbols are derived from. The iterative channel decoder: memorizes at the end of the iterations of the first iterative process, the variables used internally by the iterative channel decoder, reads the memorized variables at the following iteration of the second iterative process.

Abstract: According to one embodiment, a memory system includes a resistance change type memory including a memory cell configured to hold first data and an ECC circuit configured to detect and to correct an error in the first data; and a controller configured to control an operation of the resistance change type memory. In a read operation for the memory, when the first data from the memory cell includes an error, the memory transmits second data in which the error is corrected and a first signal to the controller. The controller transmits a control signal and a write command to the memory based on the first signal. The memory writes the second data to the memory cell based on the control signal and the write command.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.

Abstract: A system to implement a communication line coding scheme using a non-complex bit-to-symbol mapping, a forward error correction (FEC) coding, and an additive bit scrambler after the FEC at the PHY layer is provided. The system may be a part of or implemented by an automobile component. The system may be a PHY device configured to convert data from the MAC layer into 2D-PAM3 symbols that are transmitted across a communication link at a predetermined transmission rate, such as to be compliant with a communication standard. The PHY device may select characteristics of the conversion, such as the FEC coded symbol, based on the target transmission rate. The PHY device may include a transceiver, and may convert the data from MAC layer to PHY layer and back.

Abstract: A method of operating a signal processing apparatus (110) comprises receiving a first signal representing a received data bit, determining from the first signal a first soft data bit, storing the first soft data bit in a leaky storage device (130), receiving a second signal representing the received data bit, and determining from the second signal a second soft data bit. The stored first soft data bit is read from the leaky storage device (130), an elapsed leakage time of the stored first soft data bit is measured, and a third soft data bit is generated dependent on the stored first soft data bit read from the leaky storage device (130) and on the elapsed leakage time. A fourth soft data bit is generated by combining the second soft data bit and the third soft data bit, and the received data bit is decoded dependent on the fourth soft data bit and on a selected plurality of further received data bits.

Abstract: An integrity check for a first file is initiated. In response, a first key corresponding to the first file is obtained. The first file is hashed to determine that the first key is not equivalent to the hashed first file. A second key is then obtained that corresponds to the hashed first file. A second file is then obtained using the second key. This second file is hashed to determine whether the second key is equivalent to the hashed second file. Integrity of the first file is confirmed if the second key is equivalent to the hashed second file or integrity of the first file is rejected if the second key is not equivalent to the hashed second file. Related apparatus, systems, techniques and articles are also described.

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to perform a low-density parity check (LDPC) encoding on input bits using a parity check matrix to generate an LDPC codeword comprising information word bits and parity bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Abstract: The present technology relates to a transmission apparatus, a transmission method, a reception apparatus, a receiving method, and a program that enable prompt data delivery. An LCT packet including a portion which is data including part of a fragment; and an LCT header is delivered. The fragment includes a moof and an mdat including an mdat header and a sample group. The moof includes BaseMediaDecodeTime representing a presentation time of a first sample of the mdat. The LCT header includes a sequence number representing a position of the fragment; a version representing a position of the part of the fragment in the fragment; an NTP time corresponding to the BaseMediaDecodeTime; sample count start information representing a position of a first sample of the part of the fragment from a first sample of the fragment; and a moof subset that is at least part of the moof. The present technology can be applied to, for example, a case of multicast-delivering content.

Abstract: Techniques are provided for receiving data at a physical coding sublayer (PCS) transmit structure from a media access control (MAC) sublayer. Data is received at a PCS transmit structure from a MAC sublayer, and one or more alignment markers are inserted in the data. FEC encoding is performed, in a first clock domain, on the one or more alignment markers and the data in the PCS transmit structure to generate FEC encoded data. The FEC encoded data is transmitted from the first clock domain with a first clock cycle to a second clock domain with a second clock cycle, and the FEC encoded data is transmitted on one or more physical medium attachment (PMA) lanes to a PCS receive structure. FEC decoding is performed, in the second clock domain, on the FEC encoded data in the PCS receive structure to generate FEC decoded data.

Abstract: Dynamically adjusting an error correction effort level of a storage device, including: receiving, from a storage array controller, an error correction effort level to perform when attempting to read data from the storage device; identifying that an attempt to read the data resulted in an error; and determining whether an amount of error correction effort level required to attempt to correct the error exceeds the error correction effort level to perform when attempting to read data from the storage device.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.

Abstract: An apparatus and a method for transmitting and receiving a signal in a communication system are provided. The method includes checking a type of the signal to be transmitted; determining a number of puncture bits according to the type of the signal; and puncturing an encoded signal to be transmitted according to the number of puncture bits.

Abstract: This application provides an encoding method and apparatus in wireless communications between a network device and a terminal. The method includes: performing CRC encoding on A to-be-encoded information bits based on a CRC polynomial, to obtain a first bit sequence, where the first bit sequence includes L CRC bits and A information bits, L=6; and performing polar encoding on the first bit sequence. Based on an improved CRC polynomial, encoding satisfying an FAR requirement is implemented.

Abstract: A method for communication device processing a data block in a low-density parity-check (LDPC) encoder includes the steps of, if a size of a payload is equal to or greater than a prescribed size, performing code block segmentation, and performing encoding in a unit of a code block on code blocks according to the code block segmentation. In this case, the code block segmentation may be performed by a payload size supported by a parity check matrix (H) corresponding to a coding rate of the LDPC encoder.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Abstract: A data protection technique combines error correcting code and redundant array of independent disk functionality for a non-volatile memory (NVM) array of a data storage system. The technique includes receiving, by a controller, data for storage in the NVM. In response to receiving the data for storage in the NVM array, the controller forms first component codewords based on encodings with a first level code of respective first portions of the data. In response to receiving the data for storage in the NVM array, the controller forms a second component codeword based on an encoding with a second level code of a second portion of the data and the first component codes. The controller stores a respective portion of each of the first and second component codeswords on packages of the NVM array. The storing achieves maximum equal spreading of each of the component codewords across all of the packages.

Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to perform parity-permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups configuring the interleaved parity bits based on a group-wise interleaving pattern including a first pattern and a second pattern; a puncturer configured to puncture some of the parity-permutated parity bits; and an additional parity generator configured to select at least some of the punctured parity bits to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern, wherein the first pattern determines parity bits to remain after the puncturing and then to be transmitted in the current frame.

Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells, one or more control circuits in communication with the set of non-volatile memory cells, the one or more control circuits are configured to encode data with a code rate prior to storage in the set of non-volatile memory cells, the code rate selected from two or more code rates according to one or more predictive indicators received with the data, the one or more predictive indicators relating to expected conditions for storage of the data in the set of non-volatile memory cells.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

Abstract: Encoding and decoding systems are provided for reduced latency at the decoder. In the encode error detection codewords are produced from source bits. The error detection codewords are then encoded with a systematic error correction encoder to produce a set of parity bits. All of the systematic code source bits and at least some of the parity bits are mapped to modulation symbols for transmission. In the decoder, two signal processings are performed in parallel, one based on soft bit decisions and the other based on hard bit decisions. The soft bit decisions are processed using a systematic error correction decoder. The hard bit decisions are processed by re-encoding error detection codewords to produce parity bits. If the produced parity bits match received parity bits, then the hard bit decisions are reliable and are output without waiting for the result of the systematic error correction decoder.

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Abstract: A transmitter is provided. The transmitter includes: a segmenter configured to segment information bits into a plurality of blocks based on one of a plurality of preset reference values; an outer encoder configured to encode each of the plurality of blocks to generate first parity bits; and a Low Density Parity Check (LDPC) encoder configured to encode each of the plurality of blocks and the first parity bits to generate an LDPC codeword including second parity bits, wherein the one of the preset reference values is determined depending on at least one of a code rate used to encode each of the plurality of blocks and the first parity bits and whether to perform repetition of at least a part of the LDPC codeword in the LDPC codeword.

Abstract: A method for integrating a Proof of Storage (PoS) into a blockchain increases security, robustness and verifiability of a blockchain network. A part of the blockchain to be stored is received at a first one of a plurality of mining nodes of the blockchain network. The part of the blockchain is stored. Mining of the new block is bound to the stored data and performed so as to enforce that the mining nodes store different parts of the blockchain. The PoS is integrated into the new block. The PoS is verified before accepting the new block into the blockchain.

Abstract: A transmitter, a receiver and methods of controlling the transmitter and the receiver are provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to generate an LDPC codeword by performing LDPC encoding on an L1 post signaling; a demux configured to demultiplex a plurality of bits constituting the L1 post signaling of the LDPC codeword; and a modulator configured to modulate the demultiplexed bits.

Abstract: A decoder is configured to perform, for a unit of data received by the decoder, a plurality of decoding iterations in which a plurality of messages are passed between a plurality of check nodes and a plurality of variable nodes, each message indicating a degree of reliability in an observed outcome of data. The decoder determines, for each of the plurality of decoding iterations, whether a trigger condition is satisfied based on an internal state of the decoder and, when a trigger condition is determined to be satisfied during a respective decoding iteration, scales one or more respective messages of the plurality of messages during a subsequent decoding iteration. The unit of data is decoded based on the plurality of decoding iterations and at least one scaled message resulting from the trigger condition being satisfied during the respective decoding iteration.

Abstract: A method for protecting configuration data from a data bus transceiver operable in a subnetwork mode. The configuration data are provided for comparison with data bus message data arriving via a data bus. A reference checksum for the configuration data is generated and stored, and recurrently checked. In the event of an identified alteration, a wake-up signal and/or a piece of error information is output. During or after writing the configuration data to a configuration register via the data bus or directly before the change to the low-power mode of the electronic control unit, a checksum unit forms a checksum that is stored in a reference register. In the low-power mode of the electronic control unit, the checksum for the configuration is repeatedly recomputed and compared with the checksum stored in the reference register. If the recomputed checksum does not match the stored checksum, a wake-up process is triggered.

Abstract: A low-density parity check (LDPC) decoder may include a variable node processing unit and a check node processing unit. The check node processing unit includes memory elements storing a check node value. The memory elements are interconnected through two or more paths, and each of the paths may include a total or partial cyclic permutation of the memory elements to transmit the check node value.

Abstract: Apparatuses and methods for special subframe configuration in unlicensed spectrum are disclosed. For example, the disclosure presents an example method including identifying a time period for an extended clear channel assessment (ECCA) operation. Further, the example method may include determining a guard period portion included in a special subframe of a frame structure based on the identified time period. An apparatus may include means for identifying a time period for an extended clear channel assessment (ECCA) operation. Further, the example apparatus may include means for determining a guard period portion included in a special subframe of a frame structure based on the identified time period.

Abstract: Vector signaling codes providing guaranteed numbers of transitions per unit transmission interval are described, along with methods and systems for their generation and use. The described architecture may include multiple communications sub-systems, each having its own communications wire group or sub-channel, clock-embedded signaling code, pre- and post-processing stages to guarantee the desired code transition density, and global encoding and decoding stages to first distribute data elements among the sub-systems, and then to reconstitute the received data from its received sub-system elements.

Abstract: An apparatus for decoding data includes a data decoding circuit configured to decode data encoded with an irregular low density parity check code based on a parity check matrix with non-uniform column weights, and at least one scaling circuit configured to scale values in the data decoding circuit with a scaling value that is dependent at least in part on a column weight of the likelihood values being scaled.

Abstract: A method and apparatus for an adaptive Hypertext Transfer Protocol (HTTP) streaming service using metadata of content are provided. The metadata may include a minBufferTime attribute indicating a minimum amount of initially buffered media content. A terminal may receive content from a server before playback of the content, and may buffer the content by at least the minimum amount. The metadata may include a range attribute that designates a range of a target indicated by a Uniform Resource Locator (URL). The terminal may receive bytes designated by the range attribute from the URL, and may play back the content using the received bytes.

Abstract: The present disclosure relates to multiple-symbol combination based decoding for general polar codes. Multiple-symbol combination based decoding of a received word that is based on a codeword involves determining whether all nodes at an intermediate stage of the multiple-symbol combination based decoding, which provide their outputs as inputs to a subset of nodes at a next stage of the multi-symbol combination based decoding, are associated with trust symbols in the received word that have a higher reliability of being successfully decoded than doubt symbols in the received word. A hard decision is performed in response to a positive determination.

Abstract: A method is proposed for managing a parity-check node calculation unit of an error-correcting code decoder having a representation as a bipartite graph comprising at least one parity-check node, the parity-check node being configured to receive first and second input messages, and to produce an output message, the elements of the input and output messages of the parity-check node comprising a symbol and a measure of reliability associated with the symbol, the first and second input messages containing lists of elements ordered by their measure of reliability. The method comprises: initializing a plurality of nbub FIFO memories with elements calculated from combinations of elements of the first and second input messages, and iteratively determining the values of the output message.

Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to interleave the parity bits and group-wise interleave a plurality of parity bit groups configuring the interleaved parity bits based on a group-wise interleaving pattern including a first pattern and a second pattern to perform parity permutation; a puncturer configured to puncture at least some of the group-wise interleaved parity bit groups; and an additional parity generator configured to select at least some of the punctured parity bit groups to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern.

Abstract: The present embodiments relate to methods and apparatuses for detecting a codeword boundary and/or performing codeword error correction for a bitstream comprising scrambled Reed Solomon codewords. In accordance with some aspects, detecting a codeword boundary involves the use of the parity and symbols from a previous window to help in detecting a codeword boundary when the next input bit is received. In accordance with other aspects, parity symbols are more efficiently updated for each successive candidate input bit. In accordance with still further aspects, error correction during codeword boundary detection can be either partially performed or completely bypassed.