Abstract: Although a distributed storage device can recover data from multiple failures this process produces excessive inter-zone network traffic when a chunk with user data is deleted. This disclosure employs an un-encoding erasure coding and partial coding chunks to facilitate data deletes while reducing inter-zone network traffic. Therefore a data chunk representative of partitioned disk space associated with a first zone of a data store can be determined to be marked for deletion. Consequently, the data chunk can be copied, resulting in a copied data chunk, to a second zone of the data store associated with a coding chunk comprising the data chunk. Based on the copied data chunk and the coding chunk, a partial coding chunk can be generated via un-encoding, wherein the partial coding chunk is a subset of the coding chunk.

Abstract: Examples include techniques for improving low-density parity check decoder performance for a binary asymmetric channel in a multi-die scenario. Examples include logic for execution by circuitry to decode an encoded codeword of data received from a memory having a plurality of dies, bits of the encoded codeword stored across the plurality of dies, using predetermined log-likelihood ratios (LLRs) to produce a decoded codeword, return the decoded codeword when the decoded codeword is correct, and repeat the decoding using the predetermined LLRs when the decoded codeword is not correct, up to a first number of times when the decoded codeword is not correct.

Abstract: Data communication is performed appropriately. An information processing apparatus includes a control unit. In a case of transmitting data by using wireless communication, the control unit performs control of performing transmission while including determination information with which a device in a transmission destination of the data determines in a data link layer whether to pass the data to a higher layer of the data link layer into the data. Also, in a case of receiving data by using wireless communication, the control unit performs control of determining whether to pass the data to a higher layer of a data link layer on the basis of information included in the data (determination information that can be grasped in data link layer).

Abstract: A memory system, a bit-flipping (BF) low-density parity check (LDPC) decoder included in the memory system and operating methods thereof in which such decoder or decoding has a reduced error floor. Such a BF LDPC decoder is configured using a deep learning framework of trained and training neural networks and data separation that exploits the degree distribution information of the constructed LDPC codes.

Abstract: A polar code encoding and decoding method includes generating a first and second sub-codewords. The sub-codewords correspond to pre-codewords, and the pre-codewords have a shared data aspect. The sub-codewords provide useful error-recovery for data stored in a memory. When data is read from the memory, decoding takes place. The data read operation may include hard decision decoding, soft decision decoding, or hard decision decoding followed by soft decision decoding. In the method, the shared data aspect is used to decode a first sub-codeword for which decoding was not initially successful. An apparatus is also provided.

Abstract: Methods and apparatus for the decoding of forward error correction codes. One method includes decoding a number of component codes including code symbols, for which at least one code symbol is involved in multiple component codes, and analyzing the decoding of each of the component codes to generate an outcome. Analyzing the decoding includes estimating at least one possible error location, storing information related to the at least one possible error location; storing state information, and updating the state information.

Abstract: A parity check matrix generator for generating a parity check matrix including non-binary cyclic permutation matrices may include: a first memory configured to store a first weight as location information on a non-binary cyclic permutation matrix within the parity check matrix; a second memory configured to store a second weight as cyclic strength of matrix elements of the non-binary cyclic permutation matrix; a third memory configured to store a third weight used to determine a size of a non-binary matrix element among the matrix elements of the non-binary cyclic permutation matrix; and a matrix generator configured to generate the non-binary cyclic permutation matrix by applying a non-binary value to matrix elements of 1's among matrix elements of a binary cyclic permutation matrix having a size corresponding to the non-binary cyclic permutation matrix and reflecting one or more of the first to third weights into the non-binary value.

Abstract: An apparatus is provided. The apparatus comprises a first syndrome computation circuit configured to receive a codeword having a plurality of rows and a plurality of columns and further configured to compute a first syndrome for at least a portion of a first component codeword of the codeword. The apparatus further comprises a second syndrome computation circuit configured to receive the codeword and to compute a second syndrome for at least a portion of a second component codeword of the codeword. The apparatus further comprises a bit correction circuit configured to correct one or more erroneous bits in the codeword based, at least in part, on at least one of the first and second syndrome, wherein the first and second component codewords span two or more rows and two or more columns of the codeword.

Abstract: A memory system with a shared buffer architecture for multiple decoders reduces transfer latency and power consumption. Such memory system includes a memory device to generate codewords, and a dynamic memory access (DMA) assembly to receive the generated codewords. A first decoding stage of the system comprises a checksum module and a shared memory buffer, including a memory manager and destination ports, that stores and manages codewords received from the DMA assembly. A second decoding stage of the system comprises a bit-flipping (BF) decoder and a min-sum (MS) decoder, each in communication with the shared memory buffer through a respective one of the destination ports. In managing the codewords stored in the shared memory buffer, the memory manager controls assignment including reassignment of the codewords among the destination ports.

Abstract: A pipeline decoding system for performing pipelined decoding of a codeword characterized by one or more parity checks may include a first pipeline stage circuit configured to process a first parity set composed of one or more first parity checks of the codeword and to process a second parity set composed of one or more second parity checks of the codeword, a second pipeline stage circuit configured to generate one or more codeword update messages for the second parity set based on a first estimate of the codeword, and a third pipeline stage circuit configured to update the first estimate of the codeword with one or more codeword update messages for the first parity set to obtain a second estimate of the codeword.

Abstract: A decoder circuit can include low-density parity-check (LDPC) decoder circuitry having a plurality of stages and an LDPC repository configured to store parity-check information associated with one or more LDPC codes. The LDPC repository is configured to determine a stall requirement for a layer of a first data block and perform a memory check for a second data block. The LDPC repository, in response to the stall requirement indicating a stall for the layer of the first data block and determining that the memory check is satisfied, is further configured to schedule processing of the first data block and the second data block in the LDPC decoder circuitry using the parity-check information by interleaving the layer of the first data block and a layer of the second data block through the plurality of stages of the LDPC decoder circuitry.

Abstract: A data storage system capable of switching a code rate based on a host command is disclosed. A controller of the data storage system may set a code rate in a data storage device to a first code rate for encoding data to be written to non-volatile memory of the data storage device. The controller may receive, at the data storage device, a host command indicating a switch point for switching the set code rate from the first code rate to a second code rate. The controller may switch the set code rate from the first code rate to the second code rate at the indicated switch point.

Abstract: According to some embodiments, a method for use in a wireless transmitter of a wireless communication network comprises encoding information bits using a parity check matrix (PCM) and transmitting the encoded information bits to a wireless receiver. The parity click matrix (PCM) is optimized according to two or more approximate cycle extrinsic message degree (ACE) constraints. In some embodiments, a first portion of the PCM is optimized according to a first ACE constraint and a second portion of the PCM is optimized according to a second ACE constraint.

Abstract: A wireless communication device serving as an NG60 WiGig device includes a PPDU generator that generates an MF control PHY PPDU (physical layer protocol data unit) including a legacy preamble, a legacy header, an NG60 header (a non-legacy header), a data field, and identification information indicating that the non-legacy header is included in the PPDU and a transmitter that transmits the generated MF control PHY PPDU.

Abstract: A bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

Abstract: A method of low complexity SCL decoding for polar codes is disclosed. The method comprises receiving a codeword vector generated using polar encoding, and sequentially decoding multiple bits included in a source vector from the received codeword vector based on the successive cancellation list (SCL) decoding, wherein the decoding is configured not to perform a comparison of reliability between candidate decoding paths for a subset of information bits included in the source vector, but to determine value of the subset of information bits based on a reliability of the corresponding bit.

Abstract: Apparatuses and methods related to correcting errors can include using fast decoding (FD) decoders and accurate decoding (AD) decoders. Correcting errors can include receiving input data from the memory array, performing a plurality of operations associated with an error detection on the input data, and providing, based on processing the input data, output data, a validation flag, and a plurality of parity bits to a second decoder hosted by a controller coupled to the memory device.

Abstract: The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. In an embodiment, a method for encoding information bits includes receiving the information bits, encoding the information bits by using a block code, and outputting a codeword generated as a result of the encoding. A length of the information bits is a maximum of 13 bits, and the block code is composed of a Walsh basis sequence and a mask basis sequence.

Abstract: Techniques are described to address run-time issues and other considerations of data structure reorganization operations executed while decoding a polar code. A receiving entity (e.g., a user equipment or a base station) partitions an array, or other data structure, into sections. The array is used during a list decoding operation of a polar code. As the array is populated with path elements for candidate paths, each section is organized and a permutation pattern is calculated for each section. Upon identifying a section reorganization event, the array or subsections of the array are reorganized according the permutation patterns determined for each section.

Abstract: A data storage device is disclosed comprising a non-volatile storage medium (NVSM), wherein a plurality of codewords and corresponding parity sector are written to the NVSM and then read from the NVSM. Each codeword read from the NVSM is processed using a Viterbi-type detector, thereby generating codeword reliability metrics. The codeword reliability metrics for at least some of the codewords are processed using a low density parity check (LDPC) type decoder, thereby generating a LDPC reliability metric for each symbol of at least one codeword. The LDPC reliability metrics for at least one of an un-converged codeword are processed using the parity sector, thereby updating the un-converged codeword reliability metrics. Processing the codeword reliability metrics with the LDPC decoder and updating the reliability metrics with the parity sector is repeated at least once before updating the LDPC reliability metrics of at least the un-converged codeword using the Viterbi-type detector.

Abstract: A bandwidth efficient way to improve reliability without introducing additional latency is provided for Ultra-Reliable and Low Latency Communications (URLLC) service in 5G NR.

Abstract: Concepts and schemes pertaining to shift coefficient and lifting factor design for NR LDPC code are described. A processor of an apparatus may generate a quasi-cyclic-low-density parity-check (QC-LDPC) code and encode data using the selected codebook. In generating the QC-LDPC code, the processor may define a plurality of sets of lifting factors, generate a respective table of shift values for each lifting factor of the plurality of sets of lifting factors, and generate the QC-LDPC code using a base matrix and the shift coefficient table.

Abstract: In some embodiments, a method for die-level monitoring is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes. Each of the storage nodes has a non-volatile solid-state storage with non-volatile memory and the user data is accessible via the erasure coding from a remainder of the storage nodes in event of two of the storage nodes being unreachable. The method includes producing diagnostic information that diagnoses the non-volatile memory on a basis of per package, per die, per plane, per block, or per page, the producing performed by each of the plurality of storage nodes. The method includes writing the diagnostic information to a memory in the storage cluster.

Abstract: A QC-LDPC decoder includes: a zero matrix monitoring circuit, configured to monitor whether a submatrix of a check matrix of QC-LDPC coding information is a zero matrix; a check node processing circuit, configured to calculate check message of the check node by using the check matrix according to variable message of a variable node if the submatrix is not a zero matrix; a variable node processing circuit, configured to update the variable message of the variable node according to the check message returned by the check node if the submatrix is not a zero matrix; and a check circuit, configured to determine whether the variable message satisfies a check standard or not.

Abstract: One embodiment provides a silent data corruption (SDC) mitigation circuitry. The SDC mitigation circuitry includes a comparator circuitry and an SDC mitigation logic. The comparator circuitry is to compare a successful decoded codeword and a corresponding received codeword, the successful decoded codeword having been deemed a success by an error correction circuitry. The SDC mitigation logic is to reject the successful decoded codeword if a distance between the corresponding received codeword and the successful decoded codeword is greater than or equal to a threshold.

Abstract: A transmission apparatus includes: a data-symbol generation unit that generates data symbols for one block in each block; a storage and processing unit that stores therein a data symbol at a first position, among the data symbols for one block, as a copied symbol; a symbol insertion unit that generates a block symbol by putting the data symbols and the copied symbol such that the copied symbol stored in the storage and processing unit are inserted at a second position of the data symbols for one block; a time/frequency conversion unit that converts the block signal into a frequency domain signal; an interpolation unit that performs interpolation processing on the frequency domain symbol; and a CP insertion unit that generates the block signal by inserting a Cyclic Prefix into a signal on which the interpolation processing has been performed.

Abstract: Systems and methods for decoding block and concatenated codes are provided. These include advanced iterative decoding techniques based on belief propagation algorithms, with particular advantages when applied to codes having higher density parity check matrices such as iterative soft-input soft-output and list decoding of convolutional codes, Reed-Solomon codes and BCH codes. Improvements are also provided for performing channel state information estimation including the use of optimum filter lengths based on channel selectivity and adaptive decision-directed channel estimation. These improvements enhance the performance of various communication systems and consumer electronics.

Abstract: Methods and apparatus for transmitting and receiving data over a physical channel using a polar code are provided. The polar code defines a plurality of virtual channels within the physical channel and allocates a subset of the virtual channels for the transmission of data. The method for transmitting data: receives a block of data to be transmitted; receives additional data to be transmitted together with the block of data; selects one or more of the virtual channels; determines a scrambling sequence based on the additional data; applies the scrambling sequence to those bits of the block of data to generate a scrambled version of the block of data; and transmits the scrambled version of the block of data according to the polar code.

Abstract: Techniques for receiving data at a physical coding sublayer (PCS) transmit structure from a media access control (MAC) sublayer are provided. A PCS transmit structure is configured to receive data from a MAC sublayer, the PCS transmit structure comprising a first FEC hardware module that inserts one or more alignment markers in the data and performs FEC encoding, in a first clock domain, on the one or more alignment markers and the data to generate FEC encoded data. Further, a PCS receive structure configured to receive the FEC encoded data from the PCS transmit structure, the PCS receive structure comprising a second FEC hardware module is configured to perform FEC decoding, in the second clock domain, on the FEC encoded data to generate FEC decoded data, and remove the one or more alignment markers from the FEC decoded data.

Abstract: This disclosure relates to providing negative stopping criteria for turbo decoding for a wireless device. A device may wirelessly receive turbo coded data. Turbo decoding may be performed on the turbo coded data. Performing turbo decoding may use one or more negative stopping criteria for early termination of the turbo decoding for each code block of the turbo coded data. The negative stopping criteria may be selected to terminate the turbo decoding of a code block early under poor wireless medium conditions. Turbo decoding of a code block may be terminated early if the one or more negative stopping criteria for the code block are met.

Abstract: A coded signal is received via a physical channel. The coded signal is encoded by a parity check matrix. In some examples, the coded signal is low density parity check-encoded. The coded signal is decoded to determine a result signal. Said decoding alternatingly updates, for each one of a number of iterations, bit node values representing bits of the result signal and check node values representing constrains of the parity check matrix. In some examples, the decoding determines the result signal at a first precision and updates at least partly at a second precision which is lower than the first precision. In further examples, the number of iterations is dynamically adjusted.

Abstract: Dynamic erasure coding for computing and data storage systems. A method embodiment commences upon accessing a set of fault tolerance policy attributes associated with the computing and data storage system. The topology of the system is analyzed to form mappings between the computing nodes of the system and the availability domains of the system. Based on the fault tolerance policy attributes, the topology, and the generated mapping, a plurality of feasible erasure coding configurations are generated. The feasible erasure coding configurations are scored. One or more high-scoring feasible erasure coding configurations are selected and deployed to the computing and data storage system. The method is repeated when there is a change in the fault tolerance policy attributes or in the topology. Depending on the topology and/or the nature of a change in the topology, more than one erasure coding configurations can be deployed onto the computing and data storage system.

Abstract: A low-density parity check convolution code (LDPC-CC) is made, and a signal sequence is sent after being subjected to an error-correcting encodement using the low-density parity check convolution code. In this case, a low-density parity check code of a time-variant period (3g) is created by linear operations of first to 3g-th (letter g designates a positive integer) parity check polynomials and input data.

Abstract: A method for performing encoding on the basis of a parity check matrix of a LDPC code, according to one embodiment of the present invention, comprises the steps of: generating, by a terminal, a parity check matrix, wherein the parity check matrix corresponds to a characteristic matrix, each element of the characteristic matrix corresponds to a shift index value determined by a modulo operation between a corresponding element in a base matrix and a lifting value, and the base matrix is a 46×68 matrix; and performing, by the terminal, encoding of input data by using the parity check matrix, wherein the lifting value is associated with the length of the input data.

Abstract: Some embodiments include apparatuses and methods having a component to change a value of a bit among a number of M bits of information when the M bits have the same value and when M exceeds a selected value. At least one of such embodiments can include a transmitting component to provide the information to a connection. At least one of such embodiments can include a receiving component to receive the information from the connection. In at least one of such embodiments, the selected value can include a maximum number of consecutive bits having the same value that such a receiving component can be configured to receive. Other embodiments including additional apparatuses and methods are described.

Abstract: A communication device of handling transmissions comprises a storage device; and a processing circuit, coupled to the storage device, wherein the storage device stores, and the processing circuit is configured to execute instructions of: performing a first transmission comprising a first data and an identity of the communication device with a network via a first resource; and performing a second transmission comprising a second data and the identity of the communication device with the network via a second resource.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). The present disclosure discloses a method for effective retransmission when HARQ is applied to data encoded with a low density parity check (LDCP) code. A data transmission method of the transmitter may include: initially transmitting data encoded with an LDPC code to a receiver; receiving a negative acknowledgement (NACK) from the receiver; determining retransmission related information for data retransmission; and retransmitting, in response to the NACK, LDPC-encoded data based on the retransmission related information.

Abstract: A user equipment, according to one embodiment of the present invention, monitors candidates of a control channel which schedules system information in a configured specific CORESET based on a PBCH signal, obtains the system information scheduled by the control channel, and obtain a only part of entire parameters for configuring the specific CORESET from the PBCH signal. In this case, the user equipment can monitor the candidates of the control channel by assuming that remaining parameters for configuring the specific CORESET not obtained through the PBCH signal are fixed as follows a size of 1 REG bundle is fixed to 6 REGs, a CCE-to-REG mapping type is fixed to interleaving, a row size of an interleaver for interleaving is fixed to 2, and a precoder granularity which is a unit of the same precoding assumption is fixed to 1 REG bundle.

Abstract: Technology for a transmitter operable to perform data transmissions using low density parity check (LDPC) codes is disclosed. The transmitter can determine soft buffer information (Nsoft) for a receiver. The transmitter can determine a soft buffer partition per HARQ process (NIR) for the UE. The transmitter can obtain, for a transport block, a number of code block segments (C). The transmitter can select a shift size value (z). The transmitter can determine an amount of soft buffer available for the code block segments (Ncb) based on NIR, C, and z. The transmitter can encode the code block segments based on an LDPC coding scheme to obtain encoded parity bits. The transmitter can select a subset of the encoded parity bits based on the determined amount of soft buffer associated with the code block segments.

Abstract: Embodiments of the present disclosure provide an encoding/decoding method, apparatus, and system. The present disclosure is used to improve the decoding performance and improve accuracy of a survivor path. The method includes: encoding information bits to obtain a first-level encoded code word; obtaining a sorting value of each check bit of the first-level encoded code word, and adjusting each check bit to a corresponding position according to the sorting value of each check bit, where the sorting value refers to a value of S when the check bit is related to first S information bits of the information bits in the first-level encoded code word, and S is a non-zero integer; and performing second-level encoding on the first-level encoded code word after positions of the check bits are adjusted, thereby obtaining a second-level encoded code word. The present disclosure is applicable to various communication systems.

Abstract: In a signal generating device 2, first signal generation means 12 for generating a most significant bit signal stream MSB, second signal generation means 13 for generating a least significant bit signal stream LSB, a mask generation means 14 for defining a bit that allows error insertion and a bit that prohibits error insertion with different pieces of bit information, and generating a mask pattern of each of the most significant bit signal stream MSB and the least significant bit signal stream LSB, based on symbol transition information indicating a transition destination of four PAM4 symbols of a PAM4 signal; and error insertion means 15 for inserting an error, based on bit information of the mask pattern corresponding to each bit of the most significant bit signal stream and the least significant bit signal stream designated according to a symbol error rate.

Abstract: This invention presents a method and apparatus for vertical layered finite alphabet iterative decoding of low-density parity-check codes (LDPC) which operate on parity check matrices that consist of blocks of sub-matrices. The iterative decoding involves passing messages between variable nodes and check nodes of the Tanner graph that associated with one or more sub-matrices constitute decoding blocks, and the messages belong to a finite alphabet. Various embodiments for the method and apparatus of the invention are presented that can achieve very high throughputs with low hardware resource usage and power.

Abstract: The present invention discloses a coding and decoding method, apparatus, and system for forward error correction, and pertains to the field of communications. The method includes: determining check matrix parameters of time-varying periodic LDPC convolutional code according to performance a transmission system, complexity of the transmission system, and a synchronization manner for code word alignment, constructing a QC-LDPC check matrix according to the determined check matrix parameters, and obtaining a check matrix (Hc) of the time-varying periodic LDPC convolutional code according to the QC-LDPC check matrix; de-blocking, according to requirements of the Hc, data to be coded, and coding data of each sub-block according to the Hc, so as to obtain multiple code words of the LDPC convolutional code; and adding the multiple code words of the LDPC convolutional code in a data frame and sending the data frame.

Abstract: Methods and apparatuses for coding a codeword. An apparatus for decoding the codeword includes a memory configured to receive the codeword encoded based on a low-density parity check (LDPC) code H-matrix and a two-step lifting matrix and processing circuitry configured to decode the received codeword. An apparatus for encoding the codeword includes memory configured to store information bits to be encoded into the codeword and processing circuitry configured to encode the codeword based on based on a LDPC code H-matrix and a two-step lifting matrix. A code length of the LDPC code H-matrix lifted by the two-step lifting matrix is an integer multiple of 672 bits. The LDPC code block H-matrix may be an IEEE 802.11ad standard LDPC coding matrix. The two-step lifting matrix can be one of a plurality of two-step lifting matrices to generate a family of LDPC codes.

Abstract: A memory device is configured to perform a parallel read-modify-write operation, which generates a syndrome for first partial data read from a memory cell array and second partial data according to a data mask option, corrects an error of the second partial data, generates merged data by combining second data with the corrected second partial data, and generates an internal parity for the merged data. The memory device sets the second partial data to binary values of 0, generates third data by combining the second partial data set to the binary values of 0 with the second data, generates a third parity for the third data, and generates an internal parity for the merged data based on the syndrome, a partial parity, and the third parity.

Abstract: Methods and systems that enable recovery of a lost packet from an incomplete block transmitted over a communication network. In one embodiment, a system includes a first processor configured to: receive a block of packets during a period spanning a certain duration, calculate a parity packet (PP) for the block, and provide in PP an indication of the number of packets in the block, where the block comprises k<n packets, and the certain duration is long enough to enable the processor to receive at least n packets. A transmitter transmits the k packets and PP. A receiver receives, over a period that is not longer than the certain duration, packets sent by the transmitter. A second processor detects, based on the number indicated in PP, that one of the k packets of the block was lost, and utilizes PP to recover said lost packet.

Abstract: One embodiment of an accelerator includes a computing unit; a first memory bank for storing input activations and a second memory bank for storing parameters used in performing computations, the second memory bank configured to store a sufficient amount of the neural network parameters on the computing unit to allow for latency below a specified level with throughput above a specified level. The computing unit includes at least one cell comprising at least one multiply accumulate (“MAC”) operator that receives parameters from the second memory bank and performs computations. The computing unit further includes a first traversal unit that provides a control signal to the first memory bank to cause an input activation to be provided to a data bus accessible by the MAC operator. The computing unit performs computations associated with at least one element of a data array, the one or more computations performed by the MAC operator.

Abstract: A method, system, and apparatus for interleaving data including creating a buffer, writing input data, and reading output data out of the buffer.

Abstract: An identification token of a programmable device is determined whether to be invalid. In response to determining that the identification token is invalid, the programmable device is identified as unauthorized. A parameter associated with the unauthorized programmable device is reported to a programming unit.

Abstract: The inventive concept provides a security device capable of reducing an area of a die required for implementation of a stable PUF by increasing the value of entropy from a predefined number of entropy sources and/or minimizing a blind zone of a validity checking module. The security device uses an asynchronous configuration to minimize a blind zone. In various embodiments of the inventive concept, the blind zone is generated only in a period when a reset signal is at a first logic level. Therefore, it is possible to minimize the blind zone by minimizing a period in which the reset signal is at such logic level. A semiconductor device, semiconductor package, and/or smart card can be provided with such security device, as well as a method for determining a validity of a random signal using a semiconductor security device.