Abstract: An integrated circuit including a capacitance multiplier having reduced parasitics and injected noise compared to conventional multiplier methods. The integrated circuit includes a reference capacitor and a current mirror arrangement coupled to the reference capacitor. The current mirror arrangement, which includes a current gain factor N, varies the capacitance of the reference capacitor by a factor of N+1, based on the reference capacitor current. The current mirror arrangement includes an operational amplifier operating in conjunction with two mirror transistors to form a current mirror arrangement having little or no series resistance. The current mirror also can include a plurality of resistors configured to reduce the noise from the capacitance multiplier, thus making the capacitance multiplier useful for applications that may require relatively low noise.

Abstract: This publication concerns electronics modules comprising at least one first material zone formed of first material which can be structurally transformed by means of electric interaction in order to increase its conductivity at least locally, the first material having a first transformation threshold, and at least one second material zone in the vicinity of the first material zone. According to the invention, the second material zone is formed from second material, which can also be structurally transformed in order to increase its conductivity, the second material having a second transformation threshold, which is lower than the transformation threshold of the first material zone. With the aid of the invention, post-processing electrical programmability and non-volatility of printable memories can be achieved.

Abstract: The present invention discloses an inverter test device and a method thereof, which provides a single-load environment or a multi-load test environment to test electrical performance of an inverter or inverters, including: unbalanced current comparison, phase comparison, current/voltage deviation, and fusion heat (I2T), and record the test results, wherein the test method of the present invention is implemented with the procedures, which can be executed in a computer or a similar device to undertake control and data processing, and the electrical signals acquired by the inverter test device are processed, compared and calculated in order to realize the abovementioned tests of unbalanced current comparison, phase comparison, current/voltage deviation, and fusion heat (I2T).

Abstract: A switched capacitor charge sharing technique for integrated circuit devices which allows for efficient charge sharing and signal level generation of exact desired values, and wherein the signal levels of the circuits sharing the charge do not have to have the same voltage levels. In a particular embodiment of the technique of the present invention disclosed herein, a switched capacitor is used to share charge between, for example, two different signals or two different groups of signals. The size of the capacitor can be adjusted to obtain the required signal level of the various signals.

Abstract: An integrated circuit including a capacitance multiplier having reduced parasitics and injected noise compared to conventional multiplier methods. The integrated circuit includes a reference capacitor and a current mirror arrangement coupled to the reference capacitor. The current mirror arrangement, which includes a current gain factor N, varies the capacitance of the reference capacitor by a factor of N+1, based on the reference capacitor current. The current mirror arrangement includes an operational amplifier operating in conjunction with two mirror transistors to form a current mirror arrangement having little or no series resistance. The current mirror also can include a plurality of resistors configured to reduce the noise from the capacitance multiplier, thus making the capacitance multiplier useful for applications that may require relatively low noise.

Abstract: An integrated circuit including a tunable capacitance multiplier. The integrated circuit includes a reference capacitor and a current source arrangement coupled in parallel to the reference capacitor. The current source arrangement can include a plurality of current sources that are switchably coupled to the reference capacitor in a manner that causes the capacitance of the reference capacitor to vary based on which current sources are coupled thereto. The current sources can be current mirror arrangements of other suitable current sources. The gain factors of the current sources are configured to establish the capacitance variability range and the incremental variance steps therein. In phase-locked loop (PLL) applications, the tunable capacitance multiplier is used to replace the main loop filter capacitor to provide a variable loop bandwidth, thus allowing relatively large values of capacitance to be realized using a relatively small physical capacitor.

Abstract: A semiconductor integrated circuit comprises a logic circuit unit, a signal control unit, a first signal selecting unit to a third signal selecting unit, and a first element electrode to a fourth element electrode. A part of signal lines of the logic circuit unit is connectable to different element electrodes, in accordance with the operating state of the logic circuit unit. The signal control unit generates connection information related to the connection of the signal lines to the element electrodes, thereafter sending the connection information to an external LSI. The connection is made after a retaining period, during which the element electrode concerned is maintained at high impedance, thereby avoiding unexpected failure. According to the present structure, the number of element electrodes required by the semiconductor integrated circuit can be reduced.

Abstract: A controlling circuit for controlling on-off switching of a power supply for a CMOS circuit includes a CMOS circuit (20) and a switch (30). The CMOS circuit includes a first circuit (50) for storing the system time of the computer and a second circuit (70) for storing other system settings of the computer. One terminal of the switch is connected to the first circuit and a power supply (10) in parallel via a resistor (R2). The one terminal of the switch is connected to the second circuit, and another terminal of the switch is connected to ground. When the one terminal of the switch is connected to the another terminal, the data stored in the second circuit is cleared while the system time stored in the first circuit remains.

Abstract: A semiconductor device has the package structure which used the lead frame, a communication device (semiconductor chip) is arranged to the main surface side of a supporting body, and the condenser for firing is arranged to the back side of the opposite side to the main surface of said supporting body. By having such structure, a miniaturization, the reduction of a manufacturing cost, and high reliability of a semiconductor device and an ignition device can be aimed at.

Abstract: An embodiment of an electronic device having a plurality of operative parameters is provided. The electronic device includes means for applying a plurality of trimming actions to each parameter for causing a corresponding correction of the parameter, for at least one reference parameter, means for measuring the reference parameter responsive to the application of at least part of the trimming actions to select one of the trimming actions providing a target value of the reference parameter, and means for forcing the application of the selected trimming action for the reference parameter.

Abstract: A monolithically integratable circuit arrangement is provided, which has at least one inductor, formed as a conductor loop, and at least one capacitor, connected to the conductor loop. According to the invention, the circuit arrangement comprises (a) at least one first conductor loop placed in at least one first metallization level and having a first DC terminal for applying a first DC potential, (b) at least one second conductor loop placed in at least one second metallization level and having a second DC terminal for applying a second DC potential, (c) at least one metal-isolator-metal capacitor with a capacitor plate, which is placed in a third metallization level between the first and second metallization level, and (d) at least one metallic connecting means placed between the capacitor plate and the first conductor loop, said means which connects the capacitor plate in an electrically conducting manner to the first conductor loop.

Abstract: A geometric ladder circuit produces a transfer function having substantially uniform steps measured in dB. Where the ladder has a plurality of substantially identical resistor rungs of a first resistance, one stile that is a conductor connecting the rungs, and another having a series of substantially identical resistors of a second resistance, then for identical currents injected at different rungs, the output signal at an end of the ladder is attenuated by a number of substantially equal steps, one for each rung between input and output. For a ladder with a base rung R, an output at an end opposite the base rung, stile resistors of resistance ?R, and other rungs all of resistance (1+(1/?))R, the step size is 20 log10 (1+?).

Abstract: An integrated circuit providing high equivalent capacitance ranging from a few tens of picofarads to a few nanofarads is presented. The integrated circuit includes active integrated circuit components, requires no external capacitor, and is substantially insensitive to transistor current gain variations. The high capacitance integrated circuit can be advantageously used to provide, for example, timing delay and servo loop compensation.

Abstract: A semiconductor device, has a main transistor that is a first-conductivity-type MOS transistor and has the drain connected to a first potential; a first switch circuit that is connected between the source of said main transistor and a second potential; a dummy transistor that is a first-conductivity-type MOS transistor whose source serves also as the source of said main transistor; and a second switch circuit that is connected between the drain of said dummy transistor and said first potential or said second potential.

Abstract: The invention provides a technique that enables a correct discrimination of reception data, when the supply voltage of a semiconductor integrated circuit having a simultaneous bi-directional interface is decreased. The data transmission system is provided with input circuits constituting a simultaneous bi-directional interface by the number of reference voltages used. Each of the input circuits is supplied with a fixed reference voltage, the input circuit supplied with a higher reference voltage employs a differential amplifier with n-channel MOSFETs served as input differential devices, and the input circuit supplied with a lower reference voltage employs a differential amplifier with p-channel MOSFETs served as input differential devices, in which selectors switch the outputs of the two differential amplifiers in correspondence with the output data of their own. Thus, the system attains the reception data.

Abstract: A monolithic capacitance multiplication circuit serves to reduce the required die area when larger capacitance values are needed such as in filter and loop frequency compensation circuits. A current mirror/cascoding device arrangement reduces the effective series resistance of the multiplier capacitor. As a result, the multiplier topology exhibits improved bandwidth over prior art capacitance multiplier circuits.

Abstract: A structure and associated method of processing data on a semi-conductor device comprising an input island, a processing island, and an output island formed on the semiconductor device. The input island is adapted to accept a specified amount of data and enable a means for providing a first specified voltage for powering the processing island after accepting the specified amount of data. The processing island is adapted to receive and process the specified amount of data from the input island upon powering the processing island by the first specified voltage. The output island is adapted to be powered by a second specified voltage. The processing island is further adapted to transmit the processed data to the output island upon said powering by the second specified voltage. The first specified voltage is adapted to be disabled thereby removing power from processing island upon completion of transmission of the processed data to the output island.

Abstract: According to an embodiment of the present invention, a capacitor comprising field effect transistors and a bias transistor.

Abstract: A data latch circuit includes anti-fuse elements for storing remedy information therein as to replacement of defective memory cells by redundant memory cells. For programming the anti-fuse elements to a logic level “1” in a programming mode, control signals CTL1 and CTL2 are set at a low level and a high level, respectively, and programming control signals PGMA and PGMB are set at a high level and a low level, respectively. A voltage selection node Nvs delivers a programming voltage Vpp, lowering an output terminal RCB to effect dielectric breakdown of anti-fuse element 25, which assumes a low resistance. In a normal operation mode, programming voltages PUMA and PGMB are set at a low level and a high level, respectively, and both control signals CTL1 and CTL2 are set at a low level Voltage output node Nvs delivers the normal operating voltage, raising output terminal RC to a high level to thereby deliver the stored logic level “1”.

Abstract: The invention concerns a control device comprising a circuit generating REF reference voltages (VPOL1, VPOL2) comprising three P-type MOS transistors (M12, M13 and M14) connected in series between a high-voltage input node (EHV) and the earth (GND), and supplying on the drain and the source of the middle transistor (M13) reference voltages (VPOL1, VPOL2). ?Said device comprises means for controlling the reference transistors either, in a first operating mode, to force the first reference transistor (M12) in current source, the second reference transistor (M13) in off-state and short-circuit the third reference transistor (M14) to the earth, or, in a second operating mode, in connecting each of said transistors in diode, their gate and their drain being connected, on the basis of a logic control signal (/WR). Thus, the resulting reference voltages in output are based on said logic signal.

Abstract: To reduce degradation of image quality when constructing anode line drive circuits in a display panel drive circuit from a plurality of IC chips.

Abstract: The invention provides a technique that enables a correct discrimination of reception data, when the supply voltage of a semiconductor integrated circuit having a simultaneous bi-directional interface is decreased. The data transmission system is provided with input circuits constituting a simultaneous bi-directional interface by the number of reference voltages used. Each of the input circuits is supplied with a fixed reference voltage, the input circuit supplied with a higher reference voltage employs a differential amplifier with n-channel MOSFETs served as input differential devices, and the input circuit supplied with a lower reference voltage employs a differential amplifier with p-channel MOSFETs served as input differential devices, in which selectors switch the outputs of the two differential amplifiers in correspondence with the output data of their own. Thus, the system attains the reception data.

Abstract: The well voltage of a CMOS circuit having low-threshold-voltage MOSFETs is controlled when the power supply is turned on, during normal operation, and when the supply voltage is cut off. The CMOS circuit can thus operate stably with lower power consumption, because latching-up is reduced when the supply voltage is applied to the CMOS circuit or when the supply voltage is cut off, and subthreshold current is decreased during normal operation.

Abstract: The present invention relates to a current reference system comprising a selectively activatable high current reference circuit operable to generate a reference calibration circuit when activated and a low current calibrated reference current circuit operable to generate a reference current having a value based upon a control data. The system further comprises a control circuit operable to activate the selectively activatable high current reference circuit during a calibration period. The control circuit is further operable to vary a characteristic of the low current calibrated reference current circuit in a predetermined fashion while comparing another characteristic of the low current calibrated reference current circuit to a predetermined value. The control circuit then identifies a calibration condition based on the comparison, and generates the control data associated therewith.

Abstract: A capacitive multiplier circuit for an integrated circuit includes a capacitor coupled between a first node and a second node. A current source is coupled to provide a controlling current to the second node. A first current path shunts the first node and a second current path shunts the second node. The first current path is a first transistor having its conductance path connected between the first node and the substrate and its control electrode connected to the first node. The second current path is a second transistor having its conductance path connected between the second node and the substrate and its control electrode connected to the first node. The current ratio between the two current paths will be determined by the relative areas of the respective conductance paths.

Abstract: In a smartcard having a subscriber identity module ("SIMI") that cooperates with a mobile station to effect communication with a telecommunications network, a system for, and method of, disabling the smartcard. The system includes: (1) data commnications circuitry that transmits a code uniquely identifying the smartcard from logic circuitry within the smartcard to the telecommunications network via the mobile station, the code employable by the telecommunications network to search a disable database associated therewith, the telecommunications network returning a disable command if the code is found in the disable database and (2) disabling circuitry that incapacitates the logic circuitry to prevent an operation thereof, the smartcard being incapacitated with respect to the telecommunications network and systems independent of the telecommunications network.

Abstract: Substituted compounds having relatively large molecular first order hyperpolarizabilities are provided, along with devices and materials containing them. In general, the compounds bear electron-donating and electron-withdrawing chemical substituents on a polyheterocyclic core.

Abstract: A method of designing improved CMOS input circuits by understanding and selecting appropriate drive strength for a CMOS output from a previous stage. The method involves modeling the net using HSPICE and including a transit time term to accurately model charge storage, then size drivers as needed to keep the V.sub.ss clamps out of forward conduction. Excessive ringing can cause data errors in the input stage if unterminated, falling edge transitions in such a net can turn on a receiver's V.sub.ss clamp diode (stored charge in the V.sub.ss clamp diode combined with the line's inductance and the receiver's capacitance form an energized resonant circuit which can release energy at a time to cause a data glitch). Currently, XNS simulation miscalculates the ring amplitude by a factor of three. Driver scaling and termination can eliminate the problem by keeping the receiver's V.sub.ss clamp out of forward conduction. Driver sizing can control the problem.

Abstract: A device for multiplying a capacitance by a variable coefficient, for example for adjusting a cut-off frequency of a filter, includes a current amplifier for amplifying a current flowing through said capacitance. The capacitance is floating between first and second predetermined points. The current amplifier circuit includes a differential current amplifier.

Abstract: A method and an apparatus for providing an adjustable floating capacitance between a first node and a second node in an integrated circuit. First and second transistors having commonly coupled gates are coupled between the input and output nodes of a digitally-adjustable floating MOS capacitor. The source and drain of the first transistor are coupled to the input node, while the source and drain of the second transistor are coupled to the output node. A switch responsive to an enable signal is coupled to the gates of the first and second transistors. In response to the enable signal, the switch alternatively couples the gates of the first and second transistors to either a first potential or a second potential. When the gates of the first and second transistors are coupled to the first potential, a first capacitance is realized between the input and output nodes.

Abstract: A simple circuit arrangement for amplifying the effect of a capacitance. The input of the circuit arrangement is connected to an output of a current mirror circuit and, via the capacitance, to an input of the current mirror circuit to which a constant current (I) of known magnitude is applied. The degree of amplification of the effect of the capacitance is dependent on the area ratio n between the input transistor and the output transistor of the current mirror circuit. A constant current (n.multidot.I) is applied to the output of the current mirror circuit and is equal to the current applied to the input of the current mirror circuit multiplied by the area ratio n.

Abstract: A common dictionary definition of a "diode" is "any electronic device that restricts current flow chiefly to one direction." This definition covers not only the conventional two lead PN junction semiconductor device presently known in the prior art (referred to herein as a "conventional diode") but also the electronic device of this invention (referred to herein as a "low power diode"). A low power diode has a comparator for comparing the voltage present at the anode and cathode of the diode. When the comparator determines that the voltage present at the anode of the low power diode equals or exceeds the voltage present at the cathode of the low power diode by a predetermined forward voltage, a signal is generated. This signal turns on a transistor acting as a switch, which in turn electronically connects the anode and the cathode of the low power diode together. Unlike conventional diodes that have a forward voltage (dependent on the physical silicon junction property of the diode) of approximately 0.

Abstract: A variable impedance circuit includes a differential circuit, an impedance element, a variable current attenuator and a pair of level shifters. The differential circuit includes a transistor pair with a pair of input terminals, a pair of output terminals, and a pair of emitters. The impedance element is connected between the emitters of the transistor pair. The variable current attenuator has a pair of input terminals connected respectively to the output terminals of the transistor pair, a pair of output terminals, and a pair of control inputs for receiving a control voltage to vary the current gain of the variable current attenuator. Each of the level shifters has an input terminal connected to a respective one of the output terminals of the variable current attenuator, and an output terminal connected to a respective one of the input terminals of the transistor pair. The level shifters ensure that the transistor pair and the variable current attenuator are properly biased.

Abstract: The invention relates to an integrated circuit including impedances having precise values. To compensate for process variations and drift in impedances, the circuit includes automatic control means (3) to adjust the value of impedances (R) to a value that is a function of that of a reference impedance (Rc) external to the integrated circuit.

Abstract: A resistor ladder (10) includes a plurality of series resistors (16,18,20,22,24,26,28) connected in series with each other between a first terminal (12) and a second terminal (14). A plurality of shunt resistors (60,62,64,66, 68,70) are connected between junctions (48,50,52,54,56) of adjacent series resistors and the second terminal (14). The series resistors (16,18,20,22,24,26,28) and shunt resistors (60,62,64,66,68,70) are formed on a substrate (80) as film resistors which blow open at a predetermined current density. The shunt resistors (60,62,64,66,68,70) have a smaller cross-sectional area than the series resistors (16,18,20,22,24,26,28) such that they successively blow open from the first terminal (12) toward the second terminal (14), while the series resistors (16,18,20,22,24,26,28) do not blow open, as a progressively increasing voltage is applied between the first terminal (12) and the second terminal (14).