Abstract: A semiconductor apparatus may include a plurality of through-semiconductor chip lines which pass through a plurality of stacked semiconductor chips. An uppermost semiconductor chip among the plurality of stacked semiconductor chips is configured to transfer its internal information signal to an assigned corresponding through-semiconductor chip line, and at least one semiconductor chip other than the uppermost semiconductor chip is configured to logically combine respective internal information signals transferred through through-semiconductor chip lines and their internal information signals and sequentially transfer resultant signals to assigned corresponding through-semiconductor chip lines. The at least one semiconductor chip other than the uppermost semiconductor chip logically combines the internal information signals transferred through the through-semiconductor chip lines from adjoining semiconductor chips and its internal information signals.

Abstract: An electrical circuit for emulating a capacitance, comprises a physical capacitor which is charged by charge flow from the input of the electrical circuit. An amplifier amplifies the voltage at the input of the electrical circuit such that the physical capacitor is charged with a larger change in voltage than the change in voltage at the input. This implements an effective multiplication of capacitance. A reset system resets the physical capacitor without drawing charge from the input of the electrical circuit. This extends the voltages which can be provided to the input.

Abstract: A pin sharing method for controlling a plurality of functions of a chip via a versatile pin of the chip is disclosed. The pin sharing method includes dividing a voltage range of the versatile pin into a plurality of sections according to the plurality of functions, and assigning the plurality of sections to correspond to a plurality of modes of the plurality of functions.

Abstract: In a process automation controller, a universal digital input module is provided. The universal digital input module comprises a plurality of digital input channels, each channel to sink a first current at a first voltage level associated with an input having a digital high value and to sink a second current at a second voltage level associated with the input having a digital high value, wherein the first current is greater than the second current and wherein the first voltage is less than the second voltage.

Abstract: An analog input device including a scanning circuit including a first insulation transformer insulating an analog signal inputted from a thermocouple, a power supply section charging a test voltage used for disconnection detection of the thermocouple, a second insulation transformer in which the scanning circuit and the power supply section are connected in parallel, and a control circuit for outputting a pulse signal to be inputted to the second insulation transformer. The second insulation transformer insulates and transfers a drive pulse for switching the scanning circuit and a power supply pulse for feeding power to the power supply section. The control circuit carries out a timing control so that the drive pulse and the power supply pulse are not outputted at the same time. Accordingly, an insulation transformer for application of a test voltage is not required, and thus the total number of the components is reduced to a great extent and reductions in costs and size thereof are realized.

Abstract: A matrix of explosive cells can include plural explosive cells formed in an array in a common substrate. Each cell can be formed as a recess filled with explosive material. An ignition device has an addressable ignition source for each cell. This matrix can be used in combination with a projectile guidance system. The projectile guidance system includes an antenna, a transceiver and a control processor. A method of guiding a projectile can include firing a projectile at a target, tracking the projectile and the target, determining a desired change in a flight path of the projectile, transmitting guidance commands to effect the desired change in the projectile's flight path to the projectile, receiving the guidance commands onboard the projectile and selectively igniting an explosive cell in a matrix of addressable explosive cells contained in a common substrate using the guidance commands.

Abstract: A circuit device includes an option pad, a first power source pad, and a first ground pad, wherein the option pad, the first power source pad, and the first ground pad are formed over various portions of a top surface of the circuit device, and a function of the circuit device is determined by coupling the option pad with one of the first power source pad and the first ground pad through a wire bond.

Abstract: This document discusses, among other things, an audio jack detection circuit configured to be coupled to an audio jack receptacle of an external device. The audio jack detection circuit configured to receive to receive audio jack receptacle information, to disable an oscillator when the audio jack receptacle information indicates that the audio jack receptacle is empty, and to enable the oscillator when the audio jack receptacle information indicates that the audio jack receptacle includes an audio jack.

Abstract: An embodiment of an electrically trimmable electronic device, wherein a resistor of electrically modifiable material is formed by a first generally strip-shaped portion and by a second generally strip-shaped portion, which extend transversely with respect to one another and are in direct electrical contact in a crossing area. The first and second portions have respective ends connected to own contact regions, coupled to a current pulse source and are made of the same material or of the same composition of materials starting from a same resistive layer of the material having electrically modifiable resistivity, for example, a phase-change material, such as a Ge—Sb—Te alloy, or polycrystalline silicon, or a metal material used for thin-film resistors. The trimming is performed by supplying a trimming current to the second portion so as to heat the crossing area and modify the resistivity thereof, without flowing longitudinally in the first portion.

Abstract: A monolithic power switch provides a semiconductor layer, a three dimensional FET formed in the semiconductor layer to modulate currents through the semiconductor layer, and a toroidal inductor with a ceramic magnetic core formed on the semiconductor layer around the FET and having a first winding connected to the FET.

Abstract: Provided are a data selection circuit, a data transmission circuit, a ramp wave generation circuit, and a solid-state imaging device. A delay section delays signals input to delay units of n (n is a natural number equal to or more than 3) stages that are connected to each other and have the same configuration and outputs delayed signals from the delay units. A delay control section controls a delay amount of the delay units. An output section performs a logical operation on signals output from i-th and j-th (i and j are natural numbers that are different from each other and equal to or more than 1 and equal to or less than n) delay units to generate a signal and outputs the signal to a k-th (k is a natural number equal to or more than 1 and equal to or less than m) first data selection pulse input terminal of a functional circuit having m (m is a natural number equal to or more than 2) first data selection pulse input terminals.

Abstract: An amplifier comprises a power source, a load network comprising a load and a resonance circuit, an input branch having a first end electrically coupled to the power source and a second end electrically coupled to the load network, and an active switch having one terminal electrically coupled to the second end of the input branch. The input branch including at least one parallel-LC-circuit configured to provide an infinitely large impedance at harmonics of a determined order.

Abstract: A device comprising both a box containing an electronic central unit, and power supply module connected to the central unit. The device also includes an external power supply block connected to the module by an electric cable and provided with both a connection member for connection to a power supply network delivering AC power and a data signal superposed thereon. A converter is provided for converting the AC power. The box includes a carrier current data transmission module, the converter being connected to the connection member and to the electric cable via a first diverter member that extracts and diverts the data signal relative to the converter. The module is connected to the electric cable by a second diverter member for separating the converted power supply current and the data signal and for bringing the power supply current to the power supply module and the data signal to the transmission module.

Abstract: A control circuit comprising an input-output unit that is connected to a signal line, which is connected to an external apparatus, and which is connected to a resistor that is one of a pull-up resistor and a pull-down resistor; a switching unit that switches a mode of the input-output unit to one of an input mode and an output mode, wherein the output mode includes an on-voltage output mode and an off-voltage output mode; an acquisition unit that acquires information regarding whether the resistor connected to the signal line is the pull-up resistor or the pull-down resistor, when the input-output unit is in the input mode; and a control unit that controls the input-output unit to switch to one of the on-voltage output mode and the off-voltage output mode based on the acquisition information acquired by the acquisition unit, when the input-output unit is in the output mode.

Abstract: An arrangement scheme for a power/ground (P/G) network of an integrated circuit is provided. Rows of standard cells in the integrated circuit are horizontally arranged. The P/G network has horizontal and vertical metal lines arranged in different metal layers. The horizontal metal lines have horizontal power metal lines and horizontal ground lines. The vertical metal lines have vertical power metal lines and vertical ground lines. The power lines and the ground lines in the horizontal metal lines are respectively interconnected with the power lines and the ground lines of the vertical metal lines. The width of the horizontal metal wires in the P/G network is such that the horizontal power metal lines only cover the power lines in the rows of the standard cells, while the horizontal ground metal lines only cover the ground lines of the rows of the standard cells.

Abstract: An embodiment of an electronic device having a plurality of operative parameters is provided. The electronic device includes means for applying a plurality of trimming actions to each parameter for causing a corresponding correction of the parameter, for at least one reference parameter, means for measuring the reference parameter responsive to the application of at least part of the trimming actions to select one of the trimming actions providing a target value of the reference parameter, and means for forcing the application of the selected trimming action for the reference parameter.

Abstract: A voltage-controlled semiconductor inductor and method is provided. According to various embodiments, the voltage-controlled inductor includes a conductor configured with a number of inductive coils. The inductor also includes a semiconductor material having a contact with at least a portion of at least one of the coils. The semiconductor material is doped to form a diode with a first doped region of first conductivity type, a second doped region of second conductivity type, and a depletion region. A voltage across the diode changes lengths of the first doped region, the second doped region and the depletion region, and adjacent coils in contact with at least one of the doped regions are electrically shorted, thereby varying the inductance of the inductor. In various embodiments, the inductor is electrically connected to a resistor and a capacitor to provide a tunable RLC circuit. Other aspects and embodiments are provided herein.

Abstract: A semiconductor apparatus having a plurality of stacked chips includes: a through silicon via (TSV) configured to couple the plurality of chips together and configured to be coupled in series to a plurality of voltage drop units; a plurality of signal conversion units, each of which is configured to convert a voltage outputted from the voltage drop unit of the corresponding one of the plurality of chips to a digital code signal and provide the digital code signal as chip identification signal of the corresponding one of the plurality of chips; and a plurality of chip selection signal generating units, each of which is configured to compare the chip identification signal with a chip selection identification signal to generate a chip selection signal of the corresponding one of the plurality of chips.

Abstract: A semiconductor apparatus having a plurality of stacked chips includes: a plurality of latch units, each of which is disposed in a corresponding one of the plurality of chips and is configured to latch a clock signal and a frequency-divided signal at mutually different points of time to generate an chip identification signal of the corresponding one of the plurality of chips; and a plurality of chip selection signal generating units, each of which is disposed in the corresponding one of the plurality of chips and is configured to compare the chip identification signal of the corresponding one of the plurality of chips with a chip selection identification signal to generate a chip selection signal of the corresponding one of the plurality of chips, wherein the chip selection signal is configured to enable the corresponding one of the plurality of chips when the chip identification signal matches the chip selection identification signal.

Abstract: A reconfigurable number of at-speed pulses and reconfigurable dead cycles between pulses is utilized to enhance test coverage of an Integrated Circuit. A reconfigurable number of programmable at-speed phase-locked loop clock pulses without a dead cycle is emitted through an integrated circuit. Further, a plurality of programmable at-speed phase-locked loop clock pulses is emitted through the Integrated Circuit such that a reconfigurable number of dead cycles is between the plurality of programmable at-speed phase locked loop clock pulses. In addition, data associated with the reconfigurable number of programmable at-speed phase-locked loop clock pulses is capture. Finally, data associated with the reconfigurable number of dead cycles is captured.

Abstract: An aging detection circuit is disclosed. An aging detection circuit may include at least an inverter and a half-latch. During a power-up sequence, if an input voltage of the first inverter changes sufficiently to cause the output of the inverter to change states, the output of the half-latch may be set to a state indicating aging of the circuit. This indication may be used in determining whether or not a supply voltage should be changed to compensate for the aging. A first transistor of the inverter may be arranged such that it remains active subsequent to power-up of the circuit. When active, the first transistor may be subject to degradation mechanisms associated with aging and which change its threshold voltage. The threshold voltage may change such that on a successive power-ups of the circuit, the first transistor is at least momentarily deactivated, leading to the setting of the state indicating aging by the half-latch circuit.

Abstract: A system and method is disclosed for providing a plurality of hardware performance monitors for adaptive voltage scaling in an integrated circuit system that comprises a plurality of clock domains. Each hardware performance monitor is associated with one of the plurality of clock domains and provides a signal that measures a performance of its respective clock domain temperature, process corner and supply voltage. The difference between the measured performance and a nominal expected performance for each hardware performance monitor is determined. The largest of the plurality of difference signals is selected and used in an advanced power controller to provide adaptive voltage scaling for the integrated circuit system.

Abstract: A differential amplifier circuit receives a pair of input signals to develop an output signal. First and second MOS transistors have commonly-connected gates and sources. A third MOS transistor has a drain connected to the commonly-connected gates, and a source connected to the first MOS transistor's drain. The third MOS transistor's gate is connected to a constant voltage source. A constant current source is connected to the third MOS transistor's drain. A first terminal, connected to the first MOS transistor's drain and to the third MOS transistor's source, provides an input current. A second terminal, connected to the first and second MOS transistors' commonly-connected sources, provides a common reference. A third terminal, connected to the second MOS transistor's drain, provides an output current.

Abstract: An integrated circuit (IC) including a controller integrally formed on a shared die with the IC and method of operating the same to compensate for process and environmental variations in the IC are provided. In one embodiment the IC is comprised of device and sub-circuits, and the method includes: receiving in the IC electrical power and information on at least one of one or more operational parameters of the IC; and adjusting one or more operating characteristics of at least one of the devices and sub-circuits in the IC based on the received information using a controller integrally formed on a shared die with the IC. Other embodiments are also disclosed.

Abstract: an electrical device that includes a first electrode and a second electrode that are separated from one another so as to form a gap structure. A layer of protective material spans the gap structure to contact the first electrode and the second electrode. A dimension of the gap structure, corresponding to a separation distance between the first electrode and the second electrode, is varied and includes a minimum separation distance that coincides with a critical path of the layer of protective material between the first electrode and the second electrode.

Abstract: An internal voltage adjusting circuit of a semiconductor memory device processes a period from activation to deactivation of a reset bar signal by dividing the period into a first period to a third period. In the first period, a peripheral circuit voltage is stabilized to a lowest value to suppress power consumption. In the second period in which a power source voltage is stabilized, the peripheral circuit voltage is set to a highest value to read out optimum internal voltage values from a fuse circuit in a stable manner. In the third period after reading out the optimum internal voltage values, the peripheral circuit voltage is returned to the lowest value to suppress the power consumption. When the reset bar signal is deactivated, the peripheral circuit voltage is set based on the optimum internal voltage values read out from the fuse circuit.

Abstract: A system and method for controlling an IC in different operational modes involves automatically loading operational configurations of target circuitries in the IC for a determined operational mode into at least one register and operating the target circuitries in the IC according to the operational configurations that are automatically loaded into the at least one register.

Abstract: An integrated circuit and a related method for determining an operation mode are disclosed. The exemplified integrated circuit includes a controller, a multi-function pin, and a mode determination circuit. The controller controls a power switch and is being set to operate in one of the operation modes including a first operation mode and a second operation mode. The multi-function pin is connected to an external resistor. The mode determination circuit detects a signal from the multi-function pin. The signal represents the resistance of the external resistor. If the resistance is within a first range, the controller is operated in the first operation mode. If the resistance is within a second range, the controller is operated in the second operation mode.

Abstract: An integrated circuit includes a first storage location, a first generator, a converter, and a second generator. The first storage location is operable to store a first adjustment value. The first generator is coupled to the first storage location, is operable to generate a first signal having a first characteristic, and includes a first adjuster operable to change the first characteristic in response to the first adjustment value. The converter is coupled to the first storage location and is operable to generate from the first adjustment value a modified adjustment value. The second generator is coupled to the converter, is operable to generate a second signal having a second characteristic, and includes a second adjuster operable to change the second characteristic in response to the modified adjustment value.

Abstract: Techniques are generally described for selecting input vectors that reduce or minimize leakage current for a plurality of integrated circuits (ICs) with the same design, but that differ due to manufacturing variability. In various embodiments, the techniques include determining at least one starting input vector that reduces leakage current in a respective one of N instances of the ICs, and selecting from the determined at least one starting input vector of each respective one of the N instances, a set R of representative input vectors. Some of the embodiments then use each of the representative input vectors in the set R to determine at least a particular input vector to apply to input terminals of an IC in the plurality of ICs to reduce or minimize leakage current in the IC. Additional variants and embodiments may also be disclosed.

Abstract: A capacitance interface circuit is provided. An external inductive capacitor is divided into a variable portion and an invariable portion. The capacitance of an internal adjustable capacitor is designed to be equal or close to the fixed capacitance of the external inductive capacitor. The internal adjustable capacitor is used for storing charges having a polarity opposite to that of the invariable portion of the external inductive capacitor in order to neutralize the effect of the invariable portion of the external inductive capacitor. Thus, a charge converter composed of a fully-differential amplifier and feedback capacitors needs only work on the variable portion of the external inductive capacitor, and accordingly the accuracy in subsequent data processing is increased.

Abstract: A signal analysis control system is provided with a signal analyzing section for analyzing signals inputted to a transmission section and generating analysis information, and a signal control section for controlling signals inputted to a receiving section by using the analysis information.

Abstract: The present invention relates to a LIN receiver having sleep/wake-up functionality, which has an input (LINI) to a LIN bus (LIN), an output (RXDO), terminals for at least one supply voltage (BVDD), and transistors (M1 through M17), the transistors (M1 through M17) being switched to activate the receiver in the recessive state of the LIN bus via a state change on the LIN bus into an active state of the receiver. In particular, the input (LINI) is connected between components of a voltage-to-current converter (SSW), in particular between a first and a second resistors, (R2, R2).

Abstract: An electronic device includes a cascade of a plurality of transistors. Each transistor of the cascade receives an input voltage at a first terminal of its source/drain channel and receives a sampling clock signal at a control gate. The second terminal of the source/drain path of a first transistor drives a sampling capacitor. The second terminal of the source/drain channel of each subsequent transistor is connected to a backgate of a previous transistor. The backgate of the last transistor is connected to a supply voltage level. The second terminals of the subsequent transistors may be connected to corresponding buffer capacitors. The backgate of the last transistor may be supplied with the input during sampling and the supply voltage level at other times.

Abstract: The negative voltage generating device includes a current interrupting controller, a voltage generating controller, and a negative voltage generator. The current interrupting controller outputs a current interrupting control signal in response to a control signal, which is enabled during the application of a power-up signal. The voltage generating controller compares a first reference voltage to a feedback voltage in response to the current interrupting control signal and outputs a voltage generating control signal. The negative voltage generator generates the feedback voltage and a second negative voltage by receiving the first negative voltage in response to the voltage generating control signal.

Abstract: A multi-function chip including a circuit and at least one control circuit is provided. The circuit having multiple functions includes an interconnection. The interconnection has at least one resistance-variable segment. The control circuit is electronically connected to the resistance-variable segment. One of the functions is carried out by adjusting the resistance of the resistance-variable segment with the control circuit.

Abstract: A semiconductor device used as an ID chip is provided, of which operation is terminated when its role is finished or expires. According to the invention, an antenna circuit, a voltage detecting circuit, a current amplifier circuit, a signal processing circuit, and a fuse are provided over an insulating substrate. When large power is applied to the antenna circuit, a voltage is detected by voltage detecting circuit and a corresponding current is amplified by the current amplifier circuit, thereby the fuse is melted down. Also, when an anti-fuse is used, the anti-fuse can short an insulating film by applying an excessive voltage. In this manner, the semiconductor device has a function for making it invalid by stopping operation of the signal processing circuit when the role of the device is finished or expires.

Abstract: In an embodiment, a circuit is disclosed comprising a circuit portion coupled to a terminal and a calibration circuit portion coupled to said terminal.

Abstract: A method of accessing electronic memory is provided in electronic circuits where it is desired to lower power consumption and hence there is no active oscillator at the time when access to data within the electronic memory is required. The invention provides a method therefore for accessing the electronic memory from a controller, which generates its own clock signals from a data, communications bus electrically coupled to the controller. Advantageously the method allows for memory access to be continued in integrated circuits where a subset of circuits are powered down to reduce power consumption, and one of the subset of circuits is an oscillator.

Abstract: The present invention optimizes the performance of integrated circuits by adjusting the circuit operating voltage using feedback on process/product parameters. To determine a desired value for the operating voltage of an integrated circuit, a preferred embodiment provides for on-wafer probing of one or more reference circuit structures to measure at least one electrical or operational parameter of the one or more reference circuit structures; determining an adjusted value for the operating voltage based on the measured parameter; and establishing the adjusted value as the desired value for the operating voltage. The reference circuit structures may comprise process control monitor structures or structures in other integrated circuits fabricated in the same production run. In an alternative embodiment, the one or more parameters are directly measured from the integrated circuit whose operating voltage is being adjusted.

Abstract: A process and apparatus for configuring one or more integrated circuits within a device in a manufacturing process is described. In an exemplary process, a device is manufactured by assembling a chip onto a board such as a printed circuit substrate and the chip is fused from power routed across the board to the chip. The power source for the fusing can be generated from the internal power supply on the board or received on a test point on the board itself or a connection interface (e.g. a USB interface) coupled to the board. In an exemplary apparatus, a device comprises a chip with a plurality of fuses that are used to configure the device and a board coupled to the chip, with the board capable of routing power from the board to the chip and the power is used to blow one or more of the plurality of fuses.

Abstract: At least one embodiment of the invention specifies a current-sensing apparatus and/or a method for its operation which is based on the current sensor provided being a GMR sensor in the form of a gradient sensor and on the gradient sensor, or a component which includes this gradient sensor, itself including a conductor section of a compensating circuit. As such, the current in the measurement circuit can be compensated for by a current in the compensating circuit and the compensating current can be evaluated as a measure of the electrical variable to be detected for the measurement circuit.

Abstract: An integrated circuit comprises an output terminal to be coupled to a non-linear circuit element, an output circuit coupled to the output terminal, the output circuit being configured to supply an operating signal to the non-linear circuit element, a measuring circuit coupled to the output terminal, the measuring circuit being configured to sense on the output terminal a signal value outside an operating regime of the non-linear circuit element, and a control circuit coupled to the measuring circuit, the control circuit being configured to configure at least one function of the integrated circuit on the basis of the signal value sensed by the measuring circuit.

Abstract: A capacitance multiplier circuit is configured to sense a current through a capacitor in an RC filter of the circuit and to multiply the current so as to achieve a capacitance multiplier effect without adding additional circuitry or requiring additional power. The circuit includes an RC filter, a first signal path connected to a filter output, and a second signal path connected to an input to the filter. A current output through the filter (iout) is split between the two paths, sensed in the first path and multiplied in the second path. The multiplied current is fed back from the second path to the filter input to raise the effective capacitance of capacitor C. The capacitance multiplier circuit, in raising the effective capacitance of the capacitor in the filter, does not affect the frequency response, linearity performance and/or stability of the overall circuit.

Abstract: A capacitance multiplier circuit is configured to sense a current through a capacitor in an RC filter of the circuit and to multiply the current so as to achieve a capacitance multiplier effect without adding additional circuitry or requiring additional power. The circuit includes an RC filter, a first signal path connected to a filter output, and a second signal path connected to an input to the filter. A current output through the filter (iout) is split between the two paths, sensed in the first path and multiplied in the second path. The multiplied current is fed back from the second path to the filter input to raise the effective capacitance of capacitor C. The capacitance multiplier circuit, in raising the effective capacitance of the capacitor in the filter, does not affect the frequency response, linearity performance and/or stability of the overall circuit.

Abstract: A method and circuit for implementing Efuse sense amplifier verification, and a design structure on which the subject circuit resides are provided. A first predefined resistor value is sensed relative to a reference resistor. A second predefined resistor value is sensed relative to a reference resistor. Responsive to identifying a respective sense amplifier output resulting from the sensing steps of an unblown eFuse and a blown eFuse, valid operation of the sense amplifier is identified.

Abstract: A tuning circuit element for a tuning circuit. The tuning circuit element may include sub-elements for generating circuit values depending on logical values of digital control input signals. The tuning circuit element may be implemented with varactors, current sources, and other components or circuits. The tuning circuit element may be configured to have fine tuning resolution that is not necessarily limited by minimum feature size of a given fabrication process technology.

Abstract: A geometric ladder circuit produces a transfer function having substantially uniform steps measured in dB. Where the ladder has a plurality of substantially identical resistor rungs of a first resistance, one stile that is a conductor connecting the rungs, and another having a series of substantially identical resistors of a second resistance, then for identical currents injected at different rungs, the output signal at an end of the ladder is attenuated by a number of substantially equal steps, one for each rung between input and output. For a ladder with a base rung R, an output at an end opposite the base rung, stile resistors of resistance ?R, and other rungs all of resistance (1+(1/?))R, the step size is 20 log10(1+?).

Abstract: A differential pair circuit includes a first transistor having a first control terminal, a first input terminal, and a first output terminal; a second transistor having a second control terminal, a second input terminal, and a second output terminal, a first buffer stage including a third transistor having a third control terminal, a third input terminal, and a third output terminal; and a second buffer stage including a fourth transistor having a fourth control terminal, a fourth input terminal, and a fourth output terminal. The first output terminal and the second output terminal are electrically connected; the third output terminal and the first control terminal are electrically connected; the fourth output terminal and the second control terminal are electrically connected; the first input terminal and the fourth input terminal are electrically connected; and the second input terminal and the third input terminal are electrically connected.

Abstract: An integrated physical layer (PHY) and powered device (PD) chip for use in a Power over Ethernet (PoE) system is provided. Embodiments reduce circuit size and cost and enable improved and novel PoE applications. Embodiments include one or more of a PHY circuit, a PD controller circuit, a DC-DC converter circuit, and an enterprise Internet Protocol (IP) circuit, integrated within a single integrated circuit (IC) chip. Embodiments are implemented using a floating ground design. Embodiments can be implemented using a mixed-voltage or a “voltage island” design or using a multi-die scheme.