Abstract: Apparatus and methods are disclosed that enable writing data on, and reading data of, multi-state elements having greater than two states. The elements may be made of magnetoplastic and/or magnetoelastic materials, including, for example, magnetic shape-memory alloy or other materials that couple magnetic and crystallographic states. The writing process is preferably conducted through the application of a magnetic field and/or a mechanical action. The reading process is preferably conducted through atomic-force microscopy, magnetic-force microscopy, spin-polarized electrons, magneto-optical Kerr effect, optical interferometry or other methods, or other methods/effects. The multifunctionality (crystallographic, magnetic, and shape states each representing a functionality) of the multi-state elements allows for simultaneous operations including read&write, sense&indicate, and sense&control.

Abstract: A power up detection system for a memory device. Two rows of memory cells are mask programmed to include a word of data having an arbitrary size. The word in the second row is a single-bit shifted version of the word in the first row, such that each bit is shifted one bit position in a predetermined direction. The bits of the first word are read from the first row into slave latches of the register stages of a data register, and then shifted into the master latches of the next register stage of the data register. The bits of the second word are read from the second row into the slave latches of the register stages. Data comparison logic compares data stored in the master and slave latches of each register stage, and provides a signal indicating matching data between the first latches and the second latches, thereby indicating successful power up of the memory device.

Abstract: A microelectronic programmable structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying a bias across the electrodes, and thus information may be stored using the structure.

Abstract: The various embodiments of the invention relate generally to semiconductors and memory technology. More specifically, the various embodiment and examples of the invention relate to memory devices, systems, and methods that protect data stored in one or more memory devices from unauthorized access. The memory device may include third dimension memory that is positioned on top of a logic layer that includes active circuitry in communication with the third dimension memory. The third dimension memory may include multiple layers of memory that are vertically stacked upon each other. Each layer of memory may include a plurality of two-terminal memory elements and the two-terminal memory elements can be arranged in a two-terminal cross-point array configuration. At least a portion of one or more of the multiple layers of memory may include an obfuscation layer configured to conceal data stored in one or more of the multiple layers of memory.

Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

Abstract: Optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit an array of conductive regions; and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a method of forming a nanocrystalline film includes fabricating a plurality of nanocrystals having a plurality of first ligands attached to their outer surfaces; exchanging the first ligands for second ligands of different chemical composition than the first ligands; forming a film of the ligand-exchanged nanocrystals; removing the second ligands; and fusing the cores of adjacent nanocrystals in the film to form an electrical network of fused nanocrystals.

Abstract: A hybrid memory system having electromechanical memory cells is discussed. A memory cell core circuit has an array of electromechanical memory cells, in which each cell is a crossbar junction at least one element of which is a nanotube or a nanotube ribbon. An access circuit provides array addresses to the memory cell core circuit to select at least one corresponding cell. The access circuit is constructed of semiconductor circuit elements.

Abstract: The various embodiments of the invention relate generally to semiconductors and memory technology. More specifically, the various embodiment and examples of the invention relate to memory devices, systems, and methods that protect data stored in one or more memory devices from unauthorized access. The memory device may include third dimension memory that is positioned on top of a logic layer that includes active circuitry in communication with the third dimension memory. The third dimension memory may include multiple layers of memory that are vertically stacked upon each other. Each layer of memory may include a plurality of two-terminal memory elements and the two-terminal memory elements can be arranged in a two-terminal cross-point array configuration. At least a portion of one or more of the multiple layers of memory may include an obfuscation layer configured to conceal data stored in one or more of the multiple layers of memory.

Abstract: Optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit an array of conductive regions; and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a method of forming a nanocrystalline film includes fabricating a plurality of nanocrystals having a plurality of first ligands attached to their outer surfaces; exchanging the first ligands for second ligands of different chemical composition than the first ligands; forming a film of the ligand-exchanged nanocrystals; removing the second ligands; and fusing the cores of adjacent nanocrystals in the film to form an electrical network of fused nanocrystals.

Abstract: In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter having an input and an output. A first resistor is coupled between the output of the first inverter and the input of the second inverter. A second resistor is coupled between the output of the second inverter and the input of the first inverter. A first write transistor is coupled to the output of the first inverter and has a gate coupled to a source of a first set of write-control signals and a second write transistor is coupled to the output of the second inverter and has a gate coupled to said source of a second set of write-control signals. Finally, a pass transistor has a gate coupled to the output of on of the first and second inverters.

Abstract: The present invention relates to a micro-electromechnical system (MEMS) and, more particularly, to an electrostatic actuator, and a driving method thereof and an application device thereof. The electrostatic actuator in accordance with the present invention comprises a fixed electrode, an electric charge charging unit electrically insulated from the fixed electrode, and a moving electrode spaced apart from the fixed electrode and the electric charge charging unit. In accordance with the present invention, the electrostatic actuator with a very low driving voltage and an arbitrarily controllable driving voltage when compared with a conventional electrostatic actuator is provided. In addition, the electrostatic actuator having durability against external noise and enabling a reliable consecutive operation is provided.

Abstract: Optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit an array of conductive regions; and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a method of forming a nanocrystalline film includes fabricating a plurality of nanocrystals having a plurality of first ligands attached to their outer surfaces; exchanging the first ligands for second ligands of different chemical composition than the first ligands; forming a film of the ligand-exchanged nanocrystals; removing the second ligands; and fusing the cores of adjacent nanocrystals in the film to form an electrical network of fused nanocrystals.

Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

Abstract: Optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit an array of conductive regions; and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a method of forming a nanocrystalline film includes fabricating a plurality of nanocrystals having a plurality of first ligands attached to their outer surfaces; exchanging the first ligands for second ligands of different chemical composition than the first ligands; forming a film of the ligand-exchanged nanocrystals; removing the second ligands; and fusing the cores of adjacent nanocrystals in the film to form an electrical network of fused nanocrystals.

Abstract: To increase the quantity of stored charges of memory cells by a simple configuration to improve the operating margin, and to allow dummy cells to be unnecessary to improve the operating margin of a DRAM without increasing the power consumption and/or the chip area. A voltage of a common plate line is changed from a first voltage to a second voltage lower than the first voltage while a word line is a third voltage which makes the word line a selected state. The voltage of the word line is changed into a fourth voltage which makes the memory cell a non-selected state and is lower than the third voltage and higher than a fifth voltage which makes the word line a non-selected state, and the voltage of the plate line is changed into the first voltage after the voltage of the word line has been changed into the fourth voltage.

Abstract: A memory cell that includes a memory element configured for switching from a first data state to a second data state by passage of current therethrough. The memory cell includes a top electrode and a bottom electrode for providing the current through the memory cell, and an alignment element positioned at least between the top electrode and the top surface of the memory element, the alignment element having an electrically conductive body tapering from the top electrode to the top surface of the memory element. Methods for forming the memory cell are also described.

Abstract: A microelectronic programmable structure and methods of forming and programming the structure are disclosed. The programmable structure generally include an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying a bias across the electrodes, and thus information may be stored using the structure.

Abstract: An object of the present invention is to provide nonvolatile, rewritable, easily-manufactured, and inexpensive storage element, storage device, and semiconductor device, which are superior in switching characteristics and which has low operation voltage. In an element including a first conductive layer, a second conductive layer facing the first conductive layer, and a layer containing at least one kind of an organic compound provided between the first conductive layer and the second conductive layer, the organic compound can be electrochemically doped or dedoped. By feeding current in this element, the organic compound provided between the conductive layers is electrochemically doped, i.e., electrons are transported, whereby the conductivity can be increased by about three to ten digits.

Abstract: A memory cell is provided in the present invention. The memory cell includes a first electrode receiving a first voltage to form an electric field therearound; and a combination arranged on the first electrode, comprising a liquid crystal molecule coupled with a magnetic substance for forming a magnetic field therearound, wherein the magnetic field changing with the first electric field.

Abstract: A power supply voltage for a memory on an integrated circuit is dynamically adjusted during the operating of the memory. The operating of the memory includes powering the memory at a supply voltage. A test memory of the integrated circuit is concurrently powered while operating the memory. The test memory and the memory each include bit cells of a first bit cell configuration type. A voltage level of the supply voltage is adjusted, while operating the memory, based on the testing of the test memory. The voltage level is adjusted with external variations to assume a value that guarantees no failed operation of the memory but also accurately minimizes the supply voltage. The system and method may be implemented with any type of memory. The memory and test memory may be physically implemented either separated or interspersed on the integrated circuit.

Abstract: A method of electronic computing, and more specifically, a method of design of cache hierarchies in 3-dimensional chips, and a cache hierarchy resulting therefrom, including a physical arrangement of bits in cache hierarchies implemented in 3 dimensions such that the planar wiring required in the busses connecting the levels of the hierarchy is minimized. In this way, the data paths between the levels are primarily the vias themselves, which leads to very short, hence fast and low power busses.

Abstract: A memory device includes a storage node, a first electrode, and a second electrode formed in a memory cell, the storage node stores electrical charges, the first electrode comprising a first portion electrically connected to a second portion, the first portion moves to connect to the storage node when the second electrode is energized.

Abstract: A high performance logic circuit optimizes a digital logic function by dividing the function into smaller blocks. Thus, the logic circuit is divided into smaller blocks. The smaller blocks are implemented with read-only memory (ROM), in which outputs corresponding to input combination are pre-stored. Inputs to each of the smaller blocks are used as an address to access the ROM.

Abstract: The various embodiments of the invention relate generally to semiconductors and memory technology. More specifically, the various embodiment and examples of the invention relate to memory devices, systems, and methods that protect data stored in one or more memory devices from unauthorized access. The memory device may include third dimension memory that is positioned on top of a logic layer that includes active circuitry in communication with the third dimension memory. The third dimension memory may include multiple layers of memory that are vertically stacked upon each other. Each layer of memory may include a plurality of two-terminal memory elements and the two-terminal memory elements can be arranged in a two-terminal cross-point array configuration. At least a portion of one or more of the multiple layers of memory may include an obfuscation layer configured to conceal data stored in one or more of the multiple layers of memory.

Abstract: A semiconductor device includes a core memory array and a periphery area. The core memory array area includes a group of memory cells. The periphery area includes a group of select transistors. The select transistors are formed at substantially the same pitch as the memory cells in the core memory array and with substantially the same channel length.

Abstract: The memory element includes a first conductive layer, a second conductive layer, a layer containing a compound which can exhibit liquid crystallinity which is interposed between the first conductive layer and the second conductive layer, and a layer containing an organic compound which is interposed between the first conductive layer and the second conductive layer and is in contact with the layer containing the compound which can exhibit liquid crystallinity. The layer containing the compound which can exhibit liquid crystallinity is formed in contact with the first conductive layer and is a layer which transfers at least from a first phase to a second phase.

Abstract: A memory array includes a plurality of memory cells, each of which receives a bit line, a first word line, and a second word line. Each memory cell includes a cell selection circuit, which allows the memory cell to be selected. Each memory cell also includes a two-terminal switching device, which includes first and second conductive terminals in electrical communication with a nanotube article. The memory array also includes a memory operation circuit, which is operably coupled to the bit line, the first word line, and the second word line of each cell. The circuit can select the cell by activating an appropriate line, and can apply appropriate electrical stimuli to an appropriate line to reprogrammably change the relative resistance of the nanotube article between the first and second terminals. The relative resistance corresponds to an informational state of the memory cell.

Abstract: A scalable nano-electro-mechanical memory cell design that requires only conventional semiconductor fabrication materials and surface micromachining technology, and is suited for use in cross-point memory arrays for very high density non-volatile storage. This design also leverages well established surface-micromachining technology and electro-mechanical device phenomena to achieve an elegantly simple and scalable memory cell structure that can potentially operate with low voltage. An elongate beam is held between a non-deflected state and a deflected state, or between two deflected states, therein defining two binary memory states. Stiction, buried charge layers, or a combination of stiction and buried charge layers can be incorporated to modify the stability of one or both deflected states for the cell. Current through the moveable portion of the elongate beam within the memory cell can be registered utilizing one or more access transistors for reading the data state.

Abstract: A control circuit (1, 11) for a memory matrix is used that defines a write process that uses circuit state transitions between at least two idle circuit states, an all column update circuit state and a column selective update state. In the second. During access the control circuit switches back and forth to the column selective update state (W) from the first idle state (II) during execution of a column selective update command and back and forth to the all-column update state (E) from the second idle state (12) during execution of an all column update command. The control circuit (1, 11) is retained in the first and second idle state (II, 12), without switching to the second and first idle state (12, II) between execution of successive column selective update commands and all column update commands respectively.

Abstract: A ballistic memory cell structure employing ballistic transistor technology for switching between a read state and a store state is disclosed. The memory cell structure includes substrate structures forming a side wall and a main chamber for defining a linear ballistic channel between the two. The main chamber is formed to include a deflection channel with deflective surfaces to deflect an electron emitted from an electron source into the memory cell structure. Deflection controllers are coupled to the substrate structures for generating biasing fields that adjust the trajectory of electrons flowing through the linear ballistic channel and the deflection channel. Logic output terminals are positioned beyond channel exits for registering exiting electrons and determining a read or store state.

Abstract: Disclosed is a switching element including: an insulative substrate; a first electrode and a second electrode provided to the insulative substrate; an interelectrode gap between the first electrode and the second electrode, comprising a gap of a nanometer order which causes switching phenomenon of resistance by applying a predetermined voltage between the first electrode and the second electrode; and a sealing member to seal the interelectrode gap such that the gap is retained.

Abstract: A memory element comprises an addressable memory cell. A thermoelectric device couples to the memory cell. Electrical conductors provide a current pulse to the thermoelectric device. The current pulse generates a thermoelectric heat flow pulse between the thermoelectric device and the memory cell.

Abstract: A switching device according to the present invention includes ion conductive layer 23 containing titanium oxide, first electrode 21 provided in contact with ion conductive layer 23, and second electrode 22 provided in contact with ion conductive layer 23 and which can supply metal ions to ion conductive layer 23.

Abstract: A memory array includes a plurality of memory cells, each of which receives a bit line, a first word line, and a second word line. Each memory cell includes a cell selection circuit, which allows the memory cell to be selected. Each memory cell also includes a two-terminal switching device, which includes first and second conductive terminals in electrical communication with a nanotube article. The memory array also includes a memory operation circuit, which is operably coupled to the bit line, the first word line, and the second word line of each cell. The circuit can select the cell by activating an appropriate line, and can apply appropriate electrical stimuli to an appropriate line to reprogrammably change the relative resistance of the nanotube article between the first and second terminals. The relative resistance corresponds to an informational state of the memory cell.

Abstract: A memory element which has high affinity with a conventional semiconductor process, which has a switching function of completely interrupting electric conduction paths by in a mechanical manner, and in which nonvolatile information recording is enabled is realized. An electromechanical memory which is formed on a substrate, which is formed by interposing a memory cell by electrodes, and which has a movable electrode that is a beam stretched in the air via a post portion is realized. According to the configuration, a nonvolatile memory can be realized by a simple structure, and it is possible to realize a high-performance electromechanical memory which is conventionally difficult to be realized, and in which the power consumption is low and the cost is low, and an electric apparatus using it.

Abstract: To greatly increase the storage density of a storage apparatus, an electron beam E emitted from a cold cathode 101 is accelerated by an accelerating electrode 102, caused to converge by a convergence electrode 103, deflected by a deflection electrode 104 and applied to a minute region of a storage film 105. The storage film 105 includes, for example, a phase change film 105a. The film is rapidly heated and cooled to change into an amorphous state upon irradiation with an electron beam E with high energy, while being gradually cooled to change into a crystallized state upon irradiation with an electron beam E with approximately intermediate energy, thereby storing data. Upon irradiation with an electron beam E with low energy, the potential difference between a detection electrode 105b and an anode 105c is detected depending on the state, i.e., the amorphous or crystallized state, thereby reading stored data.

Abstract: The present disclosure concerns a means to use at least a form of electromagnetic excitation or light-matter interactions in a structure or material having one or more addressable frequencies to generate the exchange of thermal, kinetic, electronic or photonic energy. In some implementations this provides a means to use electromagnetic excitation or light-matter interactions to influence, cause, control, modulate, stimulate or change the state or phase of electrical, magnetic, optical or electromagnetic charge, emission, conduction, storage or similar properties. The method could include the use of light-matter interactions to generate electromagnetic excitation or light-matter interactions and concentrate extremely localized field effects or concentrated plasmonic field effects to cause an exchange of energy states in a material or structure.

Abstract: A reference cell layout includes a plurality of active areas, in parallel to each other, and a first contact of the active areas, and a first gate, the first contact shorting the active areas. A memory device includes the reference cell layout and a corresponding array of memory cells having active areas sized substantially identical to the active areas of the reference cell layout and plural second contacts respectively contacting the active areas of the memory cells.

Abstract: A method of implementing a write operation for a programmable resistive random access memory array includes coupling a current source to a bit line associated with a programmable resistive memory element; prior to activating a word line associated with the memory element, precharging the bit line by passing current the bit line and through a dummy path selectively coupled to the bit line; and upon achieving a desired operating point of bit line current and bit line voltage, decoupling the dummy path from the bit line and activating the word line associated with the memory element so as to cause current from the bit line to flow for a period of time selected to program the memory element to one of a low resistance state and a high resistance state.

Abstract: Methods and apparatus for managing electrical loads of electronic devices are disclosed. According to one embodiment, a current load imposed by an electronic device, such as a memory device (or memory system), can be measured. Then, using the measured current load, the memory device can determine whether (and to what extent) operational performance should be limited. By limiting operational performance, the memory device is able to limit its current load so as to satisfy a specification criterion or other requirement. The electrical load management is well suited for use in portable memory products (e.g., memory cards) to manage current loads being drawn.

Abstract: A system and method for conserving power in a power managed information handling system are provided. While the host unit or central processing unit of the information handling system is in a reduced power state, the communication controller maintains received data in an associated buffer. The communication controller releases all or a portion of the buffered data during time intervals in which the host unit is in a normal operating mode. By buffering and releasing data in coordination with the reduced power state and normal operating state, respectively, of the host unit, power conservation in the information handling system may be enhanced by not causing the host unit to return to normal operation prematurely.

Abstract: In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter having an input and an output. A first resistor is coupled between the output of the first inverter and the input of the second inverter. A second resistor is coupled between the output of the second inverter and the input of the first inverter. A first write transistor is coupled to the output of the first inverter and has a gate coupled to a source of a first set of write-control signals and a second write transistor is coupled to the output of the second inverter and has a gate coupled to said source of a second set of write-control signals. Finally, a pass transistor has a gate coupled to the output of on of the first and second inverters.

Abstract: A biometric sensing device includes a sensor manufacture for sensing a biometric stimulus. The sensor manufacture is also configured to persistently store data electronically, such as security data.

Abstract: A self aligning memory device, with a memory element switchable between electrical property states by the application of energy, includes a substrate and word lines, at least the sides of the word lines covered with a dielectric material which defines gaps. An access device within a substrate has a first terminal under a second gap and second terminals under first and third gaps. First and second source lines are in the first and third gaps and are electrically connected to the second terminals. A first electrode in the second gap is electrically connected to the first terminal. A memory element in the second gap is positioned over and electrically connected to the first electrode. A second electrode is positioned over and contacts the memory element. The first contact, the first electrode, the memory element and the second electrode are self aligning. A portion of the memory element may have a sub lithographically dimensioned width.

Abstract: A highly dense form of static random-access memory (SRAM) takes advantage of transistor gates on both sides of silicon and high interconnectivity made possible by the complex form of silicon-on-insulator and three-dimensional integration. This technology allows one to form p-channel and n-channel devices very compactly by taking advantage of placement of gates on both sides, making common contacts and dense interconnections in 3D.

Abstract: Disclosed are a method for forming an organic layer pattern which is characterized by forming a thin layer by coating a coating solution including a polyimide-based polymer having a heteroaromatic pendant group including a heteroatom in its polyimide major chain, a photoinitiator and a crosslinking agent on a substrate and drying the substrate, and exposing and developing the thin layer, an organic layer pattern prepared by the method, and an organic memory device comprising the pattern. According to example embodiments, a high-resolution micropattern may be formed without undergoing any expensive process, e.g., photoresist, leading to simplification of the preparation process and cost reduction.

Abstract: A low-power magnetic random access memory (MRAM) with high write selectivity is provided. Write word lines and pillar write word lines covered with a magnetic material are disposed in an zigzag relation, solving the magnetic interference problem generated by cells adjacent to the pillar write word line in the magnetic RAM with the pillar write word line form. According to the disclosed structure, each of the cells has a smaller bit size and a lower write current. This effectively reduces the power consumption of the MRAM.

Abstract: One main electrode of a TFT is connected with one terminal of a two-terminal type nonvolatile memory element, a gate electrode of the TFT is connected with a word line, and the other main electrode thereof is connected with a bit line. The other terminal of the memory element is connected with a base line. A fixed resistor is connected between a connecting point between the other main electrode of the TFT and the bit line and an input terminal of the bit line. In information writing for changing the memory element whose initial state is a low impedance state to a high impedance state, voltages having polarities reverse relative to a reference voltage are applied to the input terminal of the bit line and an input terminal of the base line, respectively, so that a high voltage necessary to change the state is applied between both the terminals of the memory element.

Abstract: A memory device includes a mechanical element that exhibits distinct bistable states under amplitude modulation. The states are dynamically bistable or multi-stable with the application of a drive signal of a given frequency. The natural resonance of the element in conjunction with a hysteretic effect produces distinct states over a specific frequency range. Devices with multiple elements that respond to different frequency ranges provided on a common contact are formed with improved density. The devices may be excited and read with magnetomotive, capacitive, piezoelectric and/or optical methods. The devices may be planar oriented or out of plane oriented to permit three dimensional memory structures. DC biases may be used to shift frequency responses to permit an alternate method for differentiating states of the element.

Abstract: A memory cell uses a pair of cantilevers to store a bit of information. Changing the relative position of the cantilevers determines whether they are electrically conducting or not. The on and off state of this mechanical latch is switched by using, for example, electrostatic, electromagnetic or thermal forces applied sequentially on the two cantilevers to change their relative position. The amount of power required to change the state of the cell is reduced by supporting at least one of the cantilevers with at least one lateral projection that is placed in torsion during cantilever displacement. After a bit of data is written, the cantilevers are locked by mechanical forces inherent in the cantilevers and will not change state unless a sequential electrical writing signal is applied. The sequential nature of the required writing signal makes inadvertent, radiation or noise related data corruption unlikely.