Abstract: An embodiment of the invention provides a method for manufacturing an array substrate, wherein the procedure for forming a data line, an active layer with a channel, a source electrode, a drain electrode and a pixel electrode comprises applying a photoresist on a data line metal thin film and performing exposure and development processes by using a multi-tone mask so as to form a photoresist pattern including a third thickness region, a second thickness region and a first thickness region whose thicknesses are successively increased, the third thickness region at least corresponding to the pixel electrode, the second thickness region corresponding to the data line, the active layer, the source electrode and the drain electrode, and the first thickness region corresponding to the other regions.

Abstract: An active device including a source, a drain, an oxide semiconductor layer, a gate and a gate insulator layer is provided. The source includes first stripe electrodes parallel to each other and a first connection electrode connected thereto. The drain includes second stripe electrodes parallel to each other and a second connection electrode connected thereto, wherein the first stripe electrodes and the second stripe electrodes are parallel to each other, electrically isolated, and alternately arranged, and a zigzag trench is formed therebetween. The gate extends along the zigzag trench. The oxide semiconductor layer is in contact with the source and drain, wherein a contact area among the oxide semiconductor layer and each first stripe electrodes substantially equals to a layout area of each first stripe electrodes and a contact area among each second stripe electrodes substantially equals to a layout area of each second stripe electrodes.

Abstract: A semiconductor device includes an internal circuit provided on a substrate, a plurality of external terminals connected to the internal circuit, a plurality of wires connecting the internal circuit and the external terminals, and a plurality of inductors communicating with an external device. Each of the inductors is connected to each of the wires. The external terminals are formed in a region not to interrupt communication between the inductors and the external device.

Abstract: A method of providing miniaturized size down to nanoscale electronic materials, which may be easily incorporated into the future ever-scaling down power electronics, microelectronics and nanoelectronics device systems, is disclosed. A linear or nonlinear nanoparticle (nanowire) junction design that allows precise controllability over an electronic device (e.g., a varistor) performance, which is typically difficult for the traditional sintered bulk varistor, is also disclosed. A localized doping and chemical modulation, across junctions allows flexible and tunable design over the nanoscale grain boundary band engineering is further disclosed. Furthermore, a method of operating memory, using electrostatic potential modulated coding and decoding across periodic nanoparticle grain boundary linearly, is also disclosed.

Abstract: A microelectromechanical (MEMS) device is fabricated from a wafer having a plurality of die regions with grooves and MEMS components formed on a wafer surface at each die region. A first metal having a relatively high melting temperature is formed on sidewalls of each groove, and a cap is attached at each die region to provide a closed cavity which encloses the grooves and MEMS components. Bottoms of the grooves are opened by thinning the wafer thereby establishing through-hole vias extending through the wafer at each die region, for accessing the cavity for inserting or removing material. The vias are sealed by interacting a second metal having a relatively low melting temperature with the first metal layer to form intermetallic compounds with higher melting temperature that maintain the seal during subsequent lower temperature operations.

Abstract: An example embodiment relates to a semiconductor device including a semiconductor package in which a semiconductor chip is mounted on the package substrate. The semiconductor package may include a temperature measurement device and a temperature control circuit. The temperature measurement device may measure a temperature of the semiconductor package. The temperature control circuit may change an operation speed of the semiconductor package on the basis of the temperature of the semiconductor package measured by the temperature measurement device.

Abstract: Semiconductor devices having integrated nanochannels confined by nanometer spaced electrodes, and VLSI (very large scale integration) planar fabrication methods for making the devices. A semiconductor device includes a bulk substrate and a first metal layer formed on the bulk substrate, wherein the first metal layer comprises a first electrode. A nanochannel is formed over the first metal layer, and extends in a longitudinal direction in parallel with a plane of the bulk substrate. A second metal layer is formed over the nanochannel, wherein the second metal layer comprises a second electrode. A top wall of the nanochannel is defined at least in part by a surface of the second electrode and a bottom wall of the nanochannel is defined by a surface of the first electrode.

Abstract: The present invention provides a method for an organic thin film solar cell and an organic thin film solar cell manufactured by the same, which can reduce manufacturing cost by simplifying manufacturing process, ensure long-lasting durability and stability, and improve energy conversion efficiency of the solar cell.

Abstract: An apparatus and method for sensor architecture based on bulk machining of silicon wafers and fusion bond joining which provides a nearly all-silicon, hermetically sealed, microelectromechanical system (MEMS) device. An example device includes a device sensor mechanism formed in an active semiconductor layer and separated from a handle layer by a dielectric layer, and a silicon cover plate having a handle layer with a dielectric layer being bonded to portions of the active layer. Pit are included in one of the handle layers and corresponding dielectric layers to access electrical leads on the active layer. Another example includes set backs from the active components formed by anisotropically etching the handle layer while the active layer has been protectively doped.

Abstract: There is provided an exposing device which includes an elongated optical head in which a plurality of light emitting portions are arranged, and a supporting member to which the optical head is adhered. The optical head and the supporting member are adhered by a first adhesive, and a second adhesive of which a modulus of elasticity after curing is lower than that of the first adhesive. The second adhesive is applied in a second adhesive area which is located at a boundary between the optical head and the supporting member and which is longer, in a longitudinal direction of the optical head, than a first adhesive area which is located at the boundary and to which the first adhesive is applied.

Abstract: Disclosed are methods and apparatus for masking of substrates for deposition, and subsequent lifting of the mask with deposited material. Masking materials are utilized that can be used in high temperatures and vacuum environment. The masking material has minimal outgassing once inside a vacuum chamber and withstand the temperatures during deposition process. The mask is inkjeted over the wafers and, after deposition, removed using agitation, such as ultrasonic agitation, or using laser burn off.

Abstract: A method for manufacturing a semiconductor apparatus includes the first step of forming a silicon oxide film including a main portion on a second portion and a sub portion between a first portion and a silicon nitride film, the second step of forming a first conductivity type impurity region under the silicon oxide film, and the third step of forming a semiconductor element including a second conductivity type impurity region having an opposite conductivity to the first conductivity type impurity region in the first portion. In the second step, angled ion implantation is performed into a region under the sub portion at an implantation angle using the silicon nitride film as a mask.

Abstract: A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a first sidewall, a second sidewall, a third sidewall, a fourth sidewall, and a bottom wall. The method includes depositing a first conductive material within the trench proximate to the first sidewall and depositing a second conductive material within the trench. The method further includes depositing a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure that is adjacent to the fourth sidewall to create an opening such that the MTJ structure is substantially u-shaped.

Abstract: A reflective film including Ag of an Ag alloy is patterned in a uniform thickness without decreasing reflectivity. The reflective film is formed on the entire surface of a first insulating film by sputtering, vacuum deposition or the like, and a barrier metal film having a given pattern is formed on the reflective film by a lift-off method. The reflective film is wet etched using a silver etching liquid. The barrier metal film is not wet etched by the silver etching liquid, and therefore functions as a mask, and the reflective film in a region on which the barrier metal film has been formed remains not etched. As a result, the reflective film having a desired patter can uniformly be formed on the first insulating film.

Abstract: The invention provides combination semiconductor and plasma devices, including transistors and phototransistors. A preferred embodiment hybrid plasma semiconductor device has active solid state semiconductor regions; and a plasma generated in proximity to the active solid state semiconductor regions. Devices of the invention are referred to as hybrid plasma-semiconductor devices, in which a plasma, preferably a microplasma, cooperates with conventional solid state semiconductor device regions to influence or perform a semiconducting function, such as that provided by a transistor. The invention provides a family of hybrid plasma electronic/photonic devices having properties previously unavailable. In transistor devices of the invention, a low temperature, glow discharge is integral to the hybrid transistor. Example preferred devices include hybrid BJT and MOSFET devices.

Abstract: An electronic package implemented in an electronic device may include a damaged connection that restricts electrical communication between components in the electronic package. For example, the damaged connection may restrict communication between a silicon unit, such as a processor die for example, and a printed circuit board. The damaged connection may be repaired without damaging other components in the electronic package by using a repair apparatus that includes a heating element and a cooling element. The heating element may be activated to transfer heat to the electronic package for reforming the damaged connection between components to enable effective electrical communication. The cooling element may be activated for cooling components in the electronic package to prevent damage due to the transfer of the heat from the heating element. The heating element and/or the cooling element may be activated in a predetermined pattern to facilitate the repair of the damaged connection.

Abstract: An exemplary embodiment may include a substrate, an insulating layer on the substrate, and a pixel electrode including a transparent conductive layer on the insulating layer. A portion of a surface of the insulating layer contacting the transparent conductive layer has a plurality of recessed holes formed by etching with an etchant into an interface between the transparent conductive layer of the pixel electrode and the insulating layer.

Abstract: When forming critical threshold adjusting semiconductor alloys and/or strain-inducing embedded semiconductor materials in sophisticated semiconductor devices, at least the corresponding etch processes may be monitored efficiently on the basis of mechanically gathered profile measurement data by providing an appropriately designed test structure. Consequently, sophisticated process sequences performed on bulk semiconductor devices may be efficiently monitored and/or controlled by means of the mechanically obtained profile measurement data without significant delay. For example, superior uniformity upon providing a threshold adjusting semiconductor alloy in sophisticated high-k metal gate electrode structures for non-SOI devices may be achieved.

Abstract: A CMOS image sensor, in which an implantation process is performed on substrate under isolation structures each disposed between two adjacent photosensor cell structures. The implantation process is a destructive implantation to form lattice effects/trap centers. No defect repair process is carried out after the implantation process is performed. The implants can reside at the isolation structures or in the substrate under the isolation structures. Dark leakage and crosstalk are thus suppressed.

Abstract: A fringe field switching (FFS) liquid crystal display (LCD) device which uses an organic insulating layer and consumes less power, in which film quality of an upper layer of a low temperature protective film is changed to improve undercut within a pad portion contact hole, and a method for fabricating the same is provided.

Abstract: A unit pixel of an image sensor and a photo detector are disclosed. The photo detector of the present invention configured to absorb light can include: a light-absorbing part configured to absorb light by being formed in a floated structure; an oxide film being in contact with one surface of the light-absorbing part; a source being in contact with one side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; a drain facing the source so as to be in contact with the other side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; and a channel interposed between the source and the drain and configured to form flow of an electric current between the source and the drain.

Abstract: A unit pixel of an image sensor and a photo detector are disclosed. The photo detector of the present invention configured to absorb light can include: a light-absorbing part configured to absorb light by being formed in a floated structure; an oxide film being in contact with one surface of the light-absorbing part; a source being in contact with one side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; a drain facing the source so as to be in contact with the other side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; and a channel interposed between the source and the drain and configured to form flow of an electric current between the source and the drain.

Abstract: A method for manufacturing a micromechanical structure includes: forming a first insulation layer above a substrate; forming a first micromechanical functional layer on the first insulation layer; forming multiple first trenches in the first micromechanical functional layer, which trenches extend as far as the first insulation layer; forming a second insulation layer on the first micromechanical functional layer, which second insulation layer fills up the first trenches; forming etch accesses in the second insulation layer, which etch accesses locally expose the first micromechanical functional layer; and etching the first micromechanical functional layer through the etch accesses, the filled first trenches and the first insulation layer acting as an etch stop.

Abstract: A method of providing microelectromechanical structures (MEMS) that are compatible with silicon CMOS electronics is provided. The method providing for processes and manufacturing sequences limiting the maximum exposure of an integrated circuit upon which the MEMS is manufactured to below 350° C., and potentially to below 250° C., thereby allowing direct manufacturing of the MEMS devices onto electronics, such as Si CMOS circuits. The method further providing for the provisioning of MEMS devices with multiple non-conductive structural layers such as silicon carbide separated with small lateral gaps. Such silicon carbide structures offering enhanced material properties, increased environmental and chemical resilience whilst also allowing novel designs to be implemented taking advantage of the non-conductive material of the structural layer.

Abstract: A semiconductor light detecting element includes: an InP substrate; and a semiconductor stacked structure on the InP substrate and including at least a light absorbing layer, wherein the light absorbing layer includes an InGaAsBi layer lattice-matched to the InP substrate.

Abstract: A solid-state image pickup device includes an element isolation insulating film electrically isolating pixels on the surface of a well region; a first isolation diffusion layer electrically isolating the pixels under the element isolation insulating film; and a second isolation diffusion layer electrically isolating the pixels under the first isolation diffusion layer, wherein a charge accumulation region is disposed in the well region surrounded by the first and second isolation diffusion layers, the inner peripheral part of the first isolation diffusion layer forms a projecting region, an impurity having a conductivity type of the first isolation diffusion layer and an impurity having a conductivity type of the charge accumulation region are mixed in the projecting region, and a part of the charge accumulation region between the charge accumulation region and the second isolation diffusion layer is abutted or close to the second isolation diffusion layer under the projecting region.

Abstract: A method of roughening a substrate surface includes forming an opening in a protection film formed on a surface of a semiconductor substrate, performing a first etching process using an acid solution by utilizing the protection film as a mask so as to form a first concave under the opening and its vicinity area, performing an etching process by using the protection film as a mask so as to remove an oxide film formed on a surface of the first concave, performing anisotropic etching by using the protection film as a mask so as to form a second concave under the opening and its vicinity area, and removing the protection film.

Abstract: Pixels, imagers and related fabrication methods are described. The described methods result in cross-talk reduction in imagers and related devices by generating depletion regions. The devices can also be used with electronic circuits for imaging applications.

Abstract: The present invention discloses an MEMS sensor and a method for making the MEMS sensor. The MEMS sensor according to the present invention includes: a substrate including an opening; a suspended structure located above the opening; and an upper structure, a portion of which is at least partially separated from a portion of the suspended structure; wherein the suspended structure and the upper structure are separated from each other by a step including metal etch.

Abstract: A light emitting diode (LED) array includes a substrate with an array having a plurality of LED chips thereon, a dielectric layer, a plug, and a conductive connection layer. Each of the LED chips is isolated from another LED chip adjacent thereto by a trench. The dielectric layer covers a surface of the substrate exposed by the trench and sidewalls and partial surfaces of the LED chips adjacent to the trench. The plug fills the trench. The conductive connection layer is disposed over the plug and the dielectric layer to connect the LED chips with the LED chips adjacent thereto. Radiation emitted from one of the LED chips can be reflected by the dielectric layer and the plug, and finally reflected and output from a side of the LED chip not adjacent to the trench, thereby not affecting the adjacent LED chip and being absorbed by it.

Abstract: A process of forming a MEMS device with a device cavity underlapping an overlying dielectric layer stack having an etchable sublayer over an etch-resistant lower portion, including: etching through at least the etchable sublayer of the overlying dielectric layer stack in an access hole to expose a lateral face of the etchable sublayer, covering exposed surfaces of the etchable sublayer by protective material, and subsequently performing a cavity etch. A cavity etch mask may cover the exposed surfaces of the etchable sublayer. Alternatively, protective sidewalls may be formed by an etchback process to cover the exposed surfaces of the etchable sublayer. Alternatively, the exposed lateral face of the etchable sublayer may be recessed by an isotropic etch, than isolated by a reflow operation which causes edges of an access hole etch mask to drop and cover the exposed lateral face of the etchable sublayer.

Abstract: A structure and a process for a microelectromechanical system (MEMS)-based sensor are provided. The structure for a MEMS-based sensor includes a substrate chip. A first insulating layer covers a top surface of the substrate chip. A device layer is disposed on a top surface of the first insulating layer. The device layer includes a periphery region and a sensor component region. The periphery region and a sensor component region have an air trench therebetween. The component region includes an anchor component and a moveable component. A second insulating layer is disposed on a top surface of the device layer, bridging the periphery region and a portion of the anchor component. A conductive pattern is disposed on the second insulating layer, electrically connecting to the anchor component.

Abstract: An electrostatic discharge device and an organic electro-luminescence display device having the same are provided. The organic electro-luminescence display device includes an electrostatic discharge device including a metal pattern having an island shape on a substrate, an insulating layer on the metal pattern, a semiconductor pattern on the insulating layer, the semiconductor pattern corresponding to the metal pattern, a first electrode overlapping one end of the semiconductor pattern, and a second electrode overlapping the other end of the semiconductor pattern, and spaced from the first electrode, thereby preventing a current leakage, a signal distortion and a signal cross-talk to improve the reliability.

Abstract: An improved diode energy converter for chemical kinetic electron energy transfer is formed using nanostructures and includes identifiable regions associated with chemical reactions isolated chemically from other regions in the converter, a region associated with an area that forms energy barriers of the desired height, a region associated with tailoring the boundary between semiconductor material and metal materials so that the junction does not tear apart, and a region associated with removing heat from the semiconductor.

Abstract: The present sensor chip comprises a substrate. A plurality of electrode elements is arranged at a first level on the substrate with at least one gap between neighbouring electrode elements. A metal structure is arranged at a second level on the substrate, wherein the second level is different from the first level. The metal structure at least extends over an area of the second level that is defined by a projection of the at least one gap towards the second level.

Abstract: In the present invention, one or more inventive designs and techniques allow formation of high speed complementary metal oxide semiconductor (CMOS) process compatible tunneling devices that are formed on low dielectric loss sheet-substrates (such as silicon or germanium for infrared or quartz and sapphire for visible or near infrared) having the first and the second smooth planar surfaces and an intermediate surface in the form of a hole, or slit, or a side edge, which extends between and connects the first and second surfaces, so that deposited from opposite sides of the sheet-substrate the first metal layer followed by its oxidation or nanometer thickness tunneling dielectric coating and the second metal layer have an overlapped coupled area within the intermediate surface, thus forming a non-planar metal-insulator-metal (MIM) tunneling junction of low capacitance and high cut-off frequency, which is capable to operate at room temperature at terahertz, infrared, and even optical frequencies.

Abstract: A photodetector is formed in a front surface of a substrate. The substrate is thinned from a back surface of the substrate. A plurality of dopants is introduced into the thinned substrate from the back surface. The plurality of dopants in the thinned substrate is annealed. An anti-reflective layer is deposited over the back surface of the thinned substrate. A micro lens is formed over the anti-reflective layer. At least one ultraviolet (UV) radiation treatment is performed after at least one of the preceding steps.

Abstract: Touch sensing systems comprising bulk-solidifying amorphous alloys and methods of making touch sensing arrays and electronic devices containing touch sensitive screens that include arrays containing bulk-solidifying amorphous alloys. The bulk-solidifying amorphous alloy substrates have select areas of crystalline and amorphous alloy providing for discrete areas of conductivity and resistivity.

Abstract: An apparatus, system, and method are disclosed for providing optical power to a semiconductor chip. An active semiconductor layer of the semiconductor chip is disposed toward a front side of the semiconductor chip. The active semiconductor layer comprises one or more integrated circuit devices. A photovoltaic semiconductor layer of the semiconductor chip is disposed between the active semiconductor layer and a back side of the semiconductor chip. The back side of the semiconductor chip is opposite the front side of the semiconductor chip. The photovoltaic semiconductor layer converts electromagnetic radiation to electric power. One or more conductive pathways between the photovoltaic semiconductor layer and the active semiconductor layer provide the electric power from the photovoltaic semiconductor layer to the one or more integrated circuit devices of the active semiconductor layer.

Abstract: A method for manufacturing a solar cell is presented. The method includes: forming an amorphous silicon layer on a first surface of a light absorbing layer; doping the amorphous silicon layer with a dopant; forming a dopant layer by diffusing the dopant into the amorphous silicon layer with a laser; forming a semiconductor layer by removing the dopant that remains outside the dopant layer; etching the surface of the semiconductor layer by using an etchant; forming a first electrode on the semiconductor layer; and forming a second electrode on a second surface of the light absorbing layer.

Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a MEMS device, and technique of fabricating or manufacturing a MEMS device, having mechanical structures encapsulated in a chamber prior to final packaging. The material that encapsulates the mechanical structures, when deposited, includes one or more of the following attributes: low tensile stress, good step coverage, maintains its integrity when subjected to subsequent processing, does not significantly and/or adversely impact the performance characteristics of the mechanical structures in the chamber (if coated with the material during deposition), and/or facilitates integration with high-performance integrated circuits. In one embodiment, the material that encapsulates the mechanical structures is, for example, silicon (polycrystalline, amorphous or porous, whether doped or undoped), silicon carbide, silicon-germanium, germanium, or gallium-arsenide.

Abstract: A device for detecting the thinning down of the substrate of an integrated circuit chip, including, in the active area of the substrate, bar-shaped diffused resistors connected as a Wheatstone bridge, wherein: first opposite resistors of the bridge are oriented along a first direction; the second opposite resistors of the bridge are oriented along a second direction; and the first and second directions are such that a thinning down of the substrate causes a variation of the imbalance value of the bridge.

Abstract: A back-illuminated image sensor includes a sensor layer disposed between an insulating layer and a circuit layer electrically connected to the sensor layer. An imaging area includes a plurality of photodetectors is formed in the sensor layer and a well that spans the imaging area. The well can be disposed between the backside of the sensor layer and the photodetectors, or the well can be a buried well formed adjacent to the backside of the sensor layer with a region including formed between the photodetectors and the buried well. One or more side wells can be formed laterally adjacent to each photodetector. The dopant in the well has a segregation coefficient that causes the dopant to accumulate on the sensor layer side of an interface between the sensor layer and the insulating layer.

Abstract: A finger sensing device may include a mounting substrate having a recess in a top surface thereof and having conductive through-vias extending from the top surface to a bottom surface. The conductive through-vias may extend laterally adjacent to the recess. The finger sensing device may also include a finger sensing integrated circuit (IC) die within the recess and may include a finger sensing area on a top surface thereof and bond pads on the top surface laterally adjacent the finger sensing area. The finger sensing device may also include a dielectric layer over the mounting substrate and the finger sensing IC die. The finger sensing device may further include a conductive pattern carried by the dielectric layer and coupling the conductive through-vias to respective ones of the bond pads.

Abstract: A manufacturing method, for a liquid discharge head substrate that includes a silicon substrate in which a liquid supply port is formed, includes the steps of: preparing the silicon substrate, on one face of which a mask layer, in which an opening has been formed, is deposited; forming a first recessed portion in the silicon substrate, so that the recessed portion is extended through the opening from the one face of the silicon substrate to the other, reverse face of the silicon substrate; forming a second recessed portion by performing wet etching for the substrate, via the first recessed portion, using the mask layer; and performing dry etching for the silicon substrate in a direction from the second recessed portion to the other face.

Abstract: An apparatus and method are disclosed for electrically directly detecting biomolecular binding in a semiconductor. The semiconductor can be based on electrical percolation of nanomaterial formed in the gate region. In one embodiment of an apparatus, a semiconductor includes first and second electrodes with a gate region there between. The gate region includes a multilayered matrix of electrically conductive material with capture molecules for binding target molecules, such as antibody, receptors, DNA, RNA, peptides and aptamer. The molecular interactions between the capture molecules and the target molecules disrupts the matrix's continuity resulting in a change in electrical resistance, capacitance or impedance. The increase in resistance, capacitance or impedance can be directly measured electronically, without the need for optical sensors or labels.

Abstract: An analytical system-on-a-chip can be used as an analytical imaging device, for example, for detecting the presence of a chemical compound. A layer of analytical material is formed on a transparent layer overlying a solid state image sensor. The analytical material can react in known ways with at least one reactant to block light or to allow light to pass through to the array. The underlying sensor array, in turn, can process the presence, absence or amount of light into a digitized signal output. The system-on-a-chip may also include software that can detect and analyze the output signals of the device.

Abstract: MEMS switches and methods of fabricating MEMS switches. The switch has a vertically oriented deflection electrode having a conductive layer supported by a supporting layer, at least one drive electrode, and a stationary electrode. An actuation voltage applied to the drive electrode causes the deflection electrode to be deflect laterally and contact the stationary electrode, which closes the switch. The deflection electrode is restored to a vertical position when the actuation voltage is removed, thereby opening the switch. The method of fabricating the MEMS switch includes depositing a conductive layer on mandrels to define vertical electrodes and then releasing the deflection electrode by removing the mandrel and layer end sections.

Abstract: Fabrication of a single crystal silicon solar cell with an insitu epitaxially deposited very highly doped p-type silicon back surface field obviates the need for the conventional aluminum screen printing step, thus enabling a thinner silicon solar cell because of no aluminum induced bow in the cell. Furthermore, fabrication of a single crystal silicon solar cell with insitu epitaxial p-n junction formation and very highly doped n-type silicon front surface field completely avoids the conventional dopant diffusion step and one screen printing step, thus enabling a cheaper manufacturing process.

Abstract: A manufacturing method of a semiconductor device includes: irradiating a laser beam on a single crystal silicon substrate, and scanning the laser beam on the substrate so that a portion of the substrate is poly crystallized, wherein at least a part of a poly crystallized portion of the substrate is exposed on a surface of the substrate; and etching the poly crystallized portion of the substrate with an etchant. In this case, a process time is improved.