Making Device Or Circuit Responsive To Nonelectrical Signal Patents (Class 438/48)
  • Patent number: 8605920
    Abstract: A condenser microphone having a flexure hinge diaphragm and a method of manufacturing the same are provided. The method includes the steps of: forming a lower silicon layer and a first insulating layer; forming an upper silicon layer on the first insulating layer; forming sound holes by patterning the upper silicon layer; forming a second insulating layer and a conductive layer on the upper silicon layer; forming a passivation layer on the conductive layer; forming a sacrificial layer on the passivation layer; depositing a diaphragm on the sacrificial layer, and forming air holes passing through the diaphragm; forming electrode pads on the passivation layer and a region of the diaphragm; and etching the layers to form an air gap between the diaphragm and the upper silicon layer. Consequently, a manufacturing process may improve the sensitivity and reduce the size of the condenser microphone.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: December 10, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hye Jin Kim, Sung Q Lee, Kang Ho Park, Jong Dae Kim
  • Patent number: 8604482
    Abstract: A microelectronic device includes a plurality of disconnected similar semiconducting portions, electrically isolated from each other and forming a semiconductor layer, at a spacing by a constant distance and with a shape parallel to the other portions. The microelectronic device also includes two electrodes arranged in contact with the semiconductor layer such that a maximum distance separating the two electrodes is less than the largest dimension of one of the semiconductor portions. The shape and dimensions of the semiconductor portions, the spacing between the semiconductor portions, the shape and dimensions of the electrodes and the layout of the electrodes relative to the semiconductor portions are such that at least one of the semiconductor portions electrically connects the two electrodes to each other. The largest dimensions of the semiconductor portions are perpendicular to the largest dimension of the electrodes, the electrodes being similar.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: December 10, 2013
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Romain Gwoziecki, Romain Coppard
  • Patent number: 8597577
    Abstract: An optoelectronic swept-frequency semiconductor laser coupled to a microfabricated optical biomolecular sensor with integrated resonator and waveguide and methods related thereto are described. Biomolecular sensors with optical resonator microfabricated with integrated waveguide operation can be in a microfluidic flow cell.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: December 3, 2013
    Assignee: California Institute of Technology
    Inventors: Richard C. Flagan, Amnon Yariv, Jason Gamba, Naresh Satyan, Jacob Sendowski, Arseny Vasilyev
  • Patent number: 8597972
    Abstract: A method for manufacturing a back-illuminated type solid-state imaging device by (a) providing a substrate having, on a front surface side thereof, a semiconductor film on a semiconductor substrate with an insulation film therebetween; (b) forming in the semiconductor substrate a charge accumulation portion of a photoelectric conversion element that constitutes a pixel; (c) forming in the semiconductor film at least some transistors that constitute the pixel; and (d) forming on a rear surface side of the semiconductor substrate a rear surface electrode to which a voltage can be applied.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: December 3, 2013
    Assignee: Sony Corporation
    Inventor: Keiji Mabuchi
  • Patent number: 8592837
    Abstract: Disclosed is a semiconductor light emitting element (1) which includes: plural n-side columnar conductor portions (183), each of which is provided by penetrating a p-type semiconductor layer (160) and a light emitting layer (150), and is electrically connected to an n-type semiconductor layer (140); an n-side layer-like conductor portion (184), which is disposed on the rear surface side of the p-type semiconductor layer (160) to face the surface of the light emitting layer (150) when viewed from the light emitting layer (150), and is electrically connected to the n-side columnar conductor portions (183); plural p-side columnar conductor portions (173), each of which is electrically connected to the p-type semiconductor layer (160); and a p-side layer-like conductor portion (174), which is disposed on the rear surface side of the p-type semiconductor layer (160) to face the light emitting layer (150) when viewed from the light emitting layer (150), and is electrically connected to the p-side columnar conductor
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: November 26, 2013
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Takashi Hodota, Takehiko Okabe
  • Patent number: 8592874
    Abstract: In each of pixels 10 arranged in an array pattern, an insulating isolation part 22 electrically isolates adjacent photoelectric conversion elements 11, and the photoelectric conversion element 11 and an amplifier transistor 14. The insulating isolation part 22 constitutes a first region A between the photoelectric conversion elements 11 where the amplifier transistor 14 is not arranged, and a second region B between the photoelectric conversion elements 11 where the amplifier transistor 14 is arranged. A low concentration first isolation diffusion layer 23 is formed below the insulating isolation part 22 constituting the first region A, and a high concentration second isolation diffusion layer 24 and a low concentration first isolation diffusion layer 23 are formed below the insulating isolation part 22 constituting the second region B. A source/drain region of the amplifier transistor 14 in the second region B is formed in a well region 25 formed simultaneously with the second isolation diffusion layer 24.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: November 26, 2013
    Assignee: Panasonic Corporation
    Inventors: Mitsuyoshi Mori, Toru Okino, Yusuke Otake, Hitomi Fujiwara
  • Patent number: 8586400
    Abstract: A method of fabricating an organic photodetector including a substrate, a first electrode, an insulation layer, an organic layer, and a second electrode is provided. The first electrode is disposed on the substrate. The insulation layer is disposed on the first electrode. The organic layer is disposed on the substrate and the insulation layer and covers a side surface of the insulation layer and a side surface of the first electrode. The second electrode is disposed on the organic layer and located above the insulation layer.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: November 19, 2013
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Tzu-Yueh Chang, Po-Tsung Lee, Szu-Yuan Chen
  • Patent number: 8586393
    Abstract: A stress sensor is disclosed herein. The stress sensor includes a plurality of carbon nanotubes in a substrate, and first and second contacts electrically connectable with the plurality of carbon nanotubes. Methods of making and using the stress sensor are also disclosed.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: November 19, 2013
    Assignee: Intel Corporation
    Inventors: Mohammad M. Farahani, Vladimir Noveski, Neha M. Patel, Nachiket R. Raravikar
  • Patent number: 8587040
    Abstract: A solid state imaging device including: a pixel region that is formed on a light incidence side of a substrate and to which a plurality of pixels that include photoelectric conversion units is arranged; a peripheral circuit unit that is formed in a lower portion in the substrate depth direction of the pixel region and that includes an active element; and a light shielding member that is formed between the pixel region and the peripheral circuit unit and that shields the incidence of light, emitted from an active element, to the photoelectric conversion unit.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: November 19, 2013
    Assignee: Sony Corporation
    Inventors: Shoji Kobayashi, Yoshiharu Kudoh, Takuya Sano
  • Patent number: 8580594
    Abstract: The present disclosure provides a method including providing a first substrate; and forming a microelectromechanical system (MEMS) device on a first surface of the first substrate. A bond pad is formed on at least one bonding site on the first surface of the first substrate. The bonding site is recessed from the first surface. Thus, a top surface of the bond pad may lie below the plane of the top surface of the substrate. A device with recessed connective element(s) (e.g., bond pad) is also described. In further embodiments, a protective layer is formed on the recessed connective element during dicing of a substrate.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: November 12, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Ting Huang, Jung-Huei Peng, Shang-Ying Tsai, Yao-Te Huang, Ming-Tung Wu, Ping-Yin Liu, Xin-Hua Huang, Yuan-Chih Hsieh
  • Patent number: 8580595
    Abstract: A solid-state image sensing device includes a plurality of pixels. Each pixel has a photodiode, a first transistor, and a second transistor. The photodiode is constituted by a first-conductivity-type semiconductor region and a second-conductivity-type semiconductor region. The first and second conductivity types are opposite to each other. The first transistor has a first-conductivity-type drain region formed in the second-conductivity-type semiconductor region to transfer signal charge to the drain region. The second transistor has a source region and a drain region which are formed in the second-conductivity-type semiconductor region and which have the first conductivity type. At least one second-conductivity-type potential barrier is provided under the drain region of the first transistor and the source region and/or the drain region of the second transistor.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: November 12, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Mahito Shinohara, Shunsuke Inoue
  • Patent number: 8574941
    Abstract: A method for manufacturing a solid-state imaging device in which a charge generator that detects an electromagnetic wave and generates signal charges is formed on a semiconductor substrate and a negative-charge accumulated layer having negative fixed charges is formed above a detection plane of the charge generator. The method includes the steps of: forming an oxygen-feed film capable of feeding oxygen on the detection plane of the charge generator; forming a metal film that covers the oxygen-feed film on the detection plane of the charge generator; and performing heat treatment for the metal film in an inactive atmosphere to thereby form an oxide of the metal film between the metal film and the oxygen-feed film on the detection plane of the charge generator, the oxide being to serve as the negative-charge accumulated layer.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: November 5, 2013
    Assignee: Sony Corporation
    Inventors: Susumu Hiyama, Tomoyuki Hirano
  • Patent number: 8575474
    Abstract: Formulations and methods of making solar cell contacts and cells therewith are disclosed. In general, the invention provides a solar cell comprising a contact made from a mixture wherein, prior to firing, the mixture comprises at least one aluminum source, at least one source of a metal including one or more of boron, titanium, nickel, tin, gallium zinc, indium, and copper, and about 0.1 to about 10 wt % of a glass component. Within the mixture, the overall content of aluminum is about 50 wt % to about 85 wt % of the mixture, and the overall combined content of boron, nickel, tin, silver, gallium, zinc, indium, copper, is about 0.05 to about 40 wt % of the mixture.
    Type: Grant
    Filed: July 9, 2007
    Date of Patent: November 5, 2013
    Assignee: Heracus Precious Metals North America Conshohocken LLC
    Inventors: Jalal Salami, Srinivasan Sridharan, Steve S. Kim, Aziz S. Shaikh
  • Patent number: 8569794
    Abstract: A Group III nitride semiconductor device of the present invention is obtained by laminating at least a buffer layer (12) made of a Group III nitride compound on a substrate (11), wherein the buffer layer (12) is made of AlN, and a lattice constant of a-axis of the buffer layer (12) is smaller than a lattice constant of a-axis of AlN in a bulk state.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: October 29, 2013
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Hisayuki Miki, Yasunori Yokoyama
  • Patent number: 8569100
    Abstract: Forming an impurity diffusion layer of the second conductivity type and an antireflective film on one surface side of a semiconductor substrate of the first conductivity type; applying the first electrode material onto the antireflective film; forming a passivation film on the other surface side of the semiconductor substrate; forming openings in the passivation film to reach the other surface side; applying a second electrode material containing impurity elements of the first conductive type to fill the openings and not to be in contact with the second electrode material of adjacent openings; applying a third electrode material onto the passivation film to be in contact with the entire second electrode material; forming at a time, by heating the semiconductor substrate at a predetermined temperature after applying the first electrode material and the third electrode material, the first electrodes, a high-concentration region, and the second electrodes and third electrode.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: October 29, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Atsuro Hama, Hiroaki Morikawa
  • Patent number: 8569092
    Abstract: A method for fabricating a sensor is disclosed that in one embodiment bonds an etched semiconductor substrate wafer to an etched device wafer comprising a double silicon on insulator wafer to create a suspended structure, the flexure of which is sensed by an embedded piezoresistive sensor element. In one embodiment the sensor measures acceleration. In other embodiments the sensor measures pressure.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: October 29, 2013
    Assignee: General Electric Company
    Inventors: Naresh Venkata Mantravadi, Sisira Kankanam Gamage
  • Patent number: 8569081
    Abstract: A method of making a LED includes following steps. A substrate is provided, and the substrate includes an epitaxial growth surface. A buffer layer is grown on the epitaxial growth surface. A carbon nanotube layer is placed on the buffer layer. A first semiconductor layer, an active layer, and a second semiconductor layer are grown in that order on the buffer layer. A reflector and a first electrode are deposited on the second semiconductor layer in that order. The substrate and the buffer layer are removed. A second electrode is deposited on the first semiconductor layer.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: October 29, 2013
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 8569806
    Abstract: A unit pixel of an image sensor and a photo detector are disclosed. The photo detector of the present invention configured to absorb light can include: a light-absorbing part configured to absorb light by being formed in a floated structure; an oxide film being in contact with one surface of the light-absorbing part; a source being in contact with one side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; a drain facing the source so as to be in contact with the other side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; and a channel interposed between the source and the drain and configured to form flow of an electric current between the source and the drain.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: October 29, 2013
    Inventor: Hoon Kim
  • Patent number: 8567041
    Abstract: A heated resonator includes a base substrate, a piezoelectric piece having a thickness and a top side and a bottom side, a first electrode on the top side, a second electrode opposite the first electrode on the bottom side, an anchor connected between the piezoelectric piece and the base substrate, and a heater on the piezoelectric material. A thermal resistor region in the piezoelectric piece is between the heater and the anchor.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: October 29, 2013
    Assignee: HRL Laboratories, LLC
    Inventor: Christopher S. Roper
  • Patent number: 8563984
    Abstract: Device having reduced buffer leak on GaN substrate. In HEMT device, n-GaN (n-type GaN wafer) is used as substrate 11. Non-doped AlpGa1-pN layer with non-uniform composition p is formed on substrate 11 as buffer layer 12. On buffer layer 12, channel layer 13 of semi-insulating GaN and electron supply layer 14 of n-AlGaN are sequentially formed. In buffer layer 12, substrate connection region 121 where p=0 (GaN) is formed on lower end side, and active layer connection region 122 where value of p is also 0 (GaN) is formed on upper end side (channel layer 13 side). High Al composition region 123 where value of p is set to 1 (p=1) (AlN) is formed between substrate connection region 121 and active layer connection region 122. Resistivity of the high Al composition region 123 is highest in the buffer layer.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: October 22, 2013
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Ken Sato
  • Patent number: 8563337
    Abstract: A semiconductor device and methods of manufacturing the same are disclosed. Specifically, methods and devices for manufacturing optocouplers are disclosed. Even more specifically, methods and devices that deposit one or more encapsulant materials on optocouplers are disclosed. The encapsulant material may include silicone and the devices used to deposit the silicone may be configured to simultaneously deposit the silicone on different sides of the optocoupler, thereby reducing manufacturing steps and time.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: October 22, 2013
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Premkumar Jeromerajan, Gopinath Maasi, Tay Thiam Siew Gary
  • Patent number: 8563345
    Abstract: A method for forming a capacitive micromachined ultrasonic transducer (CMUT) includes forming multiple CMUT elements in a first semiconductor-on-insulator (SOI) structure. Each CMUT element includes multiple CMUT cells. The first SOI structure includes a first handle wafer, a first buried layer, and a first active layer. The method also includes forming a membrane over the CMUT elements and forming electrical contacts through the first handle wafer and the first buried layer. The electrical contacts are in electrical connection with the CMUT elements. The membrane could be formed by bonding a second SOI structure to the first SOI structure, where the second SOI structure includes a second handle wafer, a second buried layer, and a second active layer. The second handle wafer and the second buried layer can be removed, and the membrane includes the second active layer.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: October 22, 2013
    Assignee: National Semiconductor Corporated
    Inventors: Steven J. Adler, Peter Johnson, Gokhan Percin, Shahram Mostafazadeh
  • Patent number: 8558288
    Abstract: Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: October 15, 2013
    Assignee: Life Technologies Corporation
    Inventors: Jonathan M. Rothberg, Wolfgang Hinz, Kim L. Johnson
  • Patent number: 8558335
    Abstract: A solid-state imaging device includes a photoelectric conversion unit that is formed on a semiconductor substrate, a reading unit that reads signal charges of the photoelectric conversion unit, a gate insulating film and an electrode disposed thereon that constitute the reading unit, a light shielding film that covers the electrode, and an antireflection film that is formed on the photoelectric conversion unit and is constituted by films of four or more layers. The film of the lower layer of the antireflection film is also used as a stopper film during patterning, and a gap between the end of the light shielding film and the semiconductor substrate which is defined by interposing a plurality of films of the lower layer of the antireflection film is set so as to be smaller than the thickness of the gate insulating film.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: October 15, 2013
    Assignee: Sony Corporation
    Inventor: Mitsuhiro Nagano
  • Patent number: 8557625
    Abstract: A method for fabricating a thin film photovoltaic device. The method includes providing a substrate comprising an absorber layer and an overlying window layer. The substrate is loaded into a chamber and subjected to a vacuum environment. The vacuum environment is at a pressure ranging from 0.1 Torr to about 0.02 Torr. In a specific embodiment, a mixture of reactant species derived from diethylzinc species, water species and a carrier gas is introduced into the chamber. The method further introduces a diborane species using a selected flow rate into the mixture of reactant species. A zinc oxide film is formed overlying the window layer to define a transparent conductive oxide using the selected flow rate to provide a resistivity of about 2.5 milliohm-cm and less and an average grain size of about 3000 to 5000 Angstroms.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: October 15, 2013
    Assignee: Stion Corporation
    Inventor: Robert D. Wieting
  • Patent number: 8558326
    Abstract: Semiconductor devices having integrated nanochannels confined by nanometer spaced electrodes, and VLSI (very large scale integration) planar fabrication methods for making the devices. A semiconductor device includes a bulk substrate and a first metal layer formed on the bulk substrate, wherein the first metal layer comprises a first electrode. A nanochannel is formed over the first metal layer, and extends in a longitudinal direction in parallel with a plane of the bulk substrate. A second metal layer is formed over the nanochannel, wherein the second metal layer comprises a second electrode. A top wall of the nanochannel is defined at least in part by a surface of the second electrode and a bottom wall of the nanochannel is defined by a surface of the first electrode.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: October 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: Stefan Harrer, Stanislav Polonsky, Mark B. Ketchen, John A. Ott
  • Patent number: 8558234
    Abstract: Highly efficient, low energy, low light level imagers and photodetectors are provided. In particular, a novel class of Della-Doped Electron Bombarded Array (DDEBA) photodetectors that will reduce the size, mass, power, complexity, and cost of conventional imaging systems while improving performance by using a thinned imager that is capable of detecting low-energy electrons, has high gain, and is of low noise.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: October 15, 2013
    Assignee: California Institute of Technology
    Inventors: Shouleh Nikzad, Chris Martin, Michael E. Hoenk
  • Patent number: 8551800
    Abstract: Semiconductor structures including a movable switching element having a base disposed on a conductive pad, a body extending from the base, and an end laterally adjacent and spaced apart from a conductive contact are disclosed. Upon application of a threshold voltage, the movable switching element may deform toward the conductive contact via an electrical field, establishing electrical contact between the conductive pad and the conductive contact. Various methods may be used to form such semiconductor structures, and switching devices including such semiconductor structures. Memory devices and electronic systems include such switching devices.
    Type: Grant
    Filed: October 10, 2011
    Date of Patent: October 8, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Chandra V. Mouli
  • Patent number: 8551798
    Abstract: The present disclosure provides a microstructure device with an enhanced anchor and a narrow air gap. One embodiment of a microstructure device provided herein includes a layered wafer. The layered wafer includes a silicon handle layer, a buried oxide layer formed on the handle layer, and a silicon device layer formed on the buried oxide layer. A top oxide layer is formed on the device layer. The top oxide layer, the device layer, and the buried oxide layer are etched, thereby forming trenches to create an anchor and a microstructure device in the device layer. In process of fabricating the device, a thermal oxide layer is formed along sides of the microstructure device to enclose the microstructure device in the buried oxide layer, the top oxide layer and the thermal oxide layer. Then, a poly layer if formed to fill in the trenches and enclose the anchor. After the poly layer fills in the trenches, the oxide layers enclosing the microstructure device are etched away, releasing the microstructure device.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: October 8, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hsien Lin, Chia-Hua Chu, Chun-Wen Cheng
  • Publication number: 20130256813
    Abstract: The semiconductor device has a sensor unit including a sensing part, and a semiconductor substrate. The semiconductor substrate is bonded to the sensor unit through an insulation film such that the sensing part is disposed in an air-tightly sealed chamber provided between a recessed portion of the semiconductor substrate and the sensor unit. A surface of the semiconductor substrate provided on a periphery of the recessed portion includes a boundary region at a perimeter of the recessed portion and a bonding region on a periphery of the boundary region. The bonding region has an area greater than an area of the boundary region. The bonding region of the semiconductor substrate is bonded to the sensor unit through the insulation film.
    Type: Application
    Filed: March 26, 2013
    Publication date: October 3, 2013
    Applicant: DENSO CORPORATION
    Inventor: Yumi MARUYAMA
  • Patent number: 8546899
    Abstract: A light receiving element includes a waveguide that includes a waveguide core, a multi-mode interference waveguide that has a width larger than a width of the waveguide, the multi-mode interference waveguide receiving a first light from the waveguide core at a first end, and a photodetection portion that includes a first semiconductor layer and an absorption layer disposed on the first semiconductor layer, the first semiconductor layer including at least one layer and receiving a second light from the multi-mode interference waveguide at a second end, the absorption layer being disposed above the first semiconductor layer and absorbing the second light. A distance from the first end of the multi-mode interference waveguide to the second end of the photodetection portion is longer than 70% of a first length and shorter than 100% of the first length, the first length being a length where self-imaging occurs in the multi-mode interference waveguide.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: October 1, 2013
    Assignee: Fujitsu Limited
    Inventor: Kazumasa Takabayashi
  • Patent number: 8541850
    Abstract: In accordance with one embodiment of the present disclosure, a semiconductor substrate includes complementary metal-oxide-semiconductor (CMOS) circuitry disposed outwardly from the semiconductor substrate. An electrode is disposed outwardly from the CMOS circuitry. The electrode is electrically coupled to the CMOS circuitry. A resonator is disposed outwardly from the electrode. The resonator is operable to oscillate at a resonance frequency in response to an electrostatic field propagated, at least in part, by the electrode.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: September 24, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Arun K. Gupta, Lance W. Barron, William C. McDonald
  • Patent number: 8535965
    Abstract: The present invention provides a method for forming by plasma CVD a silicon nitride film that can be formed over heat-sensitive elements as well as an electroluminescent element and that has favorable barrier characteristics. Further, the present invention also provides a semiconductor device, a display device and a light-emitting display device formed by using the silicon nitride film. In the method for forming a silicon nitride film by plasma CVD, silane (SiH4), nitrogen (N2) and a rare gas are introduced into a deposition chamber in depositing, and the reaction pressure is within the range from 0.01 Torr to 0.1 Torr.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: September 17, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinji Maekawa, Tetsuya Kakehata, Yuuichi Takehara
  • Patent number: 8535966
    Abstract: A MEMS structure and methods of manufacture. The method includes forming a sacrificial metal layer at a same level as a wiring layer, in a first dielectric material. The method further includes forming a metal switch at a same level as another wiring layer, in a second dielectric material. The method further includes providing at least one vent to expose the sacrificial metal layer. The method further includes removing the sacrificial metal layer to form a planar cavity, suspending the metal switch. The method further includes capping the at least one vent to hermetically seal the planar cavity.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Felix P. Anderson, Thomas L. McDevitt, Anthony K. Stamper
  • Patent number: 8536663
    Abstract: A metal mesh lid MEMS package includes a substrate, a MEMS electronic component coupled to the substrate, and a metal mesh lid coupled to the substrate with a lid adhesive. The metal mesh lid includes a polymeric lid body having a top port formed therein and a metal mesh cap coupled to the lid body. The metal mesh cap covers the top port and serves as both a particulate filter and a continuous conductive shield for EMI/RF interferences. Further, the metal mesh cap provides a locking feature for the lid adhesive to maximize the attach strength of the metal mesh lid to the substrate.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: September 17, 2013
    Assignee: Amkor Technology, Inc.
    Inventors: Bob Shih-Wei Kuo, Russell Shumway, Louis B. Troche, Jr.
  • Patent number: 8535967
    Abstract: A method for etching a diaphragm pressure sensor based on a hybrid anisotropic etching process. A substrate with an epitaxial etch stop layer can be etched utilizing an etching process in order to form a diaphragm at a selective portion of the substrate. The diaphragm can be oriented at an angle (e.g., 45 degree) with respect to the substrate in order to avoid an uncertain beveled portion in a stress/strain field of the diaphragm. The diaphragm can be further etched utilizing an etch finishing process to create an anisotropic edge portion on the major areas of the diaphragm and optimize the thickness and size of the diaphragm. Such an approach provides an enhanced diaphragm structure with respect to a wide range of pressure sensor applications.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: September 17, 2013
    Assignee: Honeywell International Inc.
    Inventor: Robert Higashi
  • Patent number: 8530264
    Abstract: Methods of fabricating complementary metal-oxide-semiconductor (CMOS) imagers for backside illumination are disclosed. In one embodiment, the method may include forming at a front side of a substrate a plurality of high aspect ratio trenches having a predetermined trench depth, and forming at the front side of the substrate a plurality of photodiodes, where each photodiode is adjacent at least one trench. The method may further include forming an oxide layer on inner walls of each trench, removing the oxide layer, filling each trench with a highly doped material, and thinning the substrate from a back side opposite the front side to a predetermined final substrate thickness. In some embodiments, the substrate may have a predetermined doping profile, such as a graded doping profile, that provides a built-in electric field suitable to guide the flow of photogenerated minority carriers towards the front side.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: September 10, 2013
    Assignee: IMEC
    Inventors: Koen De Munck, Kiki Minoglou, Joeri De Vos
  • Patent number: 8530981
    Abstract: A low-cost microelectromechanical system (MEMS) device has a mass-produced carrier fabricated as a pre-molded leadframe so that the space of the leadframe center is filled with compound and a two-tier stepped recess is created in the center. The first tier is filled by an inset with a first perforation and a second perforation. An integrated circuit chip with an opening and a membrane at the end of the opening, operable as a pressure sensor, microphone, speaker, etc., is assembled on the inset so that the chip opening is aligned with the first perforation. The chip is protected by a cover transected by a vent aligned with the second inset perforation. An air channel extends from the ambient exterior through the vent and the second perforation to the second tier recess, which acts as a channel and connects to the first perforation and the chip opening to the membrane.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: September 10, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: James Richard Huckabee, Ray H. Purdom
  • Patent number: 8533634
    Abstract: A method of manufacturing an exposure mask includes generating or preparing flatness variation data relating to a mask blanks substrate to be processed into an exposure mask, the flatness variation data being data relating to change of flatness of the mask blank substrate caused when the mask blank substrate is chucked by a chuck unit of an exposure apparatus, generating position correction, data of a pattern to be drawn on the mask blanks substrate based on the flatness variation data such that a mask pattern of the exposure mask comes to a predetermined position in a state that the exposure mask is chucked by the chuck unit, and drawing a pattern on the mask blanks substrate, the drawing the pattern including drawing the pattern with correcting a drawing position of the pattern and inputting drawing data corresponding to the pattern and the position correction data into a drawing apparatus.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: September 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masamitsu Itoh
  • Publication number: 20130228880
    Abstract: Embodiments of the present invention provide a method for manufacturing an integrated sensor structure. In one step, a semiconductor substrate having integrated readout electronics and a metallization structure is provided, the metallization structure including tungsten and being exposed on a surface of the semiconductor substrate. In another step, a sensor layer is deposited onto the surface of the semiconductor substrate, the semiconductor substrate having the integrated readout electronics and the metallization structure being exposed, when depositing the sensor layer, to a temperature which is above a maximum temperature used when generating the integrated readout electronics such that the sensor layer is connected to the integrated readout electronics via the metallization structure.
    Type: Application
    Filed: February 22, 2013
    Publication date: September 5, 2013
    Applicant: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventor: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
  • Patent number: 8525276
    Abstract: The invention provides combination semiconductor and plasma devices, including transistors and phototransistors. A preferred embodiment hybrid plasma semiconductor device has active solid state semiconductor regions; and a plasma generated in proximity to the active solid state semiconductor regions. Devices of the invention are referred to as hybrid plasma-semiconductor devices, in which a plasma, preferably a microplasma, cooperates with conventional solid state semiconductor device regions to influence or perform a semiconducting function, such as that provided by a transistor. The invention provides a family of hybrid plasma electronic/photonic devices having properties previously unavailable. In transistor devices of the invention, a low temperature, glow discharge is integral to the hybrid transistor. Example preferred devices include hybrid BJT and MOSFET devices.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: September 3, 2013
    Assignee: The Board of Trustees of the University of California
    Inventors: Paul A. Tchertchian, Clark J. Wagner, J. Gary Eden
  • Patent number: 8525173
    Abstract: A means of forming unevenness for preventing specular reflection of a pixel electrode, without increasing the number of process steps, is provided. In a method of manufacturing a reflecting type liquid crystal display device, the formation of unevenness (having a radius of curvature r in a convex portion) in the surface of a pixel electrode is performed by the same photomask as that used for forming a channel etch type TFT, in which the convex portion is formed in order to provide unevenness to the surface of the pixel electrode and give light scattering characteristics.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: September 3, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Publication number: 20130221452
    Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A conductive layer can be formed over the encapsulant and the semiconductor die. A transmissive layer can be formed over the semiconductor die. An interconnect structure can be formed through the encapsulant and electrically connected to the conductive layer, whereby the interconnect structure is formed off to only one side of the semiconductor die.
    Type: Application
    Filed: March 29, 2013
    Publication date: August 29, 2013
    Applicant: Stats ChipPAC, Ltd.
    Inventor: Stats ChipPAC, Ltd.
  • Publication number: 20130221455
    Abstract: An embedded micro-electro-mechanical system (MEMS) (100) comprising a semiconductor chip (101) embedded in an insulating board (120), the chip having a cavity (102) including a radiation sensor MEMS (105), the opening (104) of the cavity at the chip surface covered by a plate (110) transmissive to the radiation (150) sensed by the MEMS. The plate surface remote from the cavity having a bare central area, to be exposed to the radiation sensed by the MEMS in the cavity, and a peripheral area covered by a metal film (111) touching the plate surface and a layer (112) of adhesive stacked on the metal film.
    Type: Application
    Filed: February 27, 2012
    Publication date: August 29, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Christopher D. Manack, Frank Stepniak, Sreenivasan K. Koduri
  • Patent number: 8519392
    Abstract: By controlling the luminance of light emitting element not by means of a voltage to be impressed to the TFT but by means of controlling a current that flows to the TFT in a signal line drive circuit, the current that flows to the light emitting element is held to a desired value without depending on the characteristics of the TFT. Further, a voltage of inverted bias is impressed to the light emitting element every predetermined period. Since a multiplier effect is given by the two configurations described above, it is possible to prevent the luminance from deteriorating due to a deterioration of the organic luminescent layer, and further, it is possible to maintain the current that flows to the light emitting element to a desired value without depending on the characteristics of the TFT.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: August 27, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Mai Akiba, Jun Koyama
  • Patent number: 8518732
    Abstract: A method for providing a semiconductor structure includes forming a sacrificial structure by etching a plurality of trenches from a first main surface of a substrate. The method further includes covering the plurality of trenches at the first main surface with a cover material to define cavities within the substrate, removing a part of the substrate from a second main surface opposite to the first main surface to a depth at which the plurality of trenches are present, and etching away the sacrificial structure from the second main surface of the substrate.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: August 27, 2013
    Assignee: Infineon Technologies AG
    Inventors: Thoralf Kautzsch, Stefan Kolb, Boris Binder, Bernd Foeste, Marco Mueller
  • Patent number: 8519491
    Abstract: The present invention discloses a MEMS sensing device which comprises a substrate, a MEMS device region, a film, an adhesive layer, a cover, at least one opening, and a plurality of leads. The substrate has a first surface and a second surface opposite the first surface. The MEMS device region is on the first surface, and includes a chamber. The film is overlaid on the MEMS device region to seal the chamber as a sealed space. The cover is mounted on the MEMS device region and adhered by the adhesive layer. The opening is on the cover or the adhesive layer, allowing the pressure of the air outside the device to pressure the film. The leads are electrically connected to the MEMS device region, and extend to the second surface.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: August 27, 2013
    Assignee: Pixart Imaging Incorporation, R.O.C.
    Inventors: Chuan-Wei Wang, Ming-Han Tsai
  • Patent number: 8519425
    Abstract: A light-emitting device includes a substrate and a planarizing film above the substrate. The planarizing film has a recessed portion between non-recessed portions. A bottom electrode layer is above the non-recessed portions. A semiconductor interlayer is above the bottom electrode layer. A filling layer is above the recessed portion. The filling layer comprises a same material as the semiconductor layer and has an inner portion between outer portions. A bank is above the recessed portion of the planarizing film and edge portions of the bottom electrode layer, with each of the edge portions of the bottom electrode layer neighboring the recessed portion of the planarizing film. The filling layer inner portion has a thickness of t1, the filling layer outer portions have a thickness of t2, and t1 is greater than t2.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: August 27, 2013
    Assignee: Panasonic Corporation
    Inventor: Shuhei Yada
  • Patent number: 8518733
    Abstract: Provided is a method of manufacturing an electromechanical transducer having a reduced variation in a breakdown strength caused by a variation in flatness of an insulating layer. In the method of manufacturing the electromechanical transducer, a first insulating layer is formed on a first substrate, a barrier wall is formed by removing a part of the first insulating layer, and a second insulating layer is formed on a region of the first substrate after the part of the first insulating layer has been removed. Next, a gap is formed by bonding a second substrate on the barrier wall, and a vibration film that is opposed to the second insulating layer via the gap is formed from the second substrate. In the forming of the barrier wall, a height on a gap side in a direction vertical to the first substrate becomes lower than a height of a center portion.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: August 27, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Ayako Kato, Kazutoshi Torashima
  • Patent number: 8513043
    Abstract: The present invention generally relates to methods for producing MEMS or NEMS devices and the devices themselves. A thin layer of a material having a lower recombination coefficient as compared to the cantilever structure may be deposited over the cantilever structure, the RF electrode and the pull-off electrode. The thin layer permits the etching gas introduced to the cavity to decrease the overall etchant recombination rate within the cavity and thus, increase the etching rate of the sacrificial material within the cavity. The etchant itself may be introduced through an opening in the encapsulating layer that is linearly aligned with the anchor portion of the cantilever structure so that the topmost layer of sacrificial material is etched first. Thereafter, sealing material may seal the cavity and extend into the cavity all the way to the anchor portion to provide additional strength to the anchor portion.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: August 20, 2013
    Assignee: Cavendish Kinetics Inc.
    Inventors: Mickael Renault, Joseph Damian Gordon Lacey, Vikram Joshi, Thomas L. Maguire