Abstract: A source electrode, a gate electrode, and a drain electrode formed on a front face active region of a semiconductor substrate in a shape of teeth of a comb are covered with an insulating film such as polyimede etc., as well as all of the upper surface and the side surfaces of the insulating film are covered with a metal protective film. Via hole receiving pads connected to the source electrode, the gate electrode, and the drain electrode are respectively connected to bonding pads on a reveres face of the semiconductor substrate through via holes.

Abstract: Methods of forming integrated circuit devices (e.g., memory devices) include the use of preferred self-aligned contact hole fabrication steps. These steps improve process reliability by reducing the likelihood that contact holes will become misaligned to underlying integrated circuit device structures and thereby potentially expose the structures in an adverse manner. Typical methods include the steps of forming a plurality of interconnection patterns on a substrate and then covering a surface of the interconnection patterns and a portion of the substrate with a capping insulating layer such as silicon nitride layer. The capping insulating layer is then covered with an upper interlayer insulating layer different from the capping insulating layer. The upper interlayer insulating layer and the capping insulating layer are then dry-etched in sequence to form a first narrow contact hole that exposes the substrate, but preferably does not expose the interconnection patterns.

Abstract: A semiconductor device on a SOI and a method for manufacturing the same are provided. The semiconductor device includes a semiconductor wafer having a SOI structure including an insulating layer having a predetermined thickness and a monocrystalline silicon layer formed on the insulating layer, an isolation insulating layer formed on the insulating layer on the semiconductor wafer, a gate comprised of a gate dielectric layer and a gate conductive layer, which are sequentially stacked on the monocrystalline silicon layer, insulating layer spacers formed at the sidewalls of the gate, and a source junction and a drain junction asymmetrically formed at either side of the gate between the isolation insulating layer spacers and the insulating layer. In the semiconductor device formed on a SOI, source and drain junctions are formed at either side of a gate to be asymmetrical, and thus a ground of a transistor is formed on the SOI, and thus the electrical characteristics of the semiconductor device are improved.

Abstract: A field effect transistor in which a continuous semiconductor layer comprises:

Abstract: This invention is embodied in an improved process for growing high-quality silicon dioxide layers on silicon by subjecting it to a gaseous mixture of nitrous oxide (N2O) and ozone (O3). The presence of O3 in the oxidizing ambiance greatly enhances the oxidation rate compared to an ambiance in which N2O is the only oxidizing agent. In addition to enhancing the oxidation rate of silicon, it is hypothesized that the presence of O3 interferes with the growth of a thin silicon oxynitride layer near the interface of the silicon dioxide layer and the unreacted silicon surface which makes oxidation in the presence of N2O alone virtually self-limiting. The presence of O3 in the oxidizing ambiance does not impair oxide reliability, as is the case when silicon is oxidized with N2O in the presence of a strong, fluorine-containing oxidizing agent such as NF3 or SF6.

Abstract: The invention includes a method of forming a transistor gate. One or more conductive materials are formed over a semiconductor substrate, and a block is formed over the one or more conductive materials. The block comprises a photoresist mass and a material other than photoresist which is against the photoresist. A pattern is transferred from the block to the one or more conductive materials to pattern a transistor gate construction from the one or more conductive materials.

Abstract: A method of fabricating a layered structure including a substrate, a first semiconductor layer with a first thermal expansion coefficient &agr;A, and a second semiconductor layer with a second thermal expansion coefficient &agr;B deposited on the first semiconductor layer, wherein &agr;Ais greater than &agr;B or smaller than &agr;B, includes: forming the first semiconductor layer, the second semiconductor layer, and a third semiconductor layer with a third thermal expansion coefficient &agr;C in this order on the substrate at a first temperature using a film deposition technique such as MOCVD, thereby forming a structural body including the substrate and the first to third semiconductor layers, wherein &agr;C is greater than &agr;B if &agr;A is greater than &agr;B or &agr;C is smaller than &agr;B if &agr;A is smaller than &agr;B; cooling the structural body to a second temperature, which is lower than the first temperature; and removing the third semiconductor layer from the structural body to expose the seco

Abstract: In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.

Abstract: A method of forming a memory transistor includes providing a substrate comprising semiconductive material and forming spaced-apart source/drain structures. At least one of the source/drain structures forms a Schottky contact to the semiconductive material. The method also includes forming a memory gate between the spaced-apart source/drain structures and forming a control gate disposed operatively over the memory gate.

Abstract: A method of forming a dielectric layer on a semiconductor substrate, comprised with multiple dielectric constants and multiple equivalent oxide thicknesses (EOT), has been developed. After formation of a high dielectric constant (high k), layer, on a semiconductor substrate, a first region of the high k layer is subjected to a process directed at incorporating elements into a top portion of the high k layer, while a second region of the high k layer remains protected during this procedure. An anneal treatment results in the processed high k layer now exhibiting a different dielectric constant, as well as a different EOT, than the unprocessed, second region of the high k layer, not exposed to the above procedures.

Abstract: A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on the main surface of the semiconductor substrate, which second region is different from the first region. An internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is different from an internal stress generated in the channel formation region of the p channel conductivity type field effect transistor. The internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is a tensile stress, while the internal stress generated in the channel formation region of the p channel conductivity type field effect transistor is a compressive stress.

Abstract: A silicon substrate is coated with one or more layers of resist. First and second circuit patterns are exposed in sequence, where the second pattern crosses the first pattern. The patterned resist layers are developed to open holes which extend down to the substrate only where the patterns cross over each other. These holes provide a mask suitable for implanting single phosphorous ions in the substrate, for a solid state quantum computer. Further development of the resist layers provides a mask for the deposition of nanoelectronic circuits, such as single electron transistors, aligned to the phosphorous ions.

Abstract: An exposed top end of a vertical oxide spacer is removed, and a nitride layer is deposited in an amount sufficient to replace the removed portion prior to exposing a memory device to a self align contact etch process. The nitride layer may be used to prevent a short circuit through the oxide spacer. The present invention also provides memory devices that have a gate stack, a vertical spacer adjacent to the gate stack, in which the vertical spacer has a lower portion comprising an oxide and an upper portion comprising a nitride, and a continuous nitride layer overlaying the vertical spacer and the gate stack. The present invention further provides methods of fabricating the above devices, and processor systems which include the devices.

Abstract: A method for forming a MOSFET having an elevated source/drain structure is described. A sacrificial oxide layer is provided on a substrate. A polish stop layer is deposited overlying the sacrificial oxide layer. An oxide layer is deposited overlying the polish stop layer. An opening is formed through the oxide layer and the polish stop layer to the sacrificial oxide layer. First polysilicon spacers are formed on sidewalls of the opening wherein the first polysilicon spacers form an elevated source/drain structure. Second polysilicon spacers are formed on the first polysilicon spacers. The oxide layer and sacrificial oxide layer exposed within the opening are removed. An epitaxial silicon layer is grown within the opening. A gate dielectric layer is formed within the opening overlying the second polysilicon spacers and the epitaxial silicon layer. A gate material layer is deposited within the opening.

Abstract: A method for fabricating a semiconductor device, in which a sufficient misalignment margin is obtained when forming interconnections and contact holes, is provided. Dielectric layer patterns which define recesses in which damascene interconnections are to be formed, are formed. Then, first contact holes between the dielectric layer patterns are etched, and the first contact holes and the recesses are concurrently filled with a conductive material. The recesses can be filled with the conductive material by performing an etch-back process. The dielectric layer patterns are then etched, thereby forming the damascene interconnections and concurrently covering only a region in which second contact holes are to be formed with the dielectric layer patterns. Spaces between the dielectric layer patterns are filled with a mask layer, and then the dielectric layer patterns are selectively removed from the resultant structure, thereby forming the second contact holes aligned with the damascene interconnections.

Abstract: A method of fabricating discrete NROM cell by self aligned process, comprising the steps of providing a substrate with already formed an ONO layer, wherein the ONO layer includes a top oxide layer, a nitride layer and a bottom oxide layer; defining the top oxide layer; defining a plurality of disposable spacers; implanting a bit line and pocket implant by self-aligned process; defining the nitride layer according to the disposable spacers; defining the bottom oxide layer according to the discrete nitride layer to form a plurality of discrete pillars, so that a channel is formed between two discrete pillars; forming a plurality of channel oxides in the channels; and forming an oxide layer over the discrete channel oxides and the nitrite layer. The method of fabricating discrete NROM cell according to the invention can solve the problem of the electrons being trapped in the nitride layer of NROM cell, and also control the implant and ONO structure at exactly mutual positions.

Abstract: High quality epitaxial layers of monocrystalline oxide materials (24) are grown overlying monocrystalline substrates such as large silicon wafers (22) using RHEED information to monitor the growth rate of the growing film. The monocrystalline oxide layer (24) may be used to form a compliant substrate for monocrystalline growth of additional layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer (24) on a silicon wafer (22) spaced apart from the silicon wafer (22) by an amorphous interface layer of silicon oxide (28). The amorphous interface layer (28) dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer (24).

Abstract: A method is provided to produce thin film transistors (TFTs) on polycrystalline films having a single predominant crystal orientation. A layer of amorphous silicon is deposited over a substrate to a thickness suitable for producing a desired crystal orientation. Lateral-seeded excimer laser annealing (LS-ELA) is used to crystallize the amorphous silicon to form a film with a preferred crystal orientation. The crystallized film is then polished to a desired thickness. A gate is formed overlying the polycrystalline film. The polycrystalline film is doped to produce source and drain regions.

Abstract: A fabrication method for a mask read only memory device is described. The method provides a substrate, and a doped conductive layer is formed on the substrate. After this, the doped conductive layer is patterned to form a plurality of bar-shaped doped conductive layers, followed by forming a dielectric layer on the substrate and on the bar-shaped conductive layers by thermal oxidation. A plurality of diffusion regions are concurrently formed under the bar-shaped conductive layers in the substrate. A patterned conductive layer is further formed on the dielectric layer.

Abstract: A gate structure of a transistor is fabricated with an additional barrier formed on a metal layer of the gate structure before the deposition of a silicon oxide layer. Applying this barrier layer on the metal layer before the deposition of the silicon oxide layer prevents an oxidation of the metal during the deposition of the silicon oxide layer. A lowering of the conductivity of the metal layer or a loss of metal through sublimating metal oxide is thereby prevented. As a result, in particular the performance of the gate structure or of the transistor is improved further. In addition, disturbing coupling effects in the circuit are significantly reduced by the use of the silicon oxide cap.

Abstract: The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.

Abstract: The invention is to provide a high-productivity method for fabricating a TFT device having different LDD structures on one and the same substrate, and the TFT device. Specifically, the invention provides a novel TFT structure, and a high-productivity method for fabricating it. A Ta film or a Ta-based film having good heat resistance is used for forming interconnections, and the interconnections are covered with a protective film. The interconnections can be subjected to heat treatment at high temperatures (400 to 700° C.), and, in addition, the protective film serves as an etching stopper. In the peripheral driving circuit portion in the device, TFTs having an LDD structure are disposed in a self-aligned process in which is used side walls 126 and 127; while in the pixel matrix portion therein, TFTs having an LDD structure are disposed in a non-self-aligned process in which is used an insulator 125.

Abstract: A semiconductor device including an IGFET (insulated gate field effect transistor) (30) is disclosed. IGFET (30) may include a source/drain area (15) having an impurity concentration distribution that may be formed shallower at a higher concentration than the impurity concentration distribution in another source/drain area (7). A gate oxide film may include a first gate oxide film (5) adjacent to source/drain area (7) and a second gate oxide film (12) adjacent to source drain area (15). Second gate oxide film (12) may be thinner than first gate oxide film (5). An impurity concentration distribution of a second channel impurity area (11) under second gate oxide film (12) may be at a higher concentration than an impurity concentration distribution of a first channel impurity area (9) under first gate oxide film (5). In this way, an electric field at a PN junction of source/drain area (7) may be reduced.

Abstract: In a substrate, a portion for forming wiring extending to a connection terminal is provided with a recess. The connection terminal and the wiring are covered by an interlayer insulating film, and an opening is provided in a portion corresponding to the connection terminal. Thereby, a difference in level between the connection terminal and the wiring extending thereto is reduced.

Abstract: A method for forming first and second linear structures of a first composition that meet at right angles, there being a gap at the point at which the structures meet. The linear structures are constructed on an etchable crystalline layer having the first composition. First and second self-aligned nanowires of a second composition are grown on this layer and used as masks for etching the layer. The self-aligned nanowires are constructed from a material that has an asymmetric lattice mismatch with respect to the crystalline layer. The gap is sufficiently small to allow one of the structures to act as the gate of a transistor and the other to form the source and drain of the transistor. The gap can be filled with electrically switchable materials thereby converting the transistor to a memory cell.

Abstract: A method of fabricating a memory cell is described in which an access transistor is first formed on an SOI substrate. The access transistor contains source and drain regions in a semiconductor material layer of the substrate and at least one gate stack which includes a gate region electrically connected with a word line. At least one capacitor is formed con a first side of the substrate and is electrically connected to one of the source and drain regions. At least one bit line conductor is formed on the reverse or flip side of the substrate, wherein the bit line conductor is electrically connected to the other of the source and drain regions. Self-aligned contact openings are formed through insulative material over the substrate to provide vias for the electrical connections for each of the capacitor and bit line conductor. These contact openings and the deposited contact material are substantially preserved throughout the entire fabrication process.

Abstract: A method of fabricating an RF lateral MOS device, comprising the following steps. A substrate having a gate oxide layer formed thereover is provided. A first layer of polysilicon is formed over the gate oxide layer. A second layer of material is formed over the polysilicon layer. The polysilicon and the second layer of material are patterned to form a gate having exposed sidewalls with the gate having a lower patterned polysilicon layer and an upper patterned second material layer. Sidewall spacers are formed on the exposed sidewalls of the gate. The upper patterned second material layer of the gate is removed to form a cavity above the patterned polysilicon layer and between the sidewall spacers. A planarized copper plug is formed within the cavity.

Abstract: The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.

Abstract: A method of producing an integrated circuit with a carbon nanotube is disclosed. The integrated circuit includes a source, a drain, and a gate, and the source and the drain are positioned on the gate. A catalytic material is deposited onto the source. The catalytic material is then subjected to chemical vapor deposition. This initiates growth of the carbon nanotube such that the carbon nanotube extends from the source. Next, the carbon nanotube is bent toward the integrated circuit such that the carbon nanotube extends between the source and the drain to render the circuit operable.

Abstract: This invention is embodied in an improved process for growing high-quality silicon dioxide layers on silicon by subjecting it to a gaseous mixture of nitrous oxide (N2O) and ozone (O3). The presence of O3 in the oxidizing ambiance greatly enhances the oxidation rate compared to an ambiance in which N2O is the only oxidizing agent. In addition to enhancing the oxidation rate of silicon, it is hypothesized that the presence of O3 interferes with the growth of a thin silicon oxynitride layer near the interface of the silicon dioxide layer and the unreacted silicon surface which makes oxidation in the presence of N2O alone virtually self-limiting. The presence of N2O in the oxidizing ambiance does not impair oxide reliability, as is the case when silicon is oxidized with N2O in the presence of a strong, fluorine-containing oxidizing agent such as NF3 or SF6.

Abstract: An electric double layer capacitor including at least one pair of polarizable electrodes connected to current collectors, a separator made of ion-permeable but electron-insulating material interposed between the electrodes in each pair of electrodes, and a liquid electrolyte. According to the invention the electrodes include a layer of carbon particles having a narrow distribution of nanopores therein, the pore sizes of the nanopores being adapted to fit the ion sizes of the electrolyte. The invention also relates to a method of manufacturing such a supercapacitor.

Abstract: A method of mass-producing a solid state device comprises supplying a solid state material substrate; providing two adjacent semiconductor pockets on the substrate; and forming a gate layer less than 3 to 40 Angstroms thick. The gate layer has atomically smooth major surfaces, and perfectly bonded onto the substrate to bridge a gap between the two semiconductor pockets.

Abstract: A semiconductor device has a semiconductor substrate and a conductive layer formed above the semiconductor substrate. The conductive layer has a silicon film, a silicide film formed on the silicon film, and a high melting-point metal film formed on the silicide film. The silicon film has a non-doped layer, which does not contain impurities, and an impurity layer which is formed on the non-doped layer and contains impurities. The silicide film is formed on the impurity layer of the silicon film.

Abstract: A method for fabricating a semiconductor device is disclosed. In a high speed device structure consisting of a salicide, in order to fabricate a device having at least two gate oxide structures in the identical chip, an LDD region of a core device region is formed, and an ion implant process for forming the LDD region of an input/output device region having a thick gate oxide and a process for forming a source/drain region at the rim of a field oxide of the core device region having a thin gate oxide are performed at the same time, thereby increasing a depth of a junction region. Thus, the junction leakage current is decreased in the junction region of the peripheral circuit region, and the process is simplified. As a result, a process yield and reliability of the device are improved.

Abstract: A method for forming a non-volatile memory (NVM) device, the method including forming two diffusion areas in a substrate, said diffusion areas forming a channel therebetween, the channel being adapted to permit movement of primary electrons to at least one of the diffusion areas, forming a non-conducting charge trapping layer at least over the channel, and managing at least one of movement of secondary electrons from the substrate towards the charge trapping layer and a punch-through voltage in the substrate by controlling a position of a concentration of an electron acceptor dopant in the substrate.

Abstract: In a profile extraction method, a long channel profile is first extracted through an initial profile generating stage and a long channel profile extraction stage. In a following two-dimensional profile extraction stage, a two-dimensional channel profile extraction stage and a source/drain profile extraction stage are repeated to extract an optimized two-dimensional channel profile and an optimized source/drain profile. In the two-dimensional channel profile extraction stage, a two-dimensional channel profile is extracted from the gate length dependency of the threshold voltage. In addition, in the source/drain profile extraction stage, a source/drain profile is extracted from the substrate bias voltage dependency of the threshold voltage—gate length characteristics.

Abstract: A method for forming a thin film transistor with lightly doped drain structure comprising the steps of forming a gate insulating layer and a gate electrode on a polysilicon layer; forming a photoresist layer with a predetermined thickness on the gate electrode and on a portion of the polysilicon layer; and implanting first conductive type impurities into the polysilicon layer so as to form a first ion-implant region and a second ion-implant region, wherein the doping concentration of the second ion-implant region is higher than that of the first ion-implant region.

Abstract: The present invention contemplates methods of bonding devices that produce sonic energy to polymer articles, the bonded articles themselves, methods for fabricating a semiconductor processing apparatus, and the apparatus itself. The present invention provides for an apparatus comprised of polymers, which is not susceptible to corrosion and permit the transmission of sonic energy through the walls of the apparatus. The polymer can be, for example, a fluoropolymer.

Abstract: A method of forming metal contacts in a semiconductor device having an active metal contact region and a bit line contact region is provided. In the method, a contact pad is formed in the active metal contact region and the bit line contact region using a conductive plug. An etch stopper is formed on the upper sides of the conductive plug. A portion of a lower interlayer dielectric layer is etched so that the etch stopper protrudes above the lower interlayer dielectric layer. A bit line stack is formed in the bit line contact region. An etch stopper is formed in the active metal contact region. An upper interlayer dielectric layer is etched to expose the surfaces of the etch stopper and bit line capping layer pattern of the bit line stack. The exposed surfaces of the etch stopper and bit line capping layer pattern are etched to form a contact hole which exposes the conductive plug and a bit line conductive layer of the bit line stack. The contact hole is filled with a conductive layer.

Abstract: A circuit isolation technique that uses implanted ions in embedded portions of a wafer substrate to lower the resistance of the substrate under circuits formed on the wafer or portions of circuits formed on the wafer to prevent the flow of injected currents across the substrate. The embedded ions provide low resistance regions that allow injected currents from a circuit to flow directly to a ground potential in the same circuit rather than flowing across the substrate to other circuits. High energy implantation processes on the order of 1 MeV to 3 MeVs can be used to implant the ions in embedded regions. Multiple energy levels can be used to provide thick embedded layers either prior to or after application of an epitaxial layer. Various masking materials can be used to mask the isolation regions during the implantation process, including hard masking materials such as silicon dioxide or silicon nitride, poly-silicon or an amorphous silicon layer, and a photoresist layer.

Abstract: A semiconductor device containing a polycrystalline silicon thin film wherein crystal grains of the silicon thin film have mainly a columnar structure and a crystal orientation of individual crystal grains is almost in a uniform direction can be produced by depositing a non-impurity-doped silicon thin film or an impurity layer on an interface of underlying film, followed by deposition of impurity-doped silicon thin film, if necessary, followed by heat treatment for polycrystallization.

Abstract: An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density.

Abstract: A new device and technique to realize an improved integrated circuit device incorporates an improved polysilicon upper surface. This improvement is achieved by approximately planarizing an upper surface of the polysilicon layer. First, the polysilicon layer is preferably formed as a relatively thicker layer as compared to the layer thickness in a conventional device. Then a portion of the polysilicon layer is removed, preferably utilizing a chemical mechanical polish technique. Thus, this embodiment achieves a relatively planarized upper surface of the polysilicon layer. Then, for example, a conventional metal or silicide layer may be formed upon the relatively planarized polysilicon layer. This approximately planarized upper surface of the polysilicon layer allows for a silicide layer to be formed with a relative reduction in the amount and/or severity of the conventional word line voids and seams.

Abstract: A method for fabricating a MOSFET device having a metal gate with an ultra shallow junction and allowing the application of a self-aligned contact. A sacrificial gate is formed on a silicon substrate, as is a first silicon epitaxial layer, which is thinner than the sacrificial gate. Elevated source/drain regions are formed on the silicon substrate by implanting desired impurity ions. An interlayer insulating film is deposited over the resultant structure and polished to expose the sacrificial gate. A groove is formed in which a gate insulating film and a metal film are deposited. The metal film, the gate insulating film and the interlayer insulating film are polished until the first silicon epitaxial layer is exposed. A second silicon epitaxial layer is then formed on the first silicon epitaxial layer.

Abstract: An integrated microelectromechanical system comprises at least one MOSFET interconnected to at least one MEMS device on a common substrate. A method for integrating the MOSFET with the MEMS device comprises fabricating the MOSFET and MEMS device monolithically on the common substrate. Conveniently, the gate insulator, gate electrode, and electrical contacts for the gate, source, and drain can be formed simultaneously with the MEMS device structure, thereby eliminating many process steps and materials. In particular, the gate electrode and electrical contacts of the MOSFET and the structural layers of the MEMS device can be doped polysilicon. Dopant diffusion from the electrical contacts is used to form the source and drain regions of the MOSFET. The thermal diffusion step for forming the source and drain of the MOSFET can comprise one or more of the thermal anneal steps to relieve stress in the structural layers of the MEMS device.

Abstract: A method and apparatus are provided for improving a breakdown voltage of a semiconductor device. The method includes the steps of coupling an electrode of the silicon-carbide diode to a drift layer of the semiconductor device through a charge transfer junction, said drift layer being of a first doping type and providing a junction termination layer of a relatively constant thickness in direct contact with the drift layer of the semiconductor device and in direct contact with an outside edge of the charge transfer junction, said junction termination layer extending outwards from the outside edge of the charge transfer junction, said junction termination layer also being doped with a doping material of a second doping type in sufficient concentration to provide a charge depletion region adjacent the outside edge of the charge transfer junction when the-charge transfer junction is reverse biased.

Abstract: A method of increasing the conductivity of a transparent conductive layer, in which a photoresist layer which patterns the transparent layer is given tapered edges and is partially etched. The partial etching exposing the edge regions of the underlying transparent conductor layer, which are the selectively plated. This method has a single patterning stage of the transparent layer, but uses partial etching of a tapered resist layer in order to expose a small edge region of the transparent layer for coating with a conductive layer (which can be opaque).

Abstract: The present invention provides a method for fabricating an ESD device. First, a substrate undergoes first implantation to form a first first-type well comprising an electrostatic discharge region. Next, second implantation is performed on the substrate and the electrostatic discharge region to form a second first-type well and an ESD device. Finally, gates, sources, and drains are formed to complete the process.

Abstract: A method of fabricating a MOS sensor is described. A P-doped region extending into a substrate is formed. A stacked polysilicon structure is formed over the P-doped region. Ions are implanted into the substrate to form an N-doped region extending shallowly into the P-doped region, the stacked polysilicon structure serving as an implantation buffer layer. The stacked polysilicon structure are patterned and etched to form a stacked polysilicon ring over the N-doped region. A metal line is formed for electrically connecting the stacked polysilicon ring with a gate of a MOS transistor.

Abstract: In the processes known so far, for a trench-shaped structure the doping of the side walls is coupled to the doping of the floor region.