Abstract: A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.

Abstract: A method of a fabricating a multiple wavelength adapted photodiode and resulting photodiode includes the steps of providing a substrate having a first semiconductor type surface region on at least a portion thereof, implanting and forming a second semiconductor type shallow surface layer into the surface region, and forming a multi-layer anti-reflective coating (ARC) on the shallow surface layer. The forming step includes depositing or forming a thin oxide layer on the shallow surface layer and depositing a second dielectric layer different from the thin oxide layer on the thin oxide layer. An etch stop is formed on the second dielectric, wherein the etch stop includes at least one layer resistant to oxide etch. At least one oxide including layer (e.g. ILD) is then deposited on the etch stop. The oxide including layer and etch stop are then removed to expose at least a portion of the ARC to the ambient.

Abstract: A P-type polysilicon layer having a stable and desired resistivity is formed by alternately depositing a plurality of silicon atom layers and a plurality of group IIIA element atom layers on a semiconductor substrate by atomic layer deposition, and thereafter forming a P-type polysilicon layer by thermally diffusing the plurality of group IIIA element atom layers into the plurality of silicon atom layers. The plurality of group IIIA element atom layers may comprise Al, Ga, In, and/or Tl.

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate and source and drain electrodes disposed at respective sides of the gate electrode. The device further includes a nano-line passing through the gate electrode and extending into the source and drain electrodes and having semiconductor characteristics. The nano-line may include a nano-wire and/or a nano-tube. A gate insulating layer may be interposed between the nano-line and the gate electrode. The source and drain electrodes may be disposed adjacent respective opposite sidewalls of the gate electrode, and the gate insulating layer may be further interposed between the source and drain electrodes and the gate electrode. Fabrication methods for such devices are also described.

Abstract: The invention relates to a method for producing a support comprising nanoparticles (22) for the growth of nanostructures (23), said nanoparticles being organised periodically, the method being characterised in that it comprises the following steps: providing a support comprising, in the vicinity of one of its surfaces, a periodic array of crystal defects and/or stress fields (18), depositing, on said surface, a continuous layer (20) of a first material capable of catalysing the nanostructure growth reaction, fractionating the first material layer (20) by a heat treatment so as to form the first material nanoparticles (22). The invention also relates to a method for producing nanostructures from said support.

Abstract: A fully protected H-bridge for a d-c motor consists of two high side MOSFETs and a control and logic IC on a first conductive heat sink all within a first package and two discrete low side MOSFETs. The entire bridge is controlled by the IC. Shoot thru protection is provided for each leg, and a PMW soft start sequence is provided through the control of the low side MOSFETs, programed by an external, chargeable RC circuit. Input signals to the high side MOSFETs select the operation modes. Protective circuits are provided for short circuit current and over current conditions. Sleep mode and braking/non braking control is also provided.

Abstract: In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.

Abstract: To provide a semiconductor device including a thinned substrate with high yield. After forming a protective layer in a predetermined portion (at least a portion covering a side surface of a substrate) of the substrate, grinding and polishing of the substrate are performed. In other words, an element layer including a plurality of integrated circuits is formed over one surface of the substrate, the protective layer is formed in contact with at least the side surface of the substrate, and the substrate is thinned (for example, the other surface of the substrate is ground and polished), the protective layer is removed, and the polished substrate and the element layer is divided so as to form stack bodies including a layer provided with at least one of the plurality of integrated circuits.

Abstract: The present invention includes single electron structures and devices comprising a substrate having an upper surface, one or more dielectric layers formed on the upper surface of the substrate and having at least one exposed portion, at least one monolayer of self-assembling molecules attracted to and in contact with the at least one exposed portion of only one of the one or more dielectric layers, one or more nanoparticles attracted to and in contact with the at least one monolayer, and at least one tunneling barrier in contact with the one or more nanoparticles. Typically, the single electron structure or device formed therefrom further comprise a drain, a gate and a source to provide single electron behavior, wherein there is a defined gap between source and drain and the one or more nanoparticles is positioned between the source and drain.

Abstract: During fabrication of single-walled carbon nanotube transistor devices, a porous template with numerous parallel pores is used to hold the single-walled carbon nanotubes. The porous template or porous structure may be anodized aluminum oxide or another material. A gate region may be provided one end or both ends of the porous structure. The gate electrode may be formed and extend into the porous structure.

Abstract: This invention proposes the useful, non-obvious and novel steps of a polymer or wet paper based planchette containing an RFID fully integrated system on a chip transponder which can be attached to a collectible or reusable through the use of a substrate friendly adhesive. A collectible is defined herein as an individual piece of art work or an art collection, a stamp collection or an individual stamp, sports card collections or an individual card, sports memorabilia of any sort, currency collections or an individual piece of currency and items of a similar ilk plus designer label garments and accessories. As a collectable tracing and tracking system it is called “Collectable Cop”. A reusable is defined as packaging, containers, pallets or any other non consumable item utilized on the supply chain which reusable(s) requires tracking or tracing, referred to as the “Spot Chip” system.

Abstract: A method of producing a thin film transistor comprises irradiating a resist on a glass base plate with a ray from a light source through a mask and, thereafter, developing the resist to form contact holes, using an i-ray as the ray.

Abstract: A method of producing a semiconductor element in a substrate includes forming a plurality of micro-cavities in a substrate, creating an amorphization of the substrate to form crystallographic defects and a doping of the substrate with doping atoms, depositing an amorphous layer on top of the substrate, and annealing the substrate, such that at least a part of the crystallographic defects is eliminated using the micro-cavities. The semiconductor element is formed using the doping atoms.

Abstract: A field effect transistor having a T-shaped gate electrode is formed on a GaAs substrate, and the T-shaped gate electrode of the field effect transistor is coated with a SiO2 film. A lower electrode of a MIM capacitor is formed on the GaAs substrate. The active portion of the field effect transistor is coated with a fluorine-containing polymer layer. A SiN film, which is a capacity insulating film of the MIM capacitor, is formed on the fluorine-containing polymer layer and the lower electrode. After removing the SiN film from the fluorine-containing polymer layer, the fluorine-containing polymer layer is selectively removed from the SiO2 film and the SiN film. An upper electrode of the MIM capacitor is formed opposite the lower electrode on the SiN film.

Abstract: The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.

Abstract: Methods for manufacturing trench type semiconductor devices containing thermally unstable refill materials are provided. A disposable material is used to fill the trenches and is subsequently replaced by a thermally sensitive refill material after the high temperature processes are performed. Trench type semiconductor devices manufactured according to method embodiments are also provided.

Abstract: An organic thin film transistor and a method for fabricating the same are disclosed. The method for fabricating the organic thin film transistor includes forming a gate electrode on a substrate. A gate insulating layer is formed on an entire surface of the substrate including the gate electrode, and source and drain electrodes are formed at a predetermined interval from each other on the gate insulating layer. An organic semiconductor layer is formed on the entire surface of the substrate and a first protection layer is formed on the organic semiconductor layer. The first protection layer is patterned and the organic semiconductor layer etched using the remaining first protection layer as a mask. A second protection layer is then formed on the entire surface of the substrate.

Abstract: A gate electrode (202) for a transistor including a metal gate structure (207) containing zirconium and a polycrystalline silicon cap (209) located there over. The metal gate structure (207) is located over a gate dielectric (205). The zirconium inhibits diffusion of silicon from the cap to the metal gate structure and gate dielectric. In one embodiment, the gate dielectric is a high K dielectric.

Abstract: A semiconductor device with an increased channel length and a method for fabricating the same are provided. The semiconductor device includes: a substrate with an active region including a planar active region and a prominence active region formed on the planar active region; a gate insulation layer formed over the active region; and a gate structure including at least one gate lining layer encompassing the prominence active region on the gate insulation layer.

Abstract: A method of manufacturing a transistor includes the step of forming on a substrate a source electrode and drain electrode by selective electroless plating after patterning a charge control agent attached to the substrate using light, and the step of forming an organic semiconductor, a gate insulation layer, and a gate electrode.

Abstract: A method of manufacturing a thin film transistor panel is provided, which includes forming a first signal line on a substrate. The method also includes forming in sequence a first insulating layer and a semiconductor layer on the first signal line. The method further includes patterning the semiconductor layer and the first insulating layer through one photolithography process to form a patterned semiconductor layer and a patterned first insulating layer. The method also includes forming a second signal line on the patterned semiconductor layer and the patterned first insulating layer.

Abstract: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

Abstract: In a mutual immittance calculation apparatus, an input section inputs data of a model of an electric circuit apparatus, being a target for analysis of the electromagnetic-field strength and being divided into a plurality of patches. A mutual immittance calculation section calculates respective mutual immittance for combinations of patches corresponding to the main portion and to the additional portion. The mutual immittance calculation section uses a stored calculation result corresponding to the main portion when the model in which only the additional portion has been changed is calculated for a second time onward, and recalculates the mutual immittance corresponding to the changed additional portion.

Abstract: A thin film transistor including a gate, a gate insulating layer, a semiconductor layer and a source/drain is provided. The gate is disposed over a substrate, wherein the gate comprises at least one molybdenum-niobium alloy nitride layer. The gate insulating layer is formed over the substrate to cover the gate. The semiconductor layer is disposed over the gate insulating layer above the gate. The source/drain is disposed over the semiconductor layer.

Abstract: In some aspects, a method of forming a memory circuit is provided that includes (1) forming a two-terminal memory element on a substrate between a gate layer and a first metal layer of the memory circuit; and (2) forming a CMOS transistor on the substrate, the CMOS transistor for programming the two-terminal memory element. Numerous other aspects are provided.

Abstract: The invention includes methods of forming implant regions between and/or under transistor gates. In one aspect, a pair of transistor gates is partially formed, and a layer of conductive material is left extending between the transistor gates. A dopant is implanted through the conductive material to form at least one implant region between and/or beneath the partially formed transistor gates, and subsequently the conductive material is removed from between the gates. The gates can be incorporated into various semiconductor assemblies, including, for example, DRAM assemblies.

Abstract: A probe of a scanning probe microscope having a sharp tip and an increased electric characteristic by fabricating a planar type of field effect transistor and manufacturing a conductive carbon nanotube on the planar type field effect transistor. To achieve this, the present invention provides a method for fabricating a probe having a field effect transistor channel structure including fabricating a field effect transistor, making preparations for growing a carbon nanotube at a top portion of a gate electrode of the field effect transistor, and generating the carbon nanotube at the top portion of the gate electrode of the field effect transistor.

Abstract: A method for cleaning suicide includes providing a substrate having at least an intergraded silicide and residues, sequentially performing an ammonia hydrogen peroxide (APM) mixture cleaning process and a vaporized hydrochloric acid-hydrogen peroxide mixture (HPM) cleaning process to remove the residues, and performing a sulfuric acid-hydrogen peroxide mixture (SPM) cleaning process to remove residuals of the vaporized HPM cleaning process.

Abstract: An underlying layer ALY of GaN is formed on a sapphire substrate SSB; a transfer layer TLY of GaN with a bump and dip shaped surface is formed on the underlying layer ALY; a light absorption layer BLY is formed on the bump and dip shaped surface of the transfer layer TLY; and a grown layer 4 of a planarization layer CLY and a structured light-emitting layer DLY having at least an active layer are formed on the light absorption layer BLY. A support substrate 2 is provided on the grown layer 4. The backside of the sapphire substrate SSB is irradiated with light of the second harmonic of YAG laser (wavelength 532 nm) to decompose the light absorption layer BLY and delaminate the sapphire substrate SSB, thereby allowing the planarization layer CLY of a bump and dip shaped surface to be exposed as a light extraction face.

Abstract: Organic field effect transistors (OFETs) can be created rapidly and at low cost on organic films by using a multilayer film (202) that has an electrically conducting layer (204, 206) on each side of a dielectric core. The electrically conducting layer is patterned to form gate electrodes (214), and a polymer film (223) is attached onto the gate electrode side of the multilayer dielectric film, using heat and pressure (225) or an adhesive layer (228). A source electrode and a drain electrode (236) are then fashioned on the remaining side of the multilayer dielectric film, and an organic semiconductor (247) is deposited over the source and drain electrodes, so as to fill the gap between the source and drain electrodes and touch a portion of the dielectric film to create an organic field effect transistor.

Abstract: A method including implanting carbon and fluorine into a substrate in an area of the substrate between a source/drain region and a channel, the area designated for a source/drain extension; and a source/drain extension dopant following implanting carbon and fluorine, implanting phosphorous in the area. A method including disrupting a crystal lattice of a semiconductor substrate in an area of the substrate between a source/drain region and a channel designated for a source/drain extension; after disrupting, implanting carbon and fluorine in the area; and implanting phosphorous in the area. A method including performing a boron halo implant before implanting phosphorous to form N-type source/drain extensions. An apparatus including an N-type transistor having a source/drain extension comprising carbon and phosphorous, formed in an area of a substrate between a source/drain region of the transistor and a channel of the transistor.

Abstract: A method for forming an integrated circuit device, e.g., memory, logic. The method includes providing a semiconductor substrate (e.g., silicon wafer) comprising a surface region and forming a polysilicon layer overlying the surface region. Preferably, the polysilicon layer is doped with an impurity to provide conductive characteristics. The method forms a cap layer (e.g., silicon nitride, silicon oxynitride) overlying the polysilicon layer. The method forms an Al2O3 layer using atomic layer deposition overlying the polysilicon layer to form a sandwich structure including the polysilicon layer, cap layer, and Al2O3 layer. The method includes patterning the sandwich layer to form a plurality of gate structures. Each of the gate structures includes a portion of the polysilicon layer, a portion of the cap layer, and a portion of the Al2O3 layer. The method forms an interlayer dielectric material (e.g., BPSG, FSG) having an upper surface overlying the plurality of gate structures.

Abstract: The present invention discloses a novel transistor structure employing semiconductive metal oxide as the transistor conductive channel. By replacing the silicon conductive channel with a semiconductive metal oxide channel, the transistors can achieve simpler fabrication process and could realize 3D structure to increase circuit density. The disclosed semiconductive metal oxide transistor can have great potential in ferroelectric non volatile memory device with the further advantages of good interfacial properties with the ferroelectric materials, possible lattice matching with the ferroelectric layer, reducing or eliminating the oxygen diffusion problem to improve the reliability of the ferroelectric memory transistor. The semiconductive metal oxide film is preferably a metal oxide exhibiting semiconducting properties at the transistor operating conditions, for example, In2O3 or RuO2.

Abstract: The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a semiconductor substrate within an atomic layer deposition chamber. On the substrate, an intermediate composition monolayer is formed, followed by a desired deposited composition from reaction with the intermediate composition, collectively from flowing multiple different composition deposition precursors to the substrate within the deposition chamber. A material adheres to a chamber internal component surface from such sequentially forming. After such sequentially forming, a reactive gas flows to the chamber which is different in composition from the multiple different deposition precursors and which is effective to react with such adhering material. After the reactive gas flowing, such sequentially forming is repeated. Further implementations are contemplated.

Abstract: A FET device for operation at high voltages includes a substrate, a first well and a second well within the substrate that are doped with implants of a first type and second type, respectively. The first and second wells define a p-n junction. A field oxide layer within the second well defines a first surface region to receive a drain contact. A third well is located at least partially in the first well, includes doped implants of the second type, and is adapted to receive a source contact. As such, the third well defines a channel between itself and the second well within the first well. A gate is disposed over the channel. At least a first portion of the gate is disposed over the p-n junction, and includes doped implants of the first type. A number of permutations are allowed for doping the remainder of the gate.

Abstract: A method of forming a transistor reduces leakage current and hot carrier effects, and therefore improves current performance. The method of forming a transistor includes selectively etching the semiconductor substrate to form a substrate protrusion and expose a buried source/drain implant region. A gate insulating layer covers the substrate protrusion and the first source/drain region. A gate conductor layer is selectively etched to form a gate pattern covering the sidewalls of the substrate protrusion and a portion of the semiconductor substrate adjacent to the sidewalls of the substrate protrusion. A second source/drain region is stacked over the top of the substrate protrusion. Contacts connected to the gate pattern and the first and second source/drain regions.

Abstract: A phase change memory device includes a substrate, a switching element formed in the substrate and a storage node connected to the switching element. The storage node may include a lower electrode connected to the switching element, a first phase change layer formed on the lower electrode, a magnetic resistance layer formed on the first phase change layer, a second phase change layer formed on the magnetic resistance layer and an upper electrode formed on the second phase change layer.

Abstract: A phase-change memory device has a phase-change layer, a heater electrode having an end held in contact with the phase-change layer, a contact plug of different kinds of material having a first electrically conductive material plug made of a first electrically conductive material and held in contact with the other end of the heater electrode, and a second electrically conductive material plug made of a second electrically conductive material having a specific resistance smaller than the first electrically conductive material, the first electrically conductive material plug and the second electrically conductive material plug being held in contact with each other through at least respective side surfaces thereof, the heater electrode and the second electrically conductive material plug being not in overlapping relation to each other, and an electrically conductive layer electrically connected to the second electrically conductive material plug.

Abstract: A method of manufacturing a semiconductor device. The device includes a plurality of layers on a semiconductor substrate. The method includes the steps of dividing a pattern of at least one layer into a plurality of sub-patterns, and joining the divided sub-patterns to perform patterning. A layer that includes wiring substantially affects operation of the semiconductor device depending on a positional relationship to any other wiring. The patterning is performed by one-shot exposure using a single mask.

Abstract: A memory device includes a substrate having a cell region, a low voltage region and a high voltage region. A ground selection transistor, a string selection transistor and a cell transistor are in the cell region, a low voltage transistor is in the low voltage region, and a high voltage transistor is in the high voltage region. A common source contact is on the ground selection transistor and a low voltage contact is on the low voltage transistor. A bit line contact is on the string selection transistor, a high voltage contact is on the high voltage transistor, and a bit line is on the bit line contact. A first insulating layer is on the substrate, and a second insulating layer is on the first insulating layer. The common source contact and the first low voltage contact extend to a height of the first insulating layer, and the bit line contact and the first high voltage contact extend to a height of the second insulating layer.

Abstract: An apparatus (200) such as a semiconductor device comprises a gate electrode (201) and at least a first electrode (202). The first electrode preferably has an established perimeter that at least partially overlaps with respect to the gate electrode to thereby form a corresponding transistor channel. In a preferred approach the first electrode has a surface area that is reduced notwithstanding the aforementioned established perimeter. This, in turn, aids in reducing any corresponding parasitic capacitance. This reduction in surface area may be accomplished, for example, by providing openings (203) through certain portions of the first electrode.

Abstract: A method of fabricating a tri-gate semiconductor device comprising a semiconductor body having an upper surface and side surfaces and a metal gate that has an approximately equal thickness on the upper and side surfaces. Embodiments of a tri-gate device with conformal physical vapor deposition workfunction metal on its three-dimensional body are described herein. Other embodiments may be described and claimed.

Abstract: A process for manufacturing a semiconductor device, provides that a silicide layer is formed, an amorphous semiconductor layer is applied both to the silicide layer and to an open monocrystalline semiconductor region, adjacent to the silicide layer, and during a subsequent temperature treatment, the amorphous semiconductor layer is crystallized proceeding from the open, monocrystalline semiconductor region, acting as a crystallization nucleus, so that the silicide layer is covered at least partially by a crystallized, monocrystalline semiconductor layer.

Abstract: Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.

Abstract: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a first intermediate layer over the first insulator layer, forming a charge trap layer over the first intermediate layer, forming a second intermediate layer over the charge trap layer, and forming a second insulator layer with the second intermediate layer.

Abstract: Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices. Forming the dielectric layer may include depositing zirconium oxide using atomic layer deposition and precursor chemicals, followed by depositing aluminum nitride using precursor chemicals, and repeating. The dielectric layer may be used as the gate insulator of a MOSFET, a capacitor dielectric, and a tunnel gate insulator in flash memories.

Abstract: Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described.

Abstract: A method of manufacturing a flash memory device includes the steps of forming gate patterns for cells and gate patterns for select transistors over a semiconductor substrate, forming a buffer insulating layer on the resulting surface including the gate patterns, forming an insulating layer to form void in spaces between the gate patterns for cells, forming a nitride layer on the insulating layer, and forming a spacer on one side of each of the gate patterns for select transistors by a spacer etch process.

Abstract: Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. Then, a COR pre-clean is performed and the recesses are filled by epitaxial deposition. The epi can be in-situ doped or subsequently implanted to form source/drain extensions. Alternatively, the etch is immediately followed by the COR pre-clean, which is followed by epitaxial deposition to fill the recesses. During the epitaxial deposition process, the deposited material is doped to form in-situ doped halos and, then, the dopant is switched to form in-situ doped source/drain extensions adjacent to the halos. Alternatively, after the in-situ doped halos are formed the deposition process is performed without dopants and an implant is used to form source/drain extensions.

Abstract: A nonvolatile semiconductor memory includes a first and a second active area configured to extend in the column direction in parallel; an element isolating region configured to electrically separate the first and the second active area; a plurality of word lines configured to extend in the row direction and be constituted by respective main parts and respective ends; and a plurality of memory cell transistors configured to be disposed on intersections between the respective main parts of the plurality of word lines and the second active area. Each memory cell transistor comprises a gate insulating film, a floating gate electrode, an inter-gate insulating film, and a control gate electrode, constituting a memory cell array; a short-circuit region configured to electrically short circuit the ends of the plurality of word lines; and a trench configured to separate the ends from the main parts of the plurality of word lines.