Responsive To Electromagnetic Radiation Patents (Class 438/57)
  • Patent number: 8952493
    Abstract: According to one embodiment of the present invention, a solid state electrolyte memory cell includes a cathode, an anode and a solid state electrolyte. The anode includes an intercalating material and first metal species dispersed in the intercalating material.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 10, 2015
    Assignees: Adesto Technologies Corporation, Artemis Acquisition LLC
    Inventor: Sandra Mege
  • Patent number: 8951824
    Abstract: Provided are novel methods of fabricating photovoltaic modules using pressure sensitive adhesives (PSA) to secure wire networks of interconnect assemblies to one or both surfaces of photovoltaic cells. A PSA having suitable characteristics is provided near the interface between the wire network and the cell's surface. It may be provided together as part of the interconnect assembly or as a separate component. The interconnect assembly may also include a liner, which may remain as a part of the module or may be removed later. The PSA may be distributed in a void-free manner by applying some heat and/or pressure. The PSA may then be cured by, for example, exposing it to UV radiation to increase its mechanical stability at high temperatures, in particular at a, for example the maximum, operating temperature of the photovoltaic module. For example, the modulus of the PSA may be substantially increased during this curing operation.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: February 10, 2015
    Assignee: Apollo Precision (Fujian) Limited
    Inventor: Todd Krajewski
  • Patent number: 8952474
    Abstract: Provided is a method of fabricating a backside illuminated image sensor that includes providing a device substrate having a frontside and a backside, where pixels are formed at the frontside and an interconnect structure is formed over pixels, forming a re-distribution layer (RDL) over the interconnect structure, bonding a first glass substrate to the RDL, thinning and processing the device substrate from the backside, bonding a second glass substrate to the backside, removing the first glass substrate, and reusing the first glass substrate for fabricating another backside-illuminated image sensor.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: February 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Chieh Huang, Dun-Nian Yaung, Chih-Jen Wu, Chen-Ming Huang
  • Publication number: 20150034834
    Abstract: Radiation detectors having nanowires with charged, radiation-labile coatings configured to change the electrical properties of nanowires are provided. In one aspect, a radiation detection device is provided. The radiation detector device includes at least one nanowire having a radiation-labile coating with charged moieties on a surface thereof, wherein the radiation-labile coating is configured to degrade upon exposure to radiation such that the charged moieties are cleaved from the radiation-labile coating upon exposure to radiation and thereby affect a transconductance of the nanowire.
    Type: Application
    Filed: July 31, 2013
    Publication date: February 5, 2015
    Applicant: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Jose M. Lobez Comeras
  • Publication number: 20150037922
    Abstract: A method for imparting a pattern to a flowable resist material on a substrate entails providing a resist layer so thin that during a stamp wedging process, the resist never completely fills the space between the substrate and the bottom surface of a stamp between wedge protrusions, leaving gap everywhere therebetween. A gap remains between the resist and the extended surface of the stamp. If the resist layer as deposited is somewhat thicker than the targeted amount, it will simply result in a smaller gap between resist and tool. The presence of a continuous gap assures that no pressure builds under the stamp. Thus, the force on the protrusions i determined only by the pressure above the stamp and is well controlled, resulting in well-controlled hole sizes. The gap prevents resist from being pumped entirely out of any one region, and thus prevents any regions from being uncovered of resist. The stamp can be pulsed in its contact with the substrate, repeatedly deforming the indenting protrusions.
    Type: Application
    Filed: September 22, 2012
    Publication date: February 5, 2015
    Applicant: 1366 TECHNOLOGIES, INC.
    Inventor: Emanuel M. Sachs
  • Patent number: 8945430
    Abstract: A photovoltaic cell comprises a membrane electrode assembly obtainable by the in situ polymerization between two electrodes of one or more monomers to form a polymer, and then infusing an activating agent into the polymer, wherein the activating agent enables the membrane electrode assembly to function as a photovoltaic cell.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: February 3, 2015
    Assignee: ITM Power (Research) Ltd.
    Inventors: Donald James Highgate, Nicholas Baynes, Rachel Louise Smith, Kris Hyde
  • Patent number: 8945977
    Abstract: A method for producing an opto-microelectronic micro-imaging device includes a step of forming a first functional part on the base of a first substrate, a base layer, and first electric connection pad. The first functional part is transferred onto a second substrate. The first substrate is thinned until the base layer is reached. A second functional part is formed on the base layer. One via is connected to the first electric connection pad and through the first functional part. The step of forming the second functional part includes connecting the via with the second electric connection pad.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: February 3, 2015
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Umberto Rossini, Thierry Flahaut
  • Patent number: 8946540
    Abstract: An imitation solar module for structural and aesthetic use in an array of electricity generating solar modules. The imitation solar module having a non-standard shape and a visual representation such as a decal of an actual solar module surface thereon. The imitation solar module includes triangular shapes for use in staggered module arrays.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: February 3, 2015
    Assignee: Zep Solar, LLC
    Inventors: John R. West, Alex Haines, Kyle Tripp
  • Publication number: 20150027531
    Abstract: A silicon-containing film includes a first chemical vapor deposition layer and a second chemical vapor deposition layer. The first chemical vapor deposition layer includes elemental silicon. The first chemical vapor deposition layer is formed by a plasma CVD method such that oxygen concentration is greater than or equal to 0% by element and less than 10% by element. The second chemical vapor deposition layer includes elemental silicon. The second chemical vapor deposition layer is formed by the plasma CVD method such that oxygen concentration is greater than 35% by element and less than or equal to 70% by element. A ratio of the thickness of the second chemical vapor deposition layer relative to the thickness of the first chemical vapor deposition layer is 1.5-9.
    Type: Application
    Filed: January 16, 2013
    Publication date: January 29, 2015
    Applicant: Toray Engineering Co., Ltd.
    Inventors: Masamichi Yamashita, Takayoshi Fujimoto, Takashi Iwade
  • Patent number: 8940556
    Abstract: A apparatus and method for manufacturing a photovoltaic module includes components for heating the module and applying an electrical bias to the module to improve photovoltaic module performance and manufacture multiple photovoltaic modules with similar performance.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: January 27, 2015
    Assignee: First Solar, Inc
    Inventors: Imran Khan, Markus Gloeckler, Jigish Trivedi, Thomas Truman
  • Publication number: 20150020863
    Abstract: Use of chemical mechanical polishing (CMP) and/or pure mechanical polishing to separate sub-cells in a thin film solar cell. In one embodiment the CMP is only used to separate the active, thin film layer into sub-cells, with scribing still being used to achieve sub-cell separation in conductive layers above and below the active, thin film layer. Also, the active layer may be placed over a series of protrusions so that the CMP removes the active layer that is over the protrusion, while leaving intact the flat, planar portions of the active layer. In this way, the removed active layer, from over the protrusions then becomes the division between sub-cells in the active layer.
    Type: Application
    Filed: July 22, 2013
    Publication date: January 22, 2015
    Applicant: International Business Machines Corporation
    Inventors: Hans-Juergen Eickelmann, Ruediger Kellmann, Markus Schmidt
  • Publication number: 20150024538
    Abstract: An apparatus includes a manifold coupled to a vapor source, the manifold having a plurality of nozzles, an inner cylinder, and an outer cylinder containing the inner cylinder with a space defined between the inner and outer cylinders. One of the inner cylinder or outer cylinder is rotatable with respect to the other of the inner cylinder or outer cylinder. The outer cylinder has an inlet coupled to the manifold to receive vapor from the nozzles. The outer cylinder has an outlet for dispensing the vapor.
    Type: Application
    Filed: July 19, 2013
    Publication date: January 22, 2015
    Applicant: TSMC Solar Ltd.
    Inventor: Shih-Wei Chen
  • Publication number: 20150020877
    Abstract: Fabrication methods and structures relating to backplanes for back contact solar cells that provide for solar cell substrate reinforcement and electrical interconnects as well as Fabrication methods and structures for forming thin film back contact solar cells are described.
    Type: Application
    Filed: August 9, 2012
    Publication date: January 22, 2015
    Applicant: SOLEXEL, INC.
    Inventors: Mehrdad M. Moslehi, Pawan Kapur, Karl-Josef Kramer, Virendra V. Rana, Sean Seutter, Anand Deshpande, Anthony Calcaterra, Gerry Olsen, Kamran Manteghi, Thom Stalcup, George D. Kamian, David Xuan-Qi Wang, Yen-Sheng Su, Michael Wingert
  • Patent number: 8935848
    Abstract: The present invention is a method for providing an integrated circuit assembly, the integrated circuit assembly including an integrated circuit and a substrate. The method includes mounting the integrated circuit to the substrate. The method further includes, during assembly of the integrated circuit assembly, applying a low processing temperature, at least near-hermetic, glass-based coating directly to the integrated circuit and a localized interconnect interface, the interface being configured for connecting the integrated circuit to at least one of the substrate and a second integrated circuit of the assembly. The method further includes curing the coating. Further, the integrated circuit may be a device which is available for at least one of sale, lease and license to a general public, such as a Commercial off the Shelf (COTS) device. Still further, the coating may promote corrosion resistance and reliability of the integrated circuit assembly.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: January 20, 2015
    Assignee: Rockwell Collins, Inc.
    Inventors: Alan P. Boone, Nathan P. Lower, Ross K. Wilcoxon
  • Patent number: 8936949
    Abstract: A manufacturing method of a solar cell in which a light receiving side electrode including grid electrodes is provided on one side of a semiconductor substrate, comprises: a first step of forming an impurity diffusion layer on one side of the semiconductor substrate of a first conductivity type, the diffusion layer having a second conductivity-type impurity diffused therein; a second step of measuring a sheet resistance value of the diffusion layer at a plurality of measurement points in a surface of the diffusion layer; and a third step of dividing the surface of the diffusion layer into a plurality of areas corresponding to the measured sheet resistance values of the surface of the diffusion layer, setting a distance between adjacent grid electrodes for each of the areas, and forming the light receiving side electrode, which is electrically connected to the diffusion layer, on the diffusion layer.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: January 20, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventor: Shoichi Karakida
  • Publication number: 20150017754
    Abstract: The invention provides composition for forming an n-type diffusion layer, the composition comprising a compound containing a donor element, a dispersing medium, and an organic filler; a method for producing a semiconductor substrate having an n-type diffusion layer; and a method for producing a photovoltaic cell element.
    Type: Application
    Filed: January 10, 2013
    Publication date: January 15, 2015
    Inventors: Tetsuya Sato, Masato Yoshida, Takeshi Nojiri, Toranosuke Ashizawa, Yasushi Kurata, Yoichi Machii, Mitsunori Iwamuro, Akihiro Orita, Mari Shimizu
  • Patent number: 8932894
    Abstract: Gray tone lithography is used to form curved silicon topographies for semiconductor based solid-state imaging devices. The imagers are curved to a specific curvature and shaped directly for the specific application; such as curved focal planes. The curvature of the backside is independent from the front surface, which allows thinning of the detector using standard semiconductor processing.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: January 13, 2015
    Assignee: The United States of America, as represented by the Secratary of the Navy
    Inventors: Marc Christophersen, Bernard F. Phlips
  • Publication number: 20150008551
    Abstract: A semi-conducting structure, configured to receive an electromagnetic radiation and to transform the electromagnetic radiation into an electric signal, including: a first zone and a second zone of a same conductivity type and of same elements; a barrier zone, provided between the first and second zones, for acting as a barrier to majority carriers of the first and second zones on a barrier thickness, the barrier zone having its lowest bandgap energy defining a barrier proportion; and a first interface zone configured to interface the first zone and the barrier zone on a first interface thickness, the first interface zone including a composition of elements which is varied from a proportion corresponding to that of the first material to the barrier proportion, the first interface thickness being at least equal to half the barrier thickness.
    Type: Application
    Filed: January 2, 2013
    Publication date: January 8, 2015
    Applicant: Commissariat a l'energie atomique et aux ene alt
    Inventors: Olivier Gravrand, Alexandre Ferron
  • Publication number: 20150010263
    Abstract: Forming an optical device includes growing an electro-absorption medium in a variety of different regions on a base of a device precursor. The regions include a component region and the regions are selected so as to achieve a particular chemical composition for the electro-absorption medium included in the component region. An optical component is formed on the device precursor such that the optical component includes at least a portion of the electro-absorption medium from the component region. Light signals are guided through the electro-absorption medium from the component region during operation of the component.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 8, 2015
    Inventors: Joan Fong, Wei Qian, Dazeng Feng, Mehdi Asghari
  • Publication number: 20150011036
    Abstract: The invention relates to a method for manufacturing a solar cell from a semiconductor substrate of a first conductivity type, the semiconductor substrate having a front side and a back side, the method comprising in this sequence: creating by diffusion of a dopant of a second conductivity type a second conductivity-type doped layer in the front side and the back side, during diffusion forming of a dopant containing glassy layer on the front and back side; removing the second conductivity-type doped layer and the dopant containing glassy layer from the back side by a single sided etching process, while maintaining the dopant-containing glassy layer in the front side; creating a Back Surface Field (BSF) layer of the first conductivity type on the back side by implantation of a dopant of the first conductivity type into the back side; removing the dopant containing glassy layer from the front side of said substrate by an etching process; surface oxidation by heating said substrate for a predetermined period of t
    Type: Application
    Filed: March 18, 2013
    Publication date: January 8, 2015
    Inventor: Ronald Cornelis Gerard Naber
  • Patent number: 8927313
    Abstract: In a method for manufacturing a solar cell where the solar cell includes a dopant layer having a first portion of a first resistance and a second portion of a second resistance lower than the first resistance, the method includes ion-implanting a dopant into the semiconductor substrate to form the dopant layer; firstly activating by heating the second portion and activating the dopant at the second portion; and secondly activating by heating the first portion and the second portion and activating the dopant at the first portion and the second portion.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: January 6, 2015
    Assignee: LG Electronics Inc.
    Inventors: Kyoungsoo Lee, Seongeun Lee
  • Patent number: 8927314
    Abstract: A method of manufacturing a solar cell includes the steps of: providing a substrate having a front side, a back side and a doped region; forming a conductor layer on the front side; firing the conductor layer at a temperature such that the conductor layer is formed with a first portion embedded into the doped region and a second portion other than the first portion; forming an anti-reflection coating (ARC) layer on the front side and the second portion, wherein the ARC layer covers the conductor layer so that the second portion of the conductor layer is disposed in the ARC layer; and removing the ARC layer on the conductor layer so that the conductor layer has an exposed surface exposed out of the ARC layer, wherein the exposed surface of the conductor layer is substantially flush with a first exposed surface of the ARC layer.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: January 6, 2015
    Assignee: Big Sun Energy Technology Inc.
    Inventors: Sheng Yung Liu, Chin-Tien Yang, Chun-Hung Lin
  • Patent number: 8927316
    Abstract: A camera module includes an image sensor chip including a substrate having first and second opposite surfaces and a ground pad on the first surface, a housing surrounding the sides of the image sensor chip but which leaves the second surface of the image sensor chip exposed, an electromagnetic wave-shielding film united with the housing, and an electrical conductor electrically connected to the ground pad. The camera module also has an optical unit disposed on the first surface of the image sensor chip in the housing to guide light from an object to the image sensor chip. The electrical conductor extends through a side of the housing. The conductor also contacts the electromagnetic wave-shielding film to electrically connect the ground pad and the electromagnetic wave-shielding film.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hoe Cho, Byoung-Rim Seo, Yung-Cheol Kong, Han-Sung Ryu
  • Patent number: 8927315
    Abstract: Methods and devices are provided for high-efficiency solar cells. In one embodiment, an assembly is provided comprising of a plurality of solar cells each having at least one transparent conductor, a photovoltaic layer, at least one bottom electrode, a plurality of emitter wrap through (EWT) vias containing a conductive material, and a plurality of series interconnect vias containing a conductive material. The assembly may also include a backside support coupled to the solar cells, wherein the backside support is patterned to have electrically conductive areas and electrically nonconductive areas that create a series interconnect between solar cells electrically coupled by the support and prevents parallel connections between the solar cells. The cells may have a via insulating layer in each via separating the conductive material in each via from any side walls of the bottom electrode.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: January 6, 2015
    Assignee: aeris CAPITAL Sustainable IP Ltd.
    Inventors: James R. Sheats, Werner Dumanski
  • Patent number: 8927324
    Abstract: A method for the production of a wafer-based, back-contacted heterojunction solar cell includes providing at least one absorber wafer. Metallic contacts are deposited as at least one of point contacts and strip contacts in a predetermined distribution on a back side of the at least one absorber wafer. The contacts have steep flanks that are higher than a cumulative layer thickness of an emitter layer and an emitter contact layer and are sheathed with an insulating sheath. The emitter layer is deposited over an entire surface of the back side of the at least one absorber wafer. The emitter contact layer is deposited over an entire surface of the emitter layer so as to form an emitter contact system. At least one of the emitter layer and the emitter contact layer is selectively removed so as to expose the steep flanks of the contacts that are covered with the insulating sheath.
    Type: Grant
    Filed: October 10, 2009
    Date of Patent: January 6, 2015
    Assignee: Helmholtz-Zentrum Berlin Fuer Materialien und Energie GmbH
    Inventor: Rolf Stangl
  • Patent number: 8927319
    Abstract: There is disclosed methods of making photosensitive devices, such as flexible photovoltaic (PV) devices, through the use of epitaxial liftoff. Also described herein are methods of preparing flexible PV devices comprising a structure having a growth substrate, wherein the selective etching of protective layers yields a smooth growth substrate that us suitable for reuse.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: January 6, 2015
    Assignee: The Regents of the University of Michigan
    Inventors: Stephen R. Forrest, Jeramy Zimmerman, Kyusang Lee, Kuen-Ting Shiu
  • Publication number: 20150004734
    Abstract: A method for fabricating a solar cell using a nozzle assembly that includes a base portion, a scriber coupled to the base portion, and a nozzle coupled to the base portion such that the nozzle is positioned a predefined distance from a tip of the scriber is provided. The method generally comprises positioning a substructure that includes a buffer layer and an absorber layer proximate to the base portion. A P2 line is scribed through the buffer and absorber layers of the substructure using the scriber tip. A nanoparticle solution is sprayed, using the nozzle, onto at least one portion of the buffer layer at a predefined pressure when the P2 line is being scribed through the buffer and absorber layers such that a transparent conductive oxide (TCO) layer is inhibited from forming over the portion of the buffer layer that is being sprayed with the nanoparticle solution.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventor: Shih-Wei CHEN
  • Patent number: 8921187
    Abstract: Embodiments of a process including depositing a sacrificial layer on the surface of a substrate over a photosensitive region, over the top surface of a transfer gate, and over at least the sidewall of the transfer gate closest to the photosensitive region, the sacrificial layer having a selected thickness. A layer of photoresist is deposited over the sacrificial layer, which is patterned and etched to expose the surface of the substrate over the photosensitive region and at least part of the transfer gate top surface, leaving a sacrificial spacer on the sidewall of the transfer gate closest to the photosensitive region. The substrate is plasma doped to form a pinning layer between the photosensitive region and the surface of the substrate. The spacing between the pinning layer and the sidewall of the transfer gate substantially corresponds to a thickness of the sacrificial spacer. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: December 30, 2014
    Assignee: OmniVision Technologies, Inc.
    Inventors: Gang Chen, Duli Mao, Hsin-Chih Tai, Vincent Venezia, Yin Qian, Howard E. Rhodes
  • Patent number: 8921149
    Abstract: A first species selectively dopes a workpiece to form a first doped region. In one embodiment, a selective implant is performed using a mask with apertures. A soft mask is applied to the first doped region. A second species is implanted into the workpiece to form a second implanted region. The soft mask blocks a portion of the second species. Then the soft mask is removed. The first species and second species may be opposite conductivities such that one is p-type and the other is n-type.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: December 30, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nicholas P. T. Bateman, William T. Weaver
  • Patent number: 8916873
    Abstract: A photodetector includes a semiconductor substrate having an irradiation zone configured to generate charge carriers having opposite charge carrier types in response to an irradiation of the semiconductor substrate. The photodetector further includes an inversion zone generator configured to operate in at least two operating states to generate different inversion zones within the substrate, wherein a first inversion zone generated in a first operating state differs from a second inversion zone generated in a second operating state, and wherein the first inversion zone and the second inversion zone have different extensions in the semiconductor substrate. A corresponding method for manufacturing a photodetector and a method for determining a spectral characteristic of an irradiation are also described.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: December 23, 2014
    Assignee: Infineon Technologies AG
    Inventor: Thoralf Kautzsch
  • Publication number: 20140367747
    Abstract: An exemplary embodiment is a photoelectric conversion device having a photoelectric conversion portion, and a transfer portion. The transfer portion transfers charges of the photoelectric conversion portion. The photoelectric conversion portion includes first and second semiconductor regions of a first conductivity type. Charges generated by photoelectric conversion are accumulated in the first and second semiconductor regions. According to the structure of the first and second semiconductor regions of the exemplary embodiment or the method for manufacturing them, the transfer efficiency of charges can be improved while improving the sensitivity of the photoelectric conversion portion.
    Type: Application
    Filed: June 9, 2014
    Publication date: December 18, 2014
    Inventors: Takanori Watanabe, Takafumi Miki, Satoko Iida, Masahiro Kobayashi, Junji Iwata
  • Publication number: 20140370640
    Abstract: A high-fidelity dopant paste is disclosed. The high-fidelity dopant paste includes a solvent, a set of non-glass matrix particles dispersed into the solvent, and a dopant.
    Type: Application
    Filed: August 28, 2014
    Publication date: December 18, 2014
    Applicant: Innovalight, Inc.
    Inventors: Elena Rogojina, Maxim Kelman, Giuseppe Scardera
  • Publication number: 20140366936
    Abstract: A method for doping a semiconductor substrate is disclosed wherein a layer of a first conductivity type is first formed followed by forming a blocking layer with an open area. An etch process is performed through the open area to remove the layer of the first conductivity type to exposed the top surface of the semiconductor substrate. Dopant ions are introduced to form a dopant region of a second conductivity type on the beneath the top surface of the semiconductor substrate wherein the dopant region of the second conductivity type is not in contact with the dopant layer of the first conductivity type that is not etched off thus forming a PN structure to form diodes for the interdigitated back contact photovoltaic cells. Since the ion doping processes are self-aligned, the mask requirements are minimized and the production cost for solar cells are reduced.
    Type: Application
    Filed: June 17, 2013
    Publication date: December 18, 2014
    Inventors: Jiong Chen, Junhua Hong
  • Publication number: 20140370641
    Abstract: A method for processing a coated glass substrate may include a high-temperature activation process.
    Type: Application
    Filed: September 4, 2014
    Publication date: December 18, 2014
    Inventors: Daniel Burgard, Joshua Conley, James Hinkle, Stephen Murphy, Thomas Truman
  • Patent number: 8912090
    Abstract: An improved microwave mixer manufactured using multilayer processing includes an integrated circuit that is electrically connected to a top metal layer of a substrate. The microwave mixer includes: a first metal layer; a dielectric substrate on the first metal layer; a second metal layer directly on the substrate, at least two passive circuits arranged on the second metal layer and a top layer metal; a thin dielectric layer on the second metal layer, wherein the top layer metal is directly on the thin dielectric layer; an integrated circuit (IC) attached to the second metal layer, wherein the IC includes at least one combination of non-linear devices, and wherein the IC is directly connected to the passive circuits on the second metal layer; and a protection layer on the IC.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: December 16, 2014
    Assignee: Marki Microwave, Inc.
    Inventor: Christopher Ferenc Marki
  • Patent number: 8912030
    Abstract: A radiation dosimeter includes a semiconductor substrate and a buried insulator layer disposed on the semiconductor substrate. The buried insulator layer has a plurality of charge traps. A semiconductor layer is disposed on the buried insulator layer. The semiconductor layer has an emitter, an intrinsic base, and a collector laterally arranged with respect to one another. In response to radiation exposure by the radiation dosimeter, positive charges are trapped in the plurality of charge traps in the buried insulator layer, the amount of positive charge trapped being used to determine the amount of radiation exposure.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Effendi Leobandung, Tak H. Ning, Jeng-Bang Yau
  • Patent number: 8912519
    Abstract: Provided are a variable resistive memory device and a method of fabricating the same. The variable resistive memory device includes an interlayer insulating film having an opening therein, the opening exposing a surface of a first electrode which is disposed at a bottom of the opening. A variable resistive layer is formed in the opening and a second electrode is formed on the variable resistive layer. The variable resistive layer has a sidewall that is separated from an inner side surface of the opening to define a gap between the sidewall of the variable resistive layer and the inner side surface of the opening.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: December 16, 2014
    Assignee: SK Hynix Inc.
    Inventor: Keun Lee
  • Patent number: 8912032
    Abstract: Current may be passed through an n-doped semiconductor region, a recessed metal semiconductor alloy portion, and a p-doped semiconductor region so that the diffusion of majority charge carriers in the doped semiconductor regions transfers heat from or into the semiconductor waveguide through Peltier-Seebeck effect. Further, a temperature control device may be configured to include a metal semiconductor alloy region located in proximity to an optoelectronic device, a first semiconductor region having a p-type doping, and a second semiconductor region having an n-type doping. The temperature of the optoelectronic device may thus be controlled to stabilize the performance of the optoelectronic device.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Solomon Assefa, William M. Green, Young-hee Kim, Joris Van Campenhout, Yurii A. Vlasov
  • Patent number: 8912071
    Abstract: A method for fabricating a photovoltaic device includes forming a patterned layer on a doped emitter portion of the photovoltaic device, the patterned layer including openings that expose areas of the doped emitter portion and growing an epitaxial layer over the patterned layer such that a crystalline phase grows in contact with the doped emitter portion and a non-crystalline phase grows in contact with the patterned layer. The non-crystalline phase is removed from the patterned layer. Conductive contacts are formed on the epitaxial layer in the openings to form a contact area for the photovoltaic device.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ali Khakifirooz, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Publication number: 20140363916
    Abstract: A transportable process box for processing substrates coated on one side is described. The box has a base for the placement of a first substrate in a manner such that the latter is supported over the full area, a frame, a cover which is placed onto the frame, and an intermediate element which is arranged between the base and the cover and is intended for the placement of a second substrate in a manner such that the latter is supported over the full area. Arrangements and methods for processing substrates are also described.
    Type: Application
    Filed: February 8, 2013
    Publication date: December 11, 2014
    Applicant: SAINT-GOBAIN GLASS FRANCE
    Inventors: Martin Fuerfanger, Dang Cuong Phan, Stefan Jost
  • Publication number: 20140363917
    Abstract: A depletion-mode phototransitor is disclosed. The phototransistor having a substrate, a gate, a source, a drain and a channel. The source, drain and channel are doped to be the same type of semiconductor. The substrate can be made of silicon and/or germanium. The gate can be made of either aluminum or polysilicon.
    Type: Application
    Filed: August 15, 2014
    Publication date: December 11, 2014
    Applicant: The Board of Trustees of the Leland Stanford Junior University
    Inventors: YEUL NA, KRISHNA C. SARASWAT
  • Publication number: 20140361396
    Abstract: The present invention provides a hot-carrier photoelectric conversion method. The method includes a hot-carrier photoelectric conversion device having a P-type semiconductor layer, an N-type semiconductor layer, and an inorganic conducting light-absorbing layer. The inorganic conducting light-absorbing layer is formed between the P-type semiconductor layer and the N-type semiconductor layer, and an electric field is formed between the P-type semiconductor layer and the N-type semiconductor layer. Moreover, photons are absorbed by the inorganic conducting light-absorbing layer to create electrons and holes. The electrons and holes are respectively shifted by the electric field or diffusion effect to the N-type semiconductor layer and the P-type semiconductor layer, so that the electrons and the holes are respectively conducted outside to create electric energy.
    Type: Application
    Filed: February 19, 2014
    Publication date: December 11, 2014
    Applicant: National Taiwan University
    Inventors: Ching-Fuh Lin, Hsin-Yi Chen, Jiun-Jie Chao, Hong-Jhang Syu
  • Patent number: 8906733
    Abstract: A method for creating a nanostructure according to one embodiment includes depositing material in a template for forming an array of nanocables; removing only a portion of the template such that the template forms an insulating layer between the nanocables; and forming at least one layer over the nanocables. A nanostructure according to one embodiment includes a nanocable having a roughened outer surface and a solid core. A nanostructure according to one embodiment includes an array of nanocables each having a roughened outer surface and a solid core, the roughened outer surface including reflective cavities; and at least one layer formed over the roughened outer surfaces of the nanocables, the at least one layer creating a photovoltaically active p-n junction. Additional systems and methods are also presented.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: December 9, 2014
    Assignees: Q1 Nanosystems, Inc., The Regents Of The University Of California
    Inventors: Ruxandra Vidu, Brian Argo, John Argo, Pieter Stroeve, Saif Islam, Jie-Ren Ku, Michael Chen
  • Patent number: 8906269
    Abstract: The present invention relates to a paste and a solar cell using the paste. The paste according to an embodiment of the present invention comprises three and more than aluminum powders having different shape, size, and type, a glass frit, and an organic vehicle, wherein the aluminum powers includes a first powder of 40 to 50 wt %, a second powder of 20 to 30 wt %, and a third powder of 0.1 to 2 wt %, and the first to third powders have one or more than different shapes of a globular shape, a flat shape, a nano shape, and combinations thereof.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: December 9, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: In Jae Lee, Jin Gyeong Park, Jun Phil Eom, Soon Gil Kim
  • Publication number: 20140357010
    Abstract: A method includes providing a substrate having a first surface and a second surface, the first surface being opposite the second surface, forming a light sensing region at the first surface of the substrate, forming a doped layer at the second surface of the substrate using a laser annealing process, and performing a chemical mechanical polishing process on the annealed, doped layer.
    Type: Application
    Filed: August 19, 2014
    Publication date: December 4, 2014
    Inventors: Shou-Shu Lu, Hsun-Ying Huang, I-Chang Lin, Chia-Chi Hsiao, Yung-Cheng Chang
  • Publication number: 20140352769
    Abstract: A solar cell having a large region where reverse breakdown can occur is disclosed. Reverse breakdown tends to occur near areas where heavily doped n-type regions abut heavily doped p-type regions. Thus, by increasing the region where such a heavily doped p/n junction exists may improve the reverse breakdown characteristics of the solar cell. In addition, a method of making such solar cell is disclosed, where this heavily doped p/n junction is fabricated along at least a portion of the perimeter of the solar cell.
    Type: Application
    Filed: May 29, 2013
    Publication date: December 4, 2014
    Inventor: Nicholas P.T. Bateman
  • Publication number: 20140357009
    Abstract: A method of manufacturing a photovoltaic cell including forming a semiconductor substrate comprising opposite first and second surfaces; forming, on the first surface of the substrate, a first semiconductor area doped by implantation of first dopant elements across the substrate thickness and by thermal activation of the first implanted dopant elements at a first activation temperature; forming, on the second surface of the substrate, a second semiconductor area doped by implantation of second dopant elements across the substrate thickness and by thermal activation of the second implanted dopant elements at a second activation temperature lower than the first activation temperature; at least the thermal activation of the first dopant elements is performed by laser irradiation, the irradiation parameters being selected so that the radiation is absorbed at most down to a depth of the first micrometer of the substrate.
    Type: Application
    Filed: December 19, 2012
    Publication date: December 4, 2014
    Inventors: Bertrand Paviet-Salomon, Samuel Gall, Adeline Lanterne, Sylvain Manuel
  • Publication number: 20140352779
    Abstract: One embodiment is a nanostructured arrangement having a base and pyramidal features formed on the base. Each pyramidal feature includes sloping sides converging at a vertex. The nanostructured arrangement further includes a nanostructured surface formed on at least one of the sloping sides of at least one of the pyramidal features. The nanostructured surface has a quasi-periodic, anisotropic array of elongated ridge elements having a wave-ordered structure pattern. Each ridge element has a wavelike cross-section and oriented substantially in a first direction.
    Type: Application
    Filed: January 18, 2012
    Publication date: December 4, 2014
    Applicant: Wostec. Inc.
    Inventors: Valery K. Smirnov, Dmitry S. Kibalov
  • Publication number: 20140357008
    Abstract: A method of manufacturing a solar cell is disclosed. The method includes forming a doping region including first and second portions having different doping concentrations by ion-implanting a dopant into a semiconductor substrate and forming an electrode connected to the doping region. In the forming of the doping region, the first and second portions are simultaneously formed by the same process using a mask that is disposed at a distance from the semiconductor substrate.
    Type: Application
    Filed: May 28, 2014
    Publication date: December 4, 2014
    Applicant: LG ELECTRONICS INC.
    Inventors: Jinsung KIM, Daeyong LEE
  • Publication number: 20140352770
    Abstract: Discussed is a solar cell including a semiconductor substrate, a first conductive type region formed on a surface of the semiconductor substrate, a second conductive type region formed on the other surface of the semiconductor substrate, the second conductive type region being spaced from an edge of the semiconductor substrate and having a conductive type different from that of the first conductive type region, an isolation portion formed at a perimeter of the second conductive type region on the other surface of the semiconductor substrate, a first electrode connected to the first conductive type region, and a second electrode connected to the second conductive type region, wherein the second conductive type region has a boundary portion in a part adjacent to the isolation portion, and in which a doping concentration or a junction depth varies over a width of the boundary portion.
    Type: Application
    Filed: May 28, 2014
    Publication date: December 4, 2014
    Applicant: LG ELECTRONICS INC.
    Inventors: Sunghyun HWANG, Daeyong LEE, Jinsung KIM