Abstract: A system includes a plurality of integrated circuits for propagating data between at least one central processing unit and another component of the system. The plurality of integrated circuits are configured for proximity I/O communication. The plurality of integrated circuits is configured such that data propagation through the plurality of integrated circuits is unaffected by a rotation of at least one of the plurality of integrated circuits by 90 degrees.

Abstract: A computer system detects a power state change and determines that the power state change puts the computer system in a low power state. In turn, the computer system informs an external slot device to enable an external wireless device included in the external slot device.

Abstract: A polling system polls a USB keyboard connected to a USB port of a computing system. A detect module in identifies the keyboard as a low speed USB device. A polling module polls the keyboard with the scheduled interrupt transactions. A key press polling response module detects a key press, stores corresponding key scan data in a key data buffer, and returns the key scan data in response to a scheduled interrupt transaction from the polling module. A key repeat polling response module starts akey repeat polling mode when the key scan data is returned from the key press polling response module, detects whether the key data buffer is empty when a scheduled interrupt transaction is received, and returns the key scan data again if the key scan data buffer is not empty. A stop module stops the key repeat polling mode if the key scan data buffer is empty.

Abstract: A secure communication channel between first and second radio frequency communication devices is indicated by the synchronized indicators on each of the two devices. The indicator may be a light or speaker. After a secure channel is established, the indicators may be simultaneously operated so that a user may definitively and positively determine that the two devices are securely connected to each other. Any interloper devices would not be indicating on the same pattern and thereby be identified.

Abstract: A multi-user online application network computing configuration maintains application level information at a portal or lobby server, rather than at each individual application server or host machine. Users can therefore learn about and select a desired application, such as an online game, through communication with the lobby server. After appropriate authorization processing, users can contact the associated application server, such as a game host, to begin their participation. The lobby server can therefore reduce the bandwidth requirements and other operating demands on the application server. In addition, cross-application communications in real-time are facilitated through the lobby server concept. The multi-user application environment also provides a common data model for maintaining user information, such as for establishing a ladder ranking system in the online gaming context in which user achievements are recorded and shared among users and among the different game applications.

Abstract: A scheduling method and apparatus for use by a processor that controls storage devices of a data storage system is presented. The method allocates processing time between I/O operations and background operations for predetermined time slots based on an indicator of processor workload.

Abstract: In a computer system employing PCI Express (PCIe) links, the PCIe bandwidth is increased by configuring an endpoint device with at least two PCIe interfaces, and coupling the first of these interfaces with a PCIe interface of a system controller and the second of these PCIe interfaces with an expansion PCIe interface of an I/O controller. Therefore, the endpoint device's performance becomes more efficient. For example, if the endpoint device is a graphics processing unit, then the endpoint device can execute more frames per second. When a read request is split up and issued as multiple read requests over the at least two PCIe interfaces, the multiple read completion packets that are received in response thereto are ordered in accordance with the timing of the multiple read requests.

Abstract: An extended Universal-Serial Bus (EUSB) host has reduced loading by using radio frequency (RF) transceivers or direct wiring traces rather than a pair of legacy USB cables. The reduced loading opens the eye pattern. The EUSB device transfers internal data using chained Direct-Memory Access (DMA). Registers in a DMA controller point to a vector table that has vector entries, each pointing to a destination and a source. The source is a memory table for a memory group. The memory table has entries for several memory segments. Each memory-table entry has a pointer to a memory segment and a byte count for the segment. Once all bytes in the segment are transferred, a flag in the entry indicates when another memory segment follows within the memory group. When an END flag is read, then vector table is advanced to the next vector entry, and another memory group of memory segments processed.

Abstract: Disclosed is a multimedia system using a mobile communication terminal and an external connection device for the same. The multimedia system uses a video/audio output device, a peripheral device, and an external connection device. The multimedia system includes a mobile communication terminal having a video/audio output function and a peripheral device control function so that the mobile communication terminal outputs images and sounds by using the video/audio output device and controls the peripheral device; and an external connection device for connecting the mobile communication terminal to the video/audio output device and the peripheral device, relaying the images and sounds from the mobile communication terminal to the video/audio output device, and relaying data transmitted/received between the mobile communication terminal and the peripheral device. When multimedia data is reproduced by using a mobile communication terminal, it is easily connected to an external video/audio output device (e.g.

Abstract: A system and product for a DMA controller with multi-dimensional line-walking functionality is presented. A processor includes an intelligent DMA controller, which loads a line description that corresponds to a shape or line. The intelligent DMA controller moves through a memory map and retrieves data based upon the line description that includes a major step and a minor step. In turn, the intelligent DMA controller retrieves data from the shared memory without assistance from its corresponding processor. In one embodiment, the intelligent DMA controller may analyze a line using the rate of change along its minor axes in conjunction with locations where the line intersects subspaces and store array spans of contiguous memory along the line's major axis.

Abstract: A method and apparatus are provided for implementing system to system communication in a switchless non-InfiniBand (IB) compliant environment. IB architected multicast facilities are used to communicate between HCAs in a loop or string topology. Multiple HCAs in the network subscribe to a predetermined multicast address. Multicast messages sent by one HCA destined to the pre-determined multicast address are received by other HCAs in the network. Intermediate TCA hardware, per IB architected multicast support, forward the multicast messages on via hardware facilities, which do not require invocation of software facilities thereby providing performance efficiencies. The messages flow until picked up by an HCA on the network. Architected higher level IB connections, such as IB supported Reliable Connections (RCs) are established using the multicast message flow, eliminating the need for an IB Subnet Manager (SM).

Abstract: A PC server, connected with a client PC, extracts from a database content satisfying a condition designated from the client PC, and content that does not directly satisfy the designated condition. A pamphlet including the extracted content is output.

Abstract: A mechanism that allows a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, to perform I/O transactions using the PCI host bus, device, and function numbers to validate that an I/O transaction originated from the proper host is provided. Additionally, a method for facilitating identification of a transaction source partition is provided. An input/output transaction that is directed to a physical adapter is originated from a system image of a plurality of system images. The host data processing system adds an identifier of the system image to the input/output transaction. The input/output transaction is then conveyed to the physical adapter for processing of the input/output transaction.

Abstract: A method and system for a programmable input/output transceiver is disclosed. A circuit in accordance with the invention includes a programmable transceiver. The programmable transceiver is configured and/or controlled to support an interface standard. A system according to the present invention includes a programmable transceiver and a field-programmable gate array (FPGA) core coupled to program the programmable transceiver.

Abstract: A system comprises a chassis, an IO interconnect assembly provided in the chassis, and a plurality of IO card receiving units that are installable in the chassis. When the IO card receiving units are installed, the receiving units couple to the IO interconnect assembly. Each IO card receiving unit connects to a corresponding connector on the IO interconnect assembly and provides one or more slots for receiving IO cards. At least one IO card receiving unit has a different number of slots for receiving IO cards than at least one other IO card receiving unit.

Abstract: A workspace control unit performs a process on a common work area screen for sharing information, and an information processor display transmission and reception unit transmits to a display of an information processor the common work area screen processed by the workspace control unit. An information processor manipulation detection unit detects manipulation performed on the common work area screen of the information processor. A peripheral control unit controls a peripheral based on control information managed by a peripheral control information management unit according to the result of detection by the information processor manipulation detection unit.

Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

Abstract: A modularized electronic switching controller assembly for a computer includes a computer device; a hub positioned at a rear end of the computer device; two sides of the hub unit being installed with tracks which are retained in a machine frame; the machine frame being formed by four supporting posts; a support arm connected between the computer-related assembly and the hub for receiving conductive wires; a switching controller installed at the tracks having two racks of the hub unit; a connecting surface of the switching controller having an electric connector; a rear side of the switching controller being installed with at least one connecting port; moving the switching controller through the tracks will make the switching controller entering from a rear end of the machine case; by the connection of the electric connector and the hub unit, the connecting port can be connected to external peripherals or a server.

Abstract: A network storage appliance is disclosed. The storage appliance includes a port combiner that provides data communication between at least first, second, and third I/O ports; a storage controller that controls storage devices and includes the first I/O port; a server having the second I/O port; and an I/O connector for networking the third I/O port to the port combiner. A single chassis encloses the port combiner, storage controller, and server, and the I/O connector is affixed on the storage appliance. The third I/O port is external to the chassis and is not enclosed therein. In various embodiments, the port combiner comprises a FiberChannel hub comprising a series of loop resiliency circuits, or a FiberChannel, Ethernet, or Infiniband switch. In one embodiment, the port combiner, I/O ports, and server are all comprised in a single blade module for plugging into a backplane of the chassis.

Abstract: An architecture that achieves high speed performance in a network protocol handler combines parallelism and pipelining in multiple programmable processors, along with specialized front-end logic at the network interface that handles time critical protocol operations. The multiple processors are interconnected via a high-speed interconnect, using a multi-token counter protocol for data transmission between processors and between processors and memory. Each processor's memory is globally accessible by other processors, and memory synchronization operations are used to obviate the need for “spin-locks”. Each processor has multiple threads, each capable of fully executing programs. Threads within a processor are assigned the processing of various protocol functions in a parallel/pipelined fashion. Data frame processing is done by one or more of the threads to identify related frames.

Abstract: An SCP (System Control Processor) 7 is provided in addition to a CPU 1 responsible for control of circuits in a computer. Upon receiving a Main ON signal (low level) indicative of the CPU 1 being inactive, the SCP 7 responds to a switch operation on a control panel 6 to supply a CD-ROM drive 2 with a command corresponding to the switch operation on said control panel 6 independently of the CPU 1 as well as to feed a high-level CD-POWER-ON signal to a power supply circuit 8 through an OR circuit 9. The power supply circuit 8 selectively supplies the CD-ROM drive 2 and an Audio amplifier 10 with driving power upon receiving the high-level signal.

Abstract: A network storage appliance is disclosed. The storage appliance includes a port combiner that provides data communication between at least first, second, and third I/O ports; a storage controller that controls storage devices and includes the first I/O port; a server having the second I/O port; and an I/O connector for networking the third I/O port to the port combiner. A single chassis encloses the port combiner, storage controller, and server, and the I/O connector is affixed on the storage appliance. The third I/O port is external to the chassis and is not enclosed therein. In various embodiments, the port combiner comprises a FibreChannel hub comprising a series of loop resiliency circuits, or a FibreChannel, Ethernet, or Infiniband switch. In one embodiment, the port combiner, I/O ports, and server are all comprised in a single blade module for plugging into a backplane of the chassis.

Abstract: A portable device includes solid-state memory, an Ethernet and/or wireless network connection, and an HDMI. The portable device receives content guide data from a first server and displays a content guide on a display. In response to a user's selection of a content item, the portable device requests the content item over the Internet from a second server. The portable device receives the content item, stores the content item in solid-state memory, generates display signals that represent the content item, and sends the display signals to a display. The second server may match the content item with relevant advertisements based on keywords associated with the content item and the advertisements. The second server may send selected advertisement URLs to the portable device. Using the URLs, the portable device may obtain the advertisements over the Internet and cause the display to display the advertisements in conjunction with the content item.

Abstract: A signal processing apparatus includes: a connecting means for use in connecting to a different device; a signal control means for changing a control signal to be outputted to the different device through the connecting means for a predetermined period; a changing means for changing the predetermined period; a determining means for determining for each of the predetermined periods changed by the changing means whether the different device stably makes a response to a change in the control signal caused by the signal control means; and a deciding means for deciding a shortest predetermined period from the predetermined periods determined by the determining means that the different device stably makes a response, as a standby time for the different device connected through the connecting means.

Abstract: A method, apparatus and program storage device for managing dataflow through a processing system is disclosed. A buffer monitor maintains and monitors a buffer full threshold to control the write throughput to a data bus.

Abstract: A data transfer method for connecting a master unit on an upstream side and a plurality of slave units on an downstream side in series with serial bus by a daisy chain system and transferring data having an appended error check code or error correction code between a data transmitter and a data receiver, the data transfer method including: transferring the data flowing in the serial bus in the slave unit from the data transmitter to the data receiver without performing an error check or error correction; performing an error check of the data in a circuit provided in the slave unit aside from a circuit in which the data flow; and informing a result of the error check to the master unit individually by the slave unit, which has performed the error check of the data.

Abstract: A method is disclosed to install a component in an information storage and retrieval system. The method provides an information storage and retrieval system comprising a system processor and system data, and a component comprising persistent component data. The method attaches the component to the information storage and retrieval system while the information storage and retrieval system remains in normal operation, and determines, while the information storage and retrieval system remains in normal operation, if the component is compatible with the information storage and retrieval system. If the component is compatible with the information storage and retrieval system, the method then places the component into service while the information storage and retrieval system remains in normal operation.

Abstract: A novel and useful apparatus for and method of a unified IO controller well suited for use in integrated wireless devices incorporating multiple functions. The unified IO controller is operative to provide a single host interface PHY/MAC that is shared among all functions on the controller. The invention provides an IO protocol handler comprising common and unified logic that provides IO access to any function on the device. The common and unified IO PHY interface logic is shared between multiple functions within the same device (e.g., WLAN, GPS, Bluetooth, etc.). This implementation provides optimized hardware partitioning in which common SDIO logic serves multiple functions thereby eliminating the need to provide a protocol handler for each function, reducing pin count, power consumption and die size, since the SDIO protocol handling is implemented in a shared module.

Abstract: A 32-word command IOCB format is disclosed. A conventional 8-word format is supported, although in both cases 32-word command IOCBs are used. When the conventional 8-word format is used, the host sets the LE bit=1 and writes a conventional 8-word command IOCB into words 0-7 of the 32-word command IOCB. The firmware performs a DMA operation and reads the LE bit. With the LE bit=1, the firmware knows to read only words 0-7. When the new 32-word format is used, the host sets the LE bit=0 and writes a 32-word IOCB command into the 32-word command IOCB, including command and response buffer pointers, one or more data buffer pointers, and perhaps the command buffer. The firmware performs a DMA operation and reads the LE bit. With the LE bit=0, the firmware knows to read all 32 words of the command IOCB.

Abstract: Methods, systems, and media for enhancing persistence of a message are disclosed. Embodiments include hardware and/or software for storing of a message in an inbound queue, copying the message to a working queue prior to removing the message from the inbound queue, processing the message base upon the copy in the working queue, and storing a committed reply for the message in an outbound queue. Embodiments may also include a queue manager to persist the message and the committed reply after receipt of the message, to close or substantially close gaps in persistence. Several embodiments include a dispatcher that browses the inbound queue to listen for receipt of messages to process, copy the message to the working queue, and assign the message to a thread to perform processing associated with the message. Further embodiments include persistence functionality in middleware, alleviating the burden of persisting messages from applications like upperware.

Abstract: The present invention extends to methods, systems, and computer program products for managing network response buffering behavior. A computer system receives a request for content from a client. The computer system has a default response buffering behavior used when transferring content. The computer system maps the request to a handler configured to serve the requested content. The computer system accesses buffering behavior data for the handler. The computer system determines that the requested content is to be transferred in accordance with altered response buffering behavior based at least on the buffering behavior data. The altered response buffering behavior corresponds to the requested content as an exception to the default response buffering. The computer system accesses a portion of the requested content from the handler. The computer system transfers the portion of requested content to the client in accordance with the altered response buffer behavior.

Abstract: A memory module is interposed between a host and a disk drive. The memory module includes a solid-state nonvolatile memory used for caching data sent by the host for storage in the disk drive. Caching takes place under the control of a memory controller in the memory module and may be transparent to the host. The disk drive may remain spun-down when data is cached, saving power. The destination for host data may be determined based on desired speed, power consumption and expected need for that data. A host may send specific commands to the memory module to enable additional functions.

Abstract: A CD on which only music information specified by the CD-DA is recorded, or a CD on which both music information specified by the CD-DA and music information to be recorded on a CD-ROM are recorded is mounted upon an information processing terminal. When the CD on which only music information specified by the CD-DA is recorded is mounted, the information processing terminal acquires, from a directory server, an ISRC number that identifies the music information recorded on the CD, and distribution server location information that identifies a content distribution server. The information processing terminal acquires content that is the music information compressed according to the MP3 and encrypted, from the content distribution server identified by the acquired distribution server location information, and the decryption key. The information processing terminal then decrypts the acquired content using the acquired decryption key and reproduces music.

Abstract: Asymmetric hardware support for a special class of threads is provided. Preferably, the special class threads are high-priority, I/O bound threads. In a first aspect, a multithreaded processor contains N sets of registers for supporting concurrent execution of N threads. At least one of the register sets is dedicated for use by a special class of threads, and can not be used by other threads even if idle. In a second aspect, the special class of threads can fill only the a limited portion of the cache memory, in order to reduce flushing of the cache which might otherwise occur.

Abstract: A routing module applies a plurality of routing rules simultaneously to determine routing for a Fibre Channel frame. Each rule independently determines whether the rule applies to the frame as well as a routing result for the frame. The routing result includes a port address, a zoning indicator, and a priority designation that can be used to route the frame over a virtual channel in an interswitch link. A selector chooses between the results returned by the rules. A component receives routing results specifying an ISL group and selects a physical ISL for the frame. An in-band priority determined by the content of the frame header can also be used in place of the priority designation in the routing result.

Abstract: Techniques are provided herein for reducing vibrations in various modes of a dynamic system. One such technique comprises incorporating vibration limiting and sensitivity constraints into a partial fraction expansion equation model of the system so as to reduce vibrations to specific levels. Another technique comprises shaping a command determined using the partial fraction expansion equation model to produce a desired output. The entire command may be shaped or only selected portions thereof which produce vibrations. Another technique involves commanding in current to produce saturation in voltage. By doing this, it is possible to command voltage switches. The times at which the switches occur can be set to reduce system vibrations. Other techniques are also provided. These include varying transient portions at the beginning, middle and/or end of a move and using Posicast inputs, among others.

Abstract: A method for reading input/output port data is provided. In the present method, a write trap procedure is enabled so that the data is stored in a buffer first when there is data to be written in the input/output port. Then, a read trap procedure is enabled so that the data stored in the buffer is read out and used as the data of the input/output port when there is a need to read the data of the input/output port. Therefore, the defect in the prior art that the basic input/output system (BIOS) in a direct input/output mode can only be written in but cannot be read out is resolved.

Abstract: Systems for communication across multiple game applications are provided. In various embodiments, systems of the present invention may include a first application server hosting a first game application, a second application server hosting a second game application that is different from the first game application, a first client device for interaction with the first game application, a second client device for interaction with the second game application, and a universe management server for maintaining information about the first client device and the second client device. The information maintained in the universe management server may include game application interaction information, which allows the universe management server to facilitate real-time communication between a user of the first client device and a user of the second client device. The universe management system may further receive communications from both client devices via the first and second application server.

Abstract: Provided is a stream data processing method that can effectively handle delay data. In the stream data processing method of processing data whose lifetime is defined by a window, an operation result excluding a delay tuple is immediately output along with an unconfirmed flag according to delay processing HBT while a midway processing result necessary for reproduction is retained along with the lifetime, and when the delay tuple arrives, a correct processing result is calculated from the delay tuple and the processing result restore tuple.

Abstract: A method and system for accessing audiovisual data in a computer, which has a hard disk, a hard disk controller and a device driver. The hard disk is divided into a partition region and a non-partition region. The partition region has an audiovisual table to record a location of the audiovisual data stored in the non-partition region. The non-partition region is emulated as an emulated compact disk drive. When the device driver determines to access the emulated compact disk drive, it performs a converting procedure to convert an access instruction to the compact disk drive into an access instruction to the non-partition region, and sets a command register of the hard disk controller in accordance with the instruction converted and the audiovisual table, thereby accessing the non-partition region.

Abstract: An image data serial signal output from the parallel-serial converting circuit 21 is converted into a differential amplitude signal by the LVDS transmitter 22 in such a manner that the amplitude of the differential voltage of the image data parallel signal varies depending on the value of the synchronization code serial signal. Accordingly, the signal values of the synchronization code serial signal and the image data serial signal are simultaneously transmitted. On the reception side, the differential amplitude signal in which the amplitude of the differential voltage of the image data serial signal varies depending on the value of the synchronization code serial signal is received by the LVDS receiver 31. The signal values of the synchronization code serial signal and the image data serial signal are separated and output based on a predetermined comparison processing.

Abstract: A signal processing device is a predetermined signal processing device among signal processing devices which perform signal processing on an input signal that is input to any one of the signal processing devices in such a manner that the signal processing devices share signal processing. The signal processing device includes a signal processing section that performs signal processing on a first-bandwidth signal, which is included in the input signal, in accordance with a processing capability of the signal processing device to generate a first output signal; and a signal integration section that integrates a second output signal with the first output signal, and that outputs the integrated signal to a second different signal processing device, the second output signal being generated in a first different signal processing device by performing signal processing on a second-bandwidth signal, which is included in the input signal.

Abstract: A programmable network component for use in a plurality of network devices with a shared architecture, where the programmable network component includes an interface with an external processing unit to provide management interface control between the external processing unit and a network device. The programmable network component also includes a plurality of internal busses each of which is coupled to the programmable network component and to at least one network component. The programmable network component further includes a plurality of external buses each of which is coupled to the programmable network component and to at least one physical interface. The programmable network component is configured to support a plurality of protocols for communication with a plurality of physical interface components and comprises a plurality of programmable registers for determining the status of the plurality of physical interfaces.

Abstract: A system and method for communicating between graphical programs executing on respective devices, e.g., a programmable hardware element and a controller. The system includes a first node representing a direct memory access structure, e.g., a first in, first out data structure (DMA FIFO), and a second node providing a controller interface to the DMA FIFO. A first portion of the DMA FIFO is implemented on the programmable hardware element, and a second portion of the DMA FIFO is implemented in memory of the controller. The first and second nodes are operable to be included respectively in first and second graphical programs, where the first graphical program, including the first node, is deployable to the programmable hardware element, where the second graphical program, including the second node, is deployable to the controller, and where the first and second graphical programs communicate via the DMA FIFO in cooperatively performing a specified task.

Abstract: Secrecy of printed matter is raised and charges for a storing area are more accurately charged. According to the invention, a printing apparatus is instructed so as to store print data corresponding to a print request into one of a plurality of storing areas. The print data is transmitted to the printing apparatus. The user is notified of authentication information corresponding to the print data stored in one of the plurality of storing areas.

Abstract: A data transfer apparatus with hub and ports includes design configurable hub interface units (HIU) between the ports and corresponding external application units. The configurable HIU provides a single generic superset HIU that can be configured for specific more specialized applications during implementation as part of design synthesis. Configuration allows the super-set configurable HIU to be crafted into any one of several possible special purpose HIUs. This configuration is performed during the design phase and is not applied in field applications. Optimization aimed at eliminating functional blocks not needed in a specific design and simplifying and modifying other functional blocks allows for the efficient configuring of these other types of HIUs. Configuration of HIUs for specific needs can result in significant savings in silicon area and in power consumption.

Abstract: A micro range RF data transmission system comprising at least one transmitter incorporated in a moving device and at least one receiver positioned along a fixed path that can be aligned to create a data transfer point. The moving device moves along a fixed path. Each of the at least one receiver is positioned along the fixed path such that when the moving device moves along the fixed path, one of the transmitters aligns with one of the receivers creating the data transfer point. The transmitter will only transmit a micro range signal when the transmitter is at the data transfer point. Each receiver includes an electromagnetic shield formed around the perimeter of the receiver to form a directional channel for the micro range signal. A control system is used for controlling an industrial sheet-making device. The control system uses multiple data transfer points as the backbone for bi-directional communication.

Abstract: A primary-side regulation (PSR) controller integrated circuit includes a PSR CC/CV controller and a non-volatile shift register. An assembled power supply that includes the integrated circuit is in-circuit tested to determine errors in power supply output voltage and/or current. Programming information is determined and shifted into the shift register. During programming, the power supply regulates to a different output voltage, and the different voltage is used for shift register programming. After programming, the power supply operates in a normal mode so that the output voltage and current are within specification. The voltage and current to which the power supply regulates are set by some of the bits of the programming information.

Abstract: A multi-port memory, comprising: m (m?2) input/output ports independent of one another; n (n?2) memory banks independent of one another; and a route switching circuit capable of optionally setting signal routes of a command, an address, and input/output data between the m input/output ports and the n memory banks, wherein the route switching circuit allocates p (1?p?m) input/output ports optionally selected from the m input/output ports to a memory bank optionally selected from the n memory banks.

Abstract: A customization program for use in customizing a baseboard management controller used for monitoring operation of various computer system components is disclosed. A user interacts with the customization program to customize the baseboard management controller based on a configuration of components specified for the baseboard of the computer system. The customization program provides a user interface having a repository of icons and a design page. The icons represent various components that may be connected, directly or indirectly, to the baseboard. The design page is used for constructing a model representing the specified configuration of components. As a user drags icons onto the design page, the model is updated to reflect selection of the components corresponding to these icons. Further, the customization program creates a configuration file that identifies and describes each of the selected components.