Input/output Data Processing Patents (Class 710/1)
  • Patent number: 9361348
    Abstract: A database server receives a request from a client application for performing a data transaction on persistent data storage. The request is sent to a set of replication servers. An acknowledgement for the request is received from each replication server, including a start sequence number and an end sequence number for data that is stored in local cache of the replication server, and a latest committed sequence number for data that was written to the persistent data storage by the replication server. A maximum value of latest committed sequence numbers received from the set of replication servers is determined. For each replication server, it is examined whether there is a gap between the start sequence number for data stored in local cache and the maximum value of the latest committed sequence numbers. Based on the examining, it is determined whether there is an occurrence of loss of data.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: June 7, 2016
    Assignee: Google Inc.
    Inventors: Kenneth M. Ashcraft, Vishal Kasera, Jean-Michel Leon, Amit Agarwal
  • Patent number: 9348618
    Abstract: A measuring instrument includes at least one processor having at least one processor internal resource. The measuring instrument may also include at least one hardware component external to the processor and at least one storage component. Firmware may be stored in the storage component and is accessible by the processor. The firmware includes at least one application; a virtualized hardware system having routines that emulate at least one processor internal resource; and at least one application programming interface between the application and the virtualized hardware system.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: May 24, 2016
    Assignee: Aclara Meters LLC
    Inventors: Robert Patrick Keeney, Bruce Robert Ladeau, Rajeswara Rao Pasupuleti
  • Patent number: 9342458
    Abstract: System and method for operating a solid state memory containing a memory space. The present invention provides a computerized system that includes a solid state memory having a memory space; a controller adapted to use a first portion of the memory space as a cache; and a garbage collector adapted to use a second portion of the memory space to collect garbage in the solid state memory. The controller is adapted to change a size of at least one of the first portion and the second portion of the memory space during operation of the solid state memory.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: May 17, 2016
    Assignee: International Business Machines Corporation
    Inventors: Xiao-Yu Hu, Nikolas Ioannou, Ioannis Koltsidas
  • Patent number: 9336357
    Abstract: Systems and methods may provide implementing one or more device locking procedures to block access to a device. In one example, the method may include receiving an indication that a user is no longer present, initiating a timing mechanism to set a period to issue a first device lock instruction to lock a peripheral device, relaying timing information from the timing mechanism to a controller module associated with the peripheral device; and locking the peripheral device upon expiration of the period.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: May 10, 2016
    Assignee: Intel Corporation
    Inventors: Ned Smith, Purushottam Goel, Victoria Moore
  • Patent number: 9319365
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for storing and transferring messages. An example method includes providing a queue having an ordered plurality of storage blocks. Each storage block stores one or more respective messages and is associated with a respective time. The times increase from a block designating a head of the queue to a block designating a tail of the queue. The method also includes reading, by each of a plurality of first sender processes, messages from one or more blocks in the queue beginning at the head of the queue. The read messages are sent, by each of the plurality of first sender processes, to a respective recipient. One or more of the blocks are designated as old when they have associated times that are earlier than a first time. A block is designated as a new head of the queue when the block is associated with a time later than or equal to the first time.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: April 19, 2016
    Assignee: Machine Zone, Inc.
    Inventor: Igor Milyakov
  • Patent number: 9313373
    Abstract: A display apparatus for receiving broadcasting includes a display unit configured to display an image thereon, a cover which partially covers the display unit, at least one signal connector which is configured to connect to a portable signal processing module that is located outside the cover and processes a signal to be displayed by the display unit, and receives the signal processed by the signal processing module, and a timing controller (T-con) configured to control a display timing of the signal received by the at least one signal connector.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: April 12, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-yong Son, Ho-woong Kang, Hak-jae Kim, Woo-jung Kim, Jae-hyo Lim
  • Patent number: 9312088
    Abstract: A circuit breaker includes a breaker handle that is remotely operated using a modular actuator mechanism. The actuator mechanism may be a solenoid or other electromechanical actuator that converts an electrical signal to a mechanical force which is applied to the breaker handle. The actuator mechanism is mechanically connected to the circuit breaker in a removable fashion, such as by a tab-and-slot connection, and electrically connected to the circuit breaker in a removable fashion using a plug, edge connector, or other suitable mechanism such that the electrical connection is made when the actuator mechanism is installed, and without the need for additional wiring or other installation steps.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: April 12, 2016
    Assignee: CARLING TECHNOLOGIES, INC.
    Inventor: Richard Sorenson, Sr.
  • Patent number: 9297841
    Abstract: A method and apparatus for managing an electronic appliance, which determines an abnormality of the electronic appliance, such as a malfunction or worn out of the electronic appliance, based on power consumption information measured in the electronic appliance while an operation requested by a user of the electronic appliance is performed by the electronic appliance, and past power consumption information about the same operation performed by the same electronic appliance, and a non-transitory computer-readable recording medium having recorded thereon a program to execute the method.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: March 29, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jake Chun, Jeong-il Seo, Dong-ik Lee
  • Patent number: 9286726
    Abstract: A mobile information gateway comprises a wearable human interface module having an image delivery and display mechanism for presenting information overlaid upon a wide field of view, a computing and communication module adapted receive information from the human interface module and adapted to send commands and information to the human interface module including information for presentation; and a backend service server coupled for processing data from the computing and communication module including user identification and verification.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: March 15, 2016
    Assignee: Ricoh Company, Ltd.
    Inventors: Nikhil Balram, Kathrin Berkner, Ivana Tosic, Wanmin Wu
  • Patent number: 9286249
    Abstract: A universal serial bus (USB) device communication method that relates to the field of communications includes: receiving, by a USB device, a device type query message sent by a peer device, where a human interface device (HID) descriptor and a HID report descriptor are added to a driver of the USB device; sending, by the USB device according to the HID descriptor and HID report descriptor, a query response message that carries a HID identifier to the peer device, where the HID identifier is used to enable the peer device to identify the USB device as a HID device; and encoding and encapsulating, by the USB device, data to be sent to generate a HID packet, and sending the HID packet to the peer device, or receiving a HID packet from the peer device, and decapsulating and decoding the received HID packet, where the HID packet carries a data type and data usage manner information.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: March 15, 2016
    Assignee: Huawei Device Co., Ltd.
    Inventor: Shubin Li
  • Patent number: 9280290
    Abstract: A system may include a processor which may include a cache memory and a Direct Memory Access (DMA) controller, a peripheral device on an I/O expansion bus, and a bus interface coupled to the I/O expansion bus and the processor. The bus controller may determine if data packets sent from the peripheral device to the processor include a DMA write instruction to the cache memory with an optional desired cache location. Upon determining a DMA write instruction to the cache memory is included in the data packet, the bus controller may format the data in the data packet for storage in the cache and either receive the desired cache location or determine an appropriate location within the cache to store the formatted data. The bus controller may determine an alternate location within the cache if the desired location within the cache cannot accept more data from the peripheral device.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: March 8, 2016
    Assignee: Oracle International Corporation
    Inventors: John R Feehrer, Hugh R Kurth, Aron J Silverton, Patrick Stabile
  • Patent number: 9268645
    Abstract: Techniques are disclosed that include a computer-implemented method, including storing information related to an initial state of a process upon being initialized, wherein execution of the process includes executing at least one execution phase and upon completion of the executing of the execution phase storing information representative of an end state of the execution phase; aborting execution of the process in response to a predetermined event; and resuming execution of the process from one of the saved initial and end states without needing to shut down the process.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: February 23, 2016
    Assignee: AB INITIO TECHNOLOGY LLC
    Inventors: Bryan Phil Douros, Joseph Skeffington Wholey, III
  • Patent number: 9268362
    Abstract: A method for controlling a cursor of a portable electronic apparatus having a display screen and a motion sensor is provided. The motion sensor detects a first-axis rotation angle and a second-axis rotation angle of the apparatus. A first-axis coordinate of a cursor is determined according to the first-axis rotation angle, a-first axis maximum rotation angle and a length of a short side of the display screen. A second-axis coordinate of the cursor is determined according to the second-axis rotation angle, a maximum second-axis rotation angle and a length of a long side of the display screen. The cursor is moved according to the first-axis coordinate and the second-axis coordinate.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: February 23, 2016
    Assignee: Wistron Corp.
    Inventor: Shao-Fong Chen
  • Patent number: 9257181
    Abstract: An output circuit of a nonvolatile memory device includes a sense amplification circuit configured to, during a sensing operation, generate output data based on a comparison between a first voltage on a data line and a reference voltage on a reference data line during a sensing operation, the first voltage corresponding to data read from at least one memory cell, and the sense amplification circuit being further configured to connect the reference data line with a ground terminal during the sensing operation.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: February 9, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taesung Lee, Jaewoo Im
  • Patent number: 9258257
    Abstract: Rate limiting operations can be implemented at an ingress DMA unit to minimize the probability of dropped packets because of differences between the communication rates of the ingress DMA unit and a packet processing engine. The communication rate associated with each of the software ports of a communication device can be determined and an aggregate software port ingress rate can be calculated by summing the communication rate associated with each of the software ports. The transfer rate associated with the ingress DMA unit can be limited so that packets are transmitted from the ingress DMA unit to the packet processing engine at a communication rate that is at least equal to the aggregate software port ingress rate. If each software port comprises a dedicated rate-limited ingress DMA queue, packets from a rate-limited ingress DMA queue can be transmitted at the at least the communication rate of the corresponding software port.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: February 9, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Rahul Malik, Aaditya Rai, Samarjeet Banerjee, Abhishek Rastogi
  • Patent number: 9236110
    Abstract: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.
    Type: Grant
    Filed: June 30, 2012
    Date of Patent: January 12, 2016
    Assignee: Intel Corporation
    Inventors: Kuljit S. Bains, John B. Halbert, Christopher P. Mozak, Theodore Z. Schoenborn, Zvika Greenfield
  • Patent number: 9223896
    Abstract: An apparatus, method and screen recording medium are provided. The apparatus includes a determining unit which determines, in response to a request to perform processing including a screen transition and the request is transmitted from a client device via a network, whether a screen definition data, as a transition destination, associated with a client identifier relating to the client device is stored in a screen definition data storage unit, and a generating unit which generates, when the screen definition data is stored, a data of the screen functioning as the transition destination by using the screen definition data and generates, when the screen definition data is not stored, a data of the screen functioning as the transition destination by using a common screen definition data.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: December 29, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Noboru Kurumai, Takeo Yasukawa
  • Patent number: 9215089
    Abstract: A touch sensor system includes buses, a plurality of touch sensor devices disposed on the buses, and an information integrating device that is connected to all the buses and integrates information from the touch sensor device. The touch sensor device includes a sensor unit and a signal processing unit that transmits a sensor data signal generated by processing an analog sensor signal to the information integrating device through the bus. The signal processing unit includes a digital converting unit, a threshold evaluating unit that gives a start permission of the signal process when a sensor value exceeds a preset threshold, an ID adding unit that adds a transmitter identification number to the sensor signal, and a data transmitting unit that outputs the sensor data signal to a signal line of the bus. Fast responses are made possible without increasing the amount of data and host processing load while including many touch sensor elements.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: December 15, 2015
    Assignees: TOHOKU UNIVERSITY, KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masanori Muroyama, Masayoshi Esashi, Shuji Tanaka, Sakae Matsuzaki, Mitsutoshi Makihata, Yutaka Nonomura, Motohiro Fujiyoshi, Takahiro Nakayama, Ui Yamaguchi, Hitoshi Yamada
  • Patent number: 9210352
    Abstract: A high definition multimedia interface using a modified format switcher for controlling electronic hardware. The modified format switcher enables infrared, RS-232, TCPIP, audio, and consumer electronics control interconnection with the high definition multimedia interface.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: December 8, 2015
    Assignee: KEY DIGITAL SYSTEMS, INC.
    Inventors: Mikhail Tsinberg, Ilsoo Yu, Leon Glenn Tsinberg
  • Patent number: 9202541
    Abstract: A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a mode information storage unit that stores first and second mode information, the first and second mode information being able to be set through the first bus-interface circuit, a first memory core that operates based on the first mode information, the first memory core being connected to the first bus-interface circuit and supplied with a first clock signal, a second memory core, the second memory core being supplied with a second clock signal and a select circuit that selectively connects the second memory core to the first or second bus-interface circuit based on predetermined switching information, in which the second memory core operates based on the second mode information when the second memory core is connected to the second bus-interface circuit.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: December 1, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shuuichi Senou, Kenjyu Shimogawa, Susumu Takano, Toshihiko Funaki, Hideaki Arima
  • Patent number: 9185823
    Abstract: The present invention is directed to server systems and methods thereof. More specifically, embodiments of the present invention provides a memory controller within a server system, where the memory controller is disengageably connected to one or more processors, a plurality of volatile memory modules, and plurality of solid-state memory modules. This memory controller may be connected to other similarly configured memory controllers. The volatile and solid-state memory modules can be removed and/or replaced. There are other embodiments as well.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: November 10, 2015
    Assignee: Inphi Corporation
    Inventors: Christopher Haywood, Chao Xu, Fouad G. Tamer
  • Patent number: 9178355
    Abstract: A multi-phase power control switch has multiple power controller channels, each of which includes at least one power controller having a microprocessor. Each of the microprocessors cross communicates with each other of the microprocessors using a data bus.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: November 3, 2015
    Assignee: Hamilton Sundstrand Corporation
    Inventors: Norbert J. Simper, Markus Greither, Alexander Michel, Carl A. Wagner, Andrew David Bellis
  • Patent number: 9172556
    Abstract: An interfabric link between two separate Fiber Channel fabrics so that devices in one fabric can communicate with devices in another fabric without requiring the merger of the two fabrics. The interfabric switch performs a conversion or a translation of device addresses in each fabric so that they are accessible to the other fabric. In a first embodiment the external ports of the interfabric switch are configured as E_ports. A series of internal ports in each interfabric switch are joined together forming a series of virtual or logical switches. In a second embodiment the external ports are configured as NL_ports and the connections between the virtual switches are E_ports. The virtual switches in the interfabric switch match domains with their external counterparts so that the virtual switches effectively form their own fabric.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: October 27, 2015
    Assignee: Brocade Communications Systems, Inc.
    Inventors: Christopher A. Del Signore, Vineet M. Abraham, Satish K. Gnanasekaran, Pranab Patnaik, Vincent W. Guan, Balakumar N. Kaushik
  • Patent number: 9164930
    Abstract: A docking system utilizing a single DisplayPort cable connection to a computer system is provided. In one embodiment, the docking system includes a single DisplayPort (“DP”) input, a management layer module coupled to receive video inputs from the single DP input and to provide video data to at least one video monitor output, and a USB layer module coupled to receive an AUX channel from the single DP input and to couple the AUX channel with a USB hub.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: October 20, 2015
    Assignee: Synaptics Incorporated
    Inventors: Henry Zeng, Ji Park
  • Patent number: 9152594
    Abstract: A semiconductor memory device includes a memory cell array section including a plurality of memory cell arrays, a peripheral circuit section, and an internal bus connecting the plurality of memory cell arrays and the peripheral circuit section. The peripheral circuit section includes external input/output buffers, and bus interface circuits. The bus interface circuits execute conversion between data inputted/outputted in parallel to/from the memory cell arrays through the internal bus and data inputted/outputted in serial through the plurality of external input/output buffers. The bus interface circuits are densely arranged between the internal bus and the input/output buffers, so that a width d1 of the area of the plurality of bus interface circuits being arranged is narrower than a width d2 of the area of the external input/output buffers being arranged and a bus width maximum value d3 of the internal bus.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: October 6, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Nakaba Kaiwa, Yoshinori Matsui
  • Patent number: 9150043
    Abstract: A book for use in an augmented reality system includes first and second pages. The first page is on a first leaf of the book and includes a first fiduciary marker for indicating the orientation of the book to a recognition system. The second page is on a second leaf of the book and includes a second fiduciary marker for indicating the orientation of the book to the recognition system and also page marker for indicating the page number of the second page to the recognition system. The page marker orientation is ambiguous without reference to a fiduciary marker. The page marker is positioned on the second page closer to an edge of the page than the second fiduciary marker to become visible to the recognition system before the second fiduciary marker, as the book is turned to the second page.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: October 6, 2015
    Assignee: Sony Computer Entertainment Europe Limited
    Inventors: Nicholas Andrew Lord, Thomas Lucas-Woodley, William Oliver Sykes, Adrien Bain
  • Patent number: 9152587
    Abstract: A method and circuit for a data processing system provide a partitioned interrupt controller with an efficient deferral mechanism for processing partitioned interrupt requests by executing a control instruction to encode and store a delay command (e.g., DEFER or SUSPEND) in a data payload with a hardware-inserted partition attribute (LPID) for storage to a command register (25) at a physical address (PA) retrieved from a special purpose register (46) so that the partitioned interrupt controller (14) can determine if the delay command can be performed based on local access control information.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: October 6, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Bryan D. Marietta, Gary L. Whisenhunt, Kumar K. Gala, David B. Kramer
  • Patent number: 9133019
    Abstract: The invention provides a sensor probe which has: one or more microelectromechanical systems (MEMS) sensors configured to sense one or more parameters and a communication bus in electrical communication therewith. The one or more sensors and communication bus are disposed on a substrate. The sensor probe includes a digital storage module in which a unique probe identifier is stored and which is in electrical communication with the communication bus. The probe includes, a cable, a first end of which is in electrical communication with the communication bus and a second end of which is in electrical communication with a remote monitoring unit. The cable is configured to provide electrical power received from the remote monitoring unit to the one or more sensors, via the communication bus, and to communicate data received from the one or more sensors, via the communication bus, to the remote monitoring unit.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: September 15, 2015
    Inventors: Barry John McCleland, Eugene Christiaan van Beljon
  • Patent number: 9122537
    Abstract: According to one embodiment, availability information describing virtual machines running on physical machines is accessed. The availability information associates each virtual machine with a physical resource used by the virtual machine. Use by the virtual machines is determined from the availability information. Availability of the physical resources is determined according to the use. Server load is balanced according to the availability of the physical resources. According to another embodiment, the following is performed until a load is accommodated: selecting a server having a load that is less than an expansion threshold; loading the server until the expansion threshold is reached; selecting a next server having a load that is less than a next expansion threshold; and loading the next server until the next expansion threshold is reached. Load of a low load server is determined to be below a contraction threshold, and the low load server is drained.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: September 1, 2015
    Assignee: Cisco Technology, Inc.
    Inventors: Alpesh S. Patel, Chris O'Rourke, Mark Albert, Robert A. Mackie, Walter G. Dixon
  • Patent number: 9116761
    Abstract: A transactional middleware system can exchange messages between a local machine and a remote machine using Remote Direct Memory Access (RDMA) protocol to achieve short latency in a manner like a local message transfer. The transactional middleware machine environment can prevent single-point bottleneck and achieve short latency. The transactional middleware machine environment comprises a first message queue associated with a server in a first transactional machine, wherein the server operates to be accessed using a queue address in the first message queue. The transactional middleware machine environment further comprises a second message queue associated with a client in a second transactional machine. The client operates to send a service request message to the server directly using the first message queue, and the server operates to receive the service request message from the first message queue and send a service response message directly to the client using the second message queue.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: August 25, 2015
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Todd Little, Yongshun Jin, Erli Niu
  • Patent number: 9112487
    Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: August 18, 2015
    Assignee: Broadcom Corporation
    Inventor: Armond Hairapetian
  • Patent number: 9104339
    Abstract: In response to a request received from a guest alignment module, host alignment module determines a target starting location in a virtual hard disk to which the beginning of a guest partition of a virtual machine is written. Host alignment module translates a guest partition's virtual hard disk address into a physical hard disk address and determines whether the physical hard disk address is track aligned with disk tracks of the physical hard disk. If the physical hard disk address is not track aligned, host alignment module determines a new track aligned physical hard disk address as the target starting location. If the physical hard disk address is track aligned, the same physical hard disk address is used as the target starting location. The target starting location is returned to the guest alignment module as a new virtual hard disk address.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: August 11, 2015
    Assignee: Symantec Corporation
    Inventors: Santosh Pravin Kalekar, Vipul Jain
  • Patent number: 9107027
    Abstract: Some demonstrative embodiments include a wireless connector and devices and/or systems utilizing one or more wireless connectors. For example, a device may include a wireless connector to be coupled to another device for communicating data with the other device, the wireless connector including a wireless communication unit to communicate the data over a wireless communication link, for example, a short-range wireless communication link, e.g. at a multi-gigabit-per second (MGbs) rate.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: August 11, 2015
    Assignee: INTEL CORPORATION
    Inventor: Eran Sudak
  • Patent number: 9092144
    Abstract: An input and output method includes connecting a storage apparatus to an information processing apparatus via a plurality of paths, storing management information for a timeout time of each of the plurality of paths in a storage unit of the storage apparatus, and acquiring the timeout time of a path and another path of an input/output issuance destination for the storage apparatus from the storage unit depending on the path and the another path.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: July 28, 2015
    Assignee: FUJITSU LIMITED
    Inventor: Kyuu Kobashi
  • Patent number: 9081472
    Abstract: A definition of a new user interface feature of a business software architecture supporting a business configuration used by an organization can be received and a rule in a scenario model of a business scenario can be accordingly modified to associate the new user interface feature with business process feature(s) of the business scenario. A selection of a business process feature received as a user interaction with first user interface elements arranged in a linear order in a navigation pane of a user interface to represent at least some of the plurality of business process features of the business process can result in the concurrent display via the user interface of a work frame comprising the new user interface feature.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: July 14, 2015
    Assignee: SAP SE
    Inventors: Holger Knospe, Marianne Brosche, Ulrich Keil, Jochen Mayerle, Joachim Fessler
  • Patent number: 9075628
    Abstract: Provided is an electronic system capable of dynamically switching a communication speed among a plurality of electronic devices connected in series. A first communication device and a second communication device are connected in series to a host controller. After controlling the communication speed of the second communication device to be a communication speed defined in advance, the host controller controls the communication speed of the first communication device to be the same communication speed as the communication speed of the second communication device.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: July 7, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenji Kuroki, Keita Takahashi, Satoru Yamamoto, Takuya Hayakawa, Kuniyasu Kimura
  • Patent number: 9075676
    Abstract: An information processing terminal is provided with a data acquiring means for reading data from an external recording medium; a program storing means for storing a plurality of application programs; a program executing means for executing the stored application programs; and a program selecting means for selecting the application program to be executed by the program executing means. The program selecting means selects the application program to be executed from the programs stored in the program storing means, corresponding to the data acquired through the data acquiring means, and processes the data acquired through the data acquiring means by the application program selected by the program selecting means.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: July 7, 2015
    Assignees: NEC CORPORATION, NEC Communication Systems Ltd.
    Inventors: Tomoharu Yamaguchi, Mie Noda, Yuichi Nino
  • Patent number: 9069472
    Abstract: Methods and systems to disperse and collate I/O from virtual machines (VMs) among a plurality of near line controllers for parallelization of I/O's (parallel reads and parallel writes) and for providing redundancy for stored VM data is disclosed.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: June 30, 2015
    Assignee: Atlantis Computing, Inc.
    Inventors: Chetan Venkatesh, Kartikeya Iyer
  • Patent number: 9069342
    Abstract: A method for operating a drive control device includes sending and receiving data over a bus connected to a bus port of a drive control device which has in addition to the bus port a communication interface and a memory, loading into the memory a basic functionality, which includes a software interface, for controlling and/or regulating a connected motor, loading into the memory during operation of the drive control device a functionality of a web server which cooperatively interacts with the basic functionality via the software interface, and forwarding to the web server incoming data received via the communication interface for editing or processing.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: June 30, 2015
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventor: Alexander Pfister
  • Patent number: 9059906
    Abstract: Embodiments of the invention provide a data communication interface which includes a controller module, a switching module and a data port. The controller module is operable to monitor a status of a power line of the data port and, if the power line has a first status, to transmit a first communication mode instruction to the switching module. If the power line has a second status, the controller module is configured to transmit a second communication mode instruction to the switching module. The switching module is configured to receive a communication mode instruction from the controller module and, if the first communication mode instruction is received, to route data communication lines corresponding to a first communication protocol to the data port. If the second communication mode instruction is received, the switching module is configured to route data communication lines corresponding to a second communication protocol to the data port.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: June 16, 2015
    Inventors: Barry John McCleland, Eugene Christiaan van Beljon
  • Patent number: 9060242
    Abstract: Some demonstrative embodiments include a wireless connector and devices and/or systems utilizing one or more wireless connectors. For example, a device may include a wireless connector to be coupled to another device for communicating data with the other device, the wireless connector including a wireless communication unit to communicate the data over a wireless communication link, for example, a short-range wireless communication link, e.g. at a multi-gigabit-per second (MGbs) rate.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: June 16, 2015
    Assignee: INTEL CORPORATION
    Inventor: Eran Sudak
  • Patent number: 9052799
    Abstract: An image forming apparatus includes a unit configured to manage screen type information including a type that indicates a dependence relationship between UT screens, a unit configured to manage placement item type information including a type that indicates whether to reflect customization of a first UI screen into a placement item to be placed on a second UI screen depending on the first UI screen, a unit configured to perform management and display control for configurations of plural UI screens and a unit configured to, when a placement item of a predetermined UI screen that is display-controlled is customized, determine whether to reflect customization of the predetermined UI screen into a UI screen that depends on the predetermined UI screen based on the screen type information of the predetermined UI screen and the placement item type information of the placement item of the customization target.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: June 9, 2015
    Assignee: RICOH COMPANY, LTD.
    Inventor: Tohru Sasaki
  • Patent number: 9043493
    Abstract: A virtual machine (VM) migration from a source virtual machine monitor (VMM) to a destination VMM on a computer system. Each of the VMMs includes virtualization software, and one or more VMs are executed in each of the VMMs. The virtualization software allocates hardware resources in a form of virtual resources for the concurrent execution of one or more VMs and the virtualization software. A portion of a memory of the hardware resources includes hardware memory segments. A first portion of the memory segments is assigned to a source logical partition and a second portion is assigned to a destination logical partition. The source VMM operates in the source logical partition and the destination VMM operates in the destination logical partition. The first portion of the memory segments is mapped into a source VMM memory, and the second portion of the memory segments is mapped into a destination VMM memory.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: May 26, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Utz Bacher, Reinhard Buendgen, Einar Lueck, Angel Nunez Mencias
  • Patent number: 9037752
    Abstract: A system includes reception of a client query identifying data stored by a remote data source, generation of a remote query of the remote data source based on the client query, determination of a cache name based on the remote query, determination of whether the remote data source comprises a cache associated with the cache name and, if it is determined that the remote data source comprises a valid cache associated with the cache name, instruction of the remote data source to read the data of the cache, and reception of the data of the cache from the remote data source.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: May 19, 2015
    Assignee: SAP SE
    Inventors: Shahul Hameed P, Shasha Luo, Sinisa Knezevic, Engin Dogusoy, Petya Nikolova
  • Patent number: 9032397
    Abstract: A data processing system facilitates virtual machine migration with direct physical access control. The illustrative data processing system comprises a software-programmable trap control associated with hardware registers of a computer that selectively vectors execution control of a virtual machine (VM) between a host and a guest. The data processing system further comprises a logic which is configured for execution on the computer that programs the trap control to enable the virtual machine to directly access the hardware registers when the virtual machine is not migrated and to revoke direct access of the hardware registers in preparation for virtual machine migration.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: May 12, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Troy Miller, Mark A. Criss, Jerry James Harrow, Jr., Thomas Turicchi, Michael Wisner
  • Patent number: 9032099
    Abstract: Multi-level memory architecture technologies are described. One processor includes a requesting unit, a first memory interface to couple to a far memory (FM), a second memory interface to couple to a near memory (NM) and a multi-level memory controller (MLMC) coupled to the requesting unit, the first memory interface and the second memory interface. The MLMC is to write data into a memory page of NM in response to a request from the requesting unit to retrieve the memory page from FM. The MLMC receives a hint from the requesting unit and clears a writeback bit for the memory page indicated in the hint. The hint indicates that the data contained in the memory page of the NM is not to be subsequently requested by the requesting unit. The MLMC starts a writeback operation of a memory sector including the memory page and one or more additional memory pages.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: May 12, 2015
    Assignee: Intel Corporation
    Inventors: Jorge E. Parra, Marc Torrant, Joydeep Ray
  • Patent number: 9032112
    Abstract: In one embodiment, a method includes storing, in a storage unit, a number of data transfer requests to issue for a data request signal. Data transfer requests are issued to a direct memory access (DMA) controller of a system for transfer of data to a buffer unit. The stored number of data transfer requests is determined. The issuance of data transfer requests are stopped when the stored number of data transfer requests is met.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: May 12, 2015
    Assignee: Marvell International Ltd.
    Inventor: Pinaki Mukherjee
  • Patent number: 9027015
    Abstract: A device and method of connecting an interactive communication system to a processing device. The device is a cable system that includes first and second ends. The first end of the cable system has a leg connector, while the second end of the connector system has first and second arm connectors. The method implements the cable system to load or run software onto the processing device, and includes connecting the leg connector to an interactive communication system; connecting the first arm connector having a memory device to the processing device, wherein the memory device includes predetermined software; loading/running the software on the processing device; disconnecting the first arm connector having the memory device from the processing device; and connecting a second arm connector to the processing device.
    Type: Grant
    Filed: August 14, 2008
    Date of Patent: May 5, 2015
    Assignee: Steelcase, Inc.
    Inventors: Peter W. Hildebrandt, Ian G. Hutchinson, James D. Watson, Michael H. Dunn, Neal A. Hofmann, Scott E. Wilson, Brent W. Anderson, Louis Ashford, Richard Meissner
  • Patent number: 9021151
    Abstract: A video processing device includes a connecting unit that is connected to an external apparatus via an interface including a HPD line and a DDC line, a memory that stores EDID, with the EDID being transmitted via the DDC line; and a control unit that performs a predetermined process for resetting a state of the HPD line if a predetermined error relating to a transmission of EDID is detected. The control unit changes a state of the video processing device to a power off state if a number of times that the predetermined process is performed is not less than a predetermined value.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: April 28, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masaya Yagi
  • Patent number: 9021141
    Abstract: A data storage controller exposes information stored in a locally managed volatile memory store to a host system. The locally managed volatile memory store is mapped to a corresponding portion of a peripheral component interconnect express (PCIe) compliant memory space managed by the host system. Backup logic in the data storage controller responds to a power event detected at the interface between the data storage controller and the host system by copying the contents of the volatile memory store to a non-volatile memory store on the data storage controller. Restore logic restores a data storage controller state by copying the contents of the non-volatile memory store to the locally managed volatile memory store upon the application of power such that the data in the volatile memory store is persistent even in the event of a loss of power to the host system and or the data storage controller.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: April 28, 2015
    Assignee: LSI Corporation
    Inventors: Mohamad El-Batal, Anant Baderdinni, Mark Ish, Jason M. Stuhlsatz