Abstract: In a process of printing an arbitrary text string using a composite print function, in a case where font extension using a font of a display language is not possible, a character at a first position in the text string is extracted and a font is retrieved that allows font extension for the extracted character. Using the retrieved font, font extension is performed for the text string.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

Abstract: The present invention relates to the field of communications technologies, and discloses methods for transmitting and storing downlink data, a base station, and a terminal. In this solution, each time when a base station transmits downlink data, bits are selected in such a way that a length and a start point of a sequence that a terminal of any terminal category expects to receive in initial transmission (or retransmission) of a code block are the same as a length and a start point of a sequence that a transmit end determines to transmit for the same code block, so that the terminal can perform reliable decoding. Therefore, a disadvantage is avoided that the terminal cannot correctly perform storing and further cannot correctly perform decoding each time when the terminal stores a retransmitted code block for a same code block, and decoding accuracy of the terminal is improved.

Abstract: Disclosed are techniques for selecting one or more reference voltages for performing one or more operations on a memory cell based on a determined layer of a three-dimensional memory construct to which the memory cell belongs. The one or more operations can include read or write operations. The memory cell can be a flash memory cell.

Abstract: A payment terminal such as a payment reader may receive and form electrical connections with an electronic transaction card such as an EMV chip card. The payment terminal may provide a clock signal at a rate that exceeds a specified rate for the EMV chip card. The payment terminal may transmit messages to the EMV chip card and monitor receive messages at a data connection. The payment terminal may determine that the clock rate is excessive based on a timeout of a receive message, an error rate of a receive message, or a receive message indicating that one of the transmit messages was not received by the EMV card. The payment terminal may reduce the clock rate to a rate that is below the specified rate for the EMV chip card.

Abstract: Technology that detects computation errors is disclosed, in which a system may include one or more processors and storage logic. The storage logic may be executed by the one or more processors to perform operations comprising: receiving a data vector, the data vector including a plurality of ordered blocks; transposing the data vector into a set of sub vectors, each of the sub vectors including a corresponding data element from each of the ordered blocks; generating a set of discrete cyclic redundancy checks (CRCs) based on the set of sub vectors; transposing the set of discrete CRCs into a set of mixed CRCs, each of the mixed CRCs including a CRC data element from each of the discrete CRCs; and compacting the set of mixed CRCs into a reduced CRC.

Abstract: A communication device for handling a HARQ process in a LAA SCell comprises a storage unit and a processing circuit configured to execute instructions stored in the storage unit. The instructions comprise receiving at least one UL grant from a network in a DL subframe, wherein a UL grant of the at least one UL grant schedules at least one PUSCH transmission associated with a UL HARQ process in at least one UL subframe, and a first timer and a second timer are associated with the UL HARQ process; starting the first timer in a first UL subframe of the at least one UL subframe, if the communication device is not able to perform a PUSCH transmission of the at least one PUSCH transmission in the first UL subframe; starting the second timer, when the first timer expires; and monitoring a PDCCH, when the second timer is running.

Abstract: Radio signals are received in a receiving device having an internal radio receiver that is designed to carry out a channel estimation for error correction, in the course of a receiving process of the radio signals received in a radio channel. The internal radio receiver communicates with an external radio receiver, which receives the same radio signals as the internal radio receiver at the measuring time, carries out a channel estimation for error correction, and transmits the channel estimation to the internal radio receiver, wherein the internal radio receiver uses the channel estimation of the external radio receiver in order to improve its own channel estimation.

Abstract: Performing an extract, transform, and load (ETL) process. Column data is received by a stage of the ETL process. The size of the received column data is ascertained by the stage. In response to determining that the size of the column data exceeds a predefined threshold, the stage saves the column data and creates a data locator associated with the column data. The created data locator advances through successive downstream stages of the ETL process as a replacement for the column data.

Abstract: Performing an extract, transform, and load (ETL) process. Column data is received by a stage of the ETL process. The size of the received column data is ascertained by the stage. In response to determining that the size of the column data exceeds a predefined threshold, the stage saves the column data and creates a data locator associated with the column data. The created data locator advances through successive downstream stages of the ETL process as a replacement for the column data.

Abstract: A delaying element includes a first XOR logic gate and a second XOR logic gate. A first input of the first XOR logic gate defines an input terminal. A first input of the second XOR logic gate is connected to an output of the first XOR logic gate. An output of the second XOR logic gate defines an output terminal. The second inputs of the first and second XOR logic gates are connected to a second input terminal.

Abstract: Circuits for full duplex bi-directional differential communication via a single conductor pair. A transceiver for full duplex differential communication over a single conductor pair includes a differential driver, a polarity neutral receiver, and receiver output circuitry. The differential driver is to drive the conductor pair. The polarity neutral receiver is to detect signals present on the conductor pair. The receiver output circuitry is configured to determine a logic value to be output by the transceiver as received via the conductor pair based on an output of the polarity neutral receiver and a logic value driven onto the conductor pair by the differential driver.

Abstract: A memory system according to an embodiment includes a non-volatile memory that performs multi-value recording using a plurality of pages and a controller. The controller performs bit inversion for any page of first symbols in a data string. The first symbols are a certain code sequence in the data string. The controller dispersedly allocates bits to be inverted to the plurality of pages. The controller records substitution position information indicating a position of the bit inversion in redundant data of the bit-inverted page.

Abstract: The present disclosure includes apparatuses and methods for ECC operation associated with memory. One example apparatus comprises a controller configured to perform an error correction code (ECC) operation on a codeword stored in the memory, wherein the codeword includes a first number of ECC bits and the first number of ECC bits are generated based on an encoding matrix, wherein each row of the encoding matrix has an odd number of bits having a binary value of 1.

Abstract: Method and apparatus for managing data decoder circuits, such as LDPC (low density parity check) decoders in a solid state drive (SSD). In some embodiments, a non-volatile memory (NVM) is configured to store data in the form of code words. Each code word has a user data payload and associated code bits. A plurality of data decoder circuits are configured to use the code bits to detect and correct bit errors in the code words during a read operation. A power transition circuit is configured to successively transition each of the data decoder circuits in turn from a first power mode to a second power mode, such as from an active mode to an idle mode, at a different time and at a conclusion of a predetermined time interval. In this way, voltage spikes or other anomalous conditions on a voltage source pathway may be reduced.

Abstract: According to the present disclosure, there is provided methods of processing a signal using quantized symbols. More particularly, in one example, the method comprises the steps of processing a signal (206), said method comprising the steps of: receiving a signal (206) comprising a plurality of raw symbols, each raw symbol having a plurality of bits and being conveyed in a channel; estimating a channel state information value (206) of the channel used to convey each raw symbol to generate a corresponding plurality of channel state information values; quantizing the plurality of raw symbols based on their channel state information values to generate a sequence of quantized symbols (214); and quantizing the channel state information values to generate a sequence of quantized channel state values (216).

Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, an error correction circuit and a first path selection circuit. The memory cell array includes a plurality of bank arrays. The control logic circuit controls access to the memory cell array and generates a density mode signal based on a command. The first path selection circuit selectively provides write data to the error correction circuit.

Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method.

Abstract: A method for erasure detection in a storage cluster includes establishing a connection, via a network, of a storage unit to one of a plurality of storage nodes of a storage cluster and determining, for at least one page of a storage memory of the storage unit, that the at least one page is erased. The storage unit is one of a plurality of storage units configured to store user data in memory of the storage units in accordance with direction from the plurality of storage nodes. The method includes communicating from the storage unit to the one of the plurality of storage nodes that the at least one page is erased.

Abstract: Decomposing a value range of the respective syntax elements into a sequence of n partitions with coding the components of z laying within the respective partitions separately with at least one by VLC coding and with at least one by PIPE or entropy coding is used to greatly increase the compression efficiency at a moderate coding overhead since the coding scheme used may be better adapted to the syntax element statistics. Accordingly, syntax elements are decomposed into a respective number n of source symbols si with i=1 . . . n, the respective number n of source symbols depending on as to which of a sequence of n partitions into which a value range of the respective syntax elements is sub-divided, a value z of the respective syntax elements falls into, so that a sum of values of the respective number of source symbols si yields z, and, if n>1, for all i=1 . . . n?1, the value of si corresponds to a range of the ith partition.

Abstract: [Object] To provide a new and improved information processing apparatus, information processing method, and program, capable of improving technology related to FEC for achieving low delay transfer. [Solution] Provided is an information processing apparatus including: an arrangement unit configured to arrange datagrams in a number of a predetermined matrix size or less in at least a portion of the matrix of the predetermined size, by repeating arrangement of the datagrams in order along a first direction according to a second direction; and a generation unit configured to generate a redundant datagram for forward error correction for each of the datagrams belonging to one row, and for each of the datagrams belonging to one column of the matrix arranged by the arrangement unit.

Abstract: A system that includes a multicarrier transceiver including a processor and memory. The system transmitting a packet using a forward error correction encoder and an interleaver, wherein the packet comprises a header field and a plurality of bytes, and wherein the header field comprises a sequence identifier (SID) and receiving at least one message using a forward error correction decoder and without using a deinterleaver, wherein the at least one message is received in a single DMT symbol and wherein the at least one message includes an acknowledgement (ACK) or a negative acknowledgement (NACK) of the transmitted packet. An SNR margin of the at least one message is greater than an SNR margin of the packet.

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

Abstract: An iterative decoder is controlled to iteratively decode a block by performing one or more decoding iterations for the block. The iterative decoder uses a parity-check matrix and can be configured to process that parity-check matrix for parallel, sequential or a combination of parallel and sequential (“hybrid”) parity constraint updates.

Abstract: A method and apparatus according to the present invention addresses and/or prevents lost protocol synchronization in HARQ systems caused by ACK/NACK errors. One embodiment detects lost synchronization errors for NDI-based retransmission protocols and restores synchronization by sending an explicit RESET message. In response to the RESET message, the transmitter aborts the transmission of a current PDU and transmits a new PDU and corresponding NDI. Another embodiment prevents protocol synchronization errors by sending scheduling grants on a packet by packet basis. The receiver sends a subsequent explicit scheduling grant to the transmitter based on an error evaluation of a received PDU. The transmitter will not send the next PDU unless it receives the subsequent explicit scheduling grant.

Abstract: A contents sharing method includes a step for receiving playback capability information from a client apparatus; a determination step for determining, on the basis of the received playback capability information, whether to carry out partial processing of contents to be supplied to the client apparatus; and a transmission step for processing some frames in the contents to be played in the client apparatus and transmitting the processed frames to the client apparatus if it is determined that the partial processing is to be performed. Accordingly, contents may be efficiently provided.

Abstract: The present disclosure is a method for frame acknowledgment. The method includes upon completion of downlink service data scheduling and resource allocation, allocating feedback resources in the uplink of the present physical frame; or, upon completion of the uplink service data scheduling and resource allocation, allocating feedback resources in the downlink of the next frame for sending a Group ACK response. The method further includes according to the allocated feedback resources, encapsulating the corresponding control signaling used for indicating feedback resource allocation; sending the feedback resource control signaling in a control channel of the physical frame. Also disclosed is a device for frame acknowledgement.

Abstract: Performing an extract, transform, and load (ETL) process. Column data is received by a stage of the ETL process. The size of the received column data is ascertained by the stage. In response to determining that the size of the column data exceeds a predefined threshold, the stage saves the column data and creates a data locator associated with the column data. The created data locator advances through successive downstream stages of the ETL process as a replacement for the column data.

Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.

Abstract: A method for performing polar coding is disclosed in the application. A data block is segmented into a plurality of first blocks. Difference in bit length between any two first blocks is not more than one bit. For each first block, one or more consecutive padding bits is added to obtain a second block of a bit length K if the bit length of the first block is less than K, so as to obtain a plurality of second blocks corresponding to the first blocks. N?K consecutive bits are added to each of the second blocks to obtain a plurality of third blocks. Polar encoding is performed on the third blocks.

Abstract: Systems and techniques are described for transferring data. A described technique includes receiving a request to transmit a data block from a first data storage device to a second data storage device. An attempt to read the data block from the first data storage device is made. A media error resulting from the attempt to read the data block from the first data storage device is detected. In response to detecting the media error, a new data block is generated and includes mismatched checksum data that causes a checksum mismatched error when the new data block is accessed. The new data block is transmitted for storage at the second data storage device in place of the data block.

Abstract: System and method of comparing-selecting state metric values for high speed Viterbi decoding. In an Add-Compare-Select (ACS) unit, a select control signal is produced by Boolean operations on comparator decision signals and used to control a multiplexer structure. The comparator decision signals can be generated in parallel by an array of comparators comparing all possible pairs of a set of state metrics values. The Boolean operations are predefined through Boolean algebra that uses the decision signals as variables and complies with restriction imposed by the selection criteria, e.g., to select an minimum or maximum value of the set of state metrics values. The Boolean operations are performed by a logic module implemented using basic logic gates, such as AND, OR and NOT. As a result, the multiplexer structure that receives the set of input values can output the optimum value responsive to the select control signal.

Abstract: The present disclosure dynamically selects an optimal parameter so as to stably stream an image without user's setting in a network environment. The present disclosure determines (schedules) a path to which a general packet is to be distributed based on a path cost indicator, and determines a symbol size and the number of source symbols, which minimize or sufficiently reduce a cost function.

Abstract: A semiconductor integrated circuit includes a harmonic oscillator circuit, a first switch circuit configured to cause an oscillating state of the harmonic oscillator circuit to switch between an “on” state and an “off” state, a detector circuit configured to produce a voltage responsive to an amplitude of the oscillating output of the harmonic oscillator circuit, a decision circuit configured to detect whether the voltage produced by the detector circuit exceeds a threshold in synchronization with a clock signal, and a second switch circuit configured to control whether or not to apply noise from a noise source to the harmonic oscillator circuit.

Abstract: A storage system includes a channel detector, an LDPC decoder, and an erasure block. The channel detector is configured to receive data corresponding to data read from a storage and output an LLR signal. The LDPC decoder is configured to receive the LLR signal and output a feedback signal to the channel detector. The erasure block is configured to erase at a portion of at least one of the LLR signal and the feedback signal. A method for testing includes generating an error rate function corresponding to an erasure pattern. The function is a function of a number of LDPC iterations. The method includes determining testing parameters at least in part based on the error rate function, wherein the testing parameters comprise a testing number of LDPC iterations, a passing error rate, and the erasure pattern. The method includes testing storage devices using the testing parameters.

Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method.

Abstract: A system and method for multiband rate scaling for communication, particularly wireless communication. A band is used as a parameter for wireless communication performance when a wireless communication channel has a plurality of available bands for communication. A selected communication band may be switched to another available communication band, where the switching may be based on a desired performance determination.

Abstract: An apparatus and associated methodology providing read channel circuitry having a signal equalizer that sends an equalized signal to a bit detector. The read channel circuitry is capable of sampling values of the equalized signal to identify a bit transition from among a predefined plurality of different bit transitions. The apparatus may have channel optimization (CO) logic that, based on the input signal and the sampling of the equalized signal, defines first values for a programmable parameter of the bit detector that substantially maximizes vector separations among vectors of waveform target samples corresponding to the predefined plurality of different bit transitions, while the CO logic also defines second values for a programmable parameter of the equalizer that substantially minimizes the mean squared separation of the equalized signal segment for each bit transition from the waveform target corresponding to that bit transition.

Abstract: A default read operation is performed on a page using a default read voltage set to generate default raw data. If error bits of the default raw data are not corrected, a plurality of low-level read operations is performed on the page using a plurality of read voltage sets to generate a plurality of low-level raw data. Each read voltage set is different from the default voltage set. A read voltage set is selected from the plurality of read voltage sets as a starting voltage set, according to each low-level raw data. A high-level read operation using the selected starting voltage set is performed on the page to generate high-level raw data.

Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method.

Abstract: The method includes generating, by one or more computer processors, a first piece of data based on a defined set of data characteristics. The method further includes generating a first bit, wherein the first bit corresponds to the first generated piece of data. The method further includes sending the first generated piece of data to a target location. The method further includes receiving the first generated piece of data from the target location. The method further includes determining whether to validate the first generated piece of data received from the target location. The method further includes adjusting the first generated bit based on the determination of whether to validate the first generated piece of data.

Abstract: A method of decoding data of a non-volatile memory device is provided. The method includes a first decoding operation of reading first hard decision data from the non-volatile memory device using a first hard decision read level and performing decoding using the first hard decision data; a second decoding operation of reading first soft decision data from the non-volatile memory device when the decoding fails in the first decoding operation, and performing decoding using the first soft decision; and a third decoding operation of changing from the first hard decision read level to a second hard decision read level when the decoding fails in the second decoding operation, reading second hard decision data using the second hard decision read level, and performing decoding either using the second hard decision data or using both the second hard decision data and the first soft decision data.

Abstract: Systems and methods for correcting errors in a depth map generated by a structured light system are disclosed. In one aspect, a method includes receiving valid and invalid codewords, the valid spatial codewords included in a codebook. The method includes detecting the invalid codeword. The method includes retrieving a set of candidate valid codewords a lowest Hamming distance between the invalid codeword and the valid codewords in the codebook. The method includes estimating a median depth of neighboring locations of the invalid codeword. The method includes associating a depth with each candidate codeword and selecting the candidate with an associated depth closest to the depth estimate. The method includes assigning the depth associated with the selected candidate codeword to the location of the invalid codeword.

Abstract: A method and apparatus for encoding data and for decoding data using LDPC (low density parity check) codes includes providing a mother LDPC matrix of a particular size. A data payload of a smaller size is encoded by shortening the mother matrix to a smaller daughter matrix corresponding in size to the data payload and using the smaller daughter matrix for the encoding. The portions of the mother matrix to be removed in the shortening are derived from a control signal. The encoded data is transmitted with the control signal so that the receiver can derive the portions of the mother matrix to be removed to obtain the daughter matrix. At the receiver, a mother matrix is shortened to a daughter matrix and is then used to decode the data. The data at the encoder may be further reduced by puncturing to remove selected information bits and selected parity bits. The decoder inserts the selected information bits and parity bits when decoding the data.

Abstract: The invention relates to devices and methods for signalling control information associated with transmission of data over a wireless channel. A second communication device receives (S2) data from a first communication device, wherein the data comprises an indication of recommended precoders and a recommendation of a first transmission rank to possibly use during transmission. The second communication device determines (S4) a second transmission rank to use for transmitting data, and transmits (S6) a confirmation message to the first communication device. The confirmation message comprises a confirmation that transmission of data from the second communication device is using at least parts of each recommended precoder associated with a frequency resource that falls within the transmission of data and an indicator of the second transmission rank to use.

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Abstract: A display device includes a source driver integrated circuit (IC) including an equalizer for boosting a data signal received through a pair of signal lines depending on an equalization (EQ) setting value and a clock recovery circuit recovering a clock of the data signal, and a timing controller, which is connected to the source driver IC through the signal line pair and transmits the data signal to the source driver IC. The source driver IC samples the data signal in conformity with a timing of an internal clock output when the clock recovery circuit is in a lock state. The source driver IC further includes an equalizer control circuit for initializing the equalizer when the clock recovery circuit is in an unlock state and the EQ setting value is changed.

Abstract: An operating method of a non-volatile memory device having a string including a plurality of memory cells and a plurality of auxiliary cells, the plurality of memory cells and the plurality of auxiliary cells being connected in series, includes detecting a threshold voltage of at least one of the plurality of auxiliary cells and generating an output signal corresponding to a deterioration level of the plurality of memory cells, based on the threshold voltage.

Abstract: In a method and system for offline content playback, a first plurality of portions of content streamed from a content sharing service for presentation by a media player is received. A request from a user to make the content available for offline playback is received, and in response to the request, a second plurality of portions of the content streamed from the content sharing service for presentation by the media player is stored. The first plurality of portions is requested and received from the content sharing service. The received first plurality of portions is stored, such that the first plurality of portions and the second plurality of portions are available for offline playback.

Abstract: An image-capturing device includes: an image-capturing unit that captures an image of a photographic subject; a selection unit that selects, as a reference image, a single image from among a plurality of images that have been captured in succession by the image-capturing unit; a calculation unit that calculates an amount of positional deviation between the reference image and each of the plurality of images other than the reference image; and a generation unit that generates a combined image by positionally aligning and then combining the reference image and those ones of the plurality of images whose amounts of positional deviation are less than or equal to a predetermined amount of deviation. The selection unit selects the reference image so that the number of images for which the amount of positional deviation is less than or equal to the predetermined amount of deviation becomes large.