Abstract: A technique for improving performance of a cache is provided. The technique involves maintaining indicators of whether cache entries are dirty in a random access memory (“RAM”) that has a lower latency to a cache controller than the cache memory that stores the cache entries. When a request to invalidate one or more cache entries is received by the cache controller, the cache controller checks the RAM to determine whether any cache entries are dirty and thus should be written out to a backing store. Using the RAM removes the need to check the actual cache memory for whether cache entries are dirty, which reduces the latency associated with performing such checks and thus with performing cache invalidations.

Abstract: Methods (C) for converting a data signal (U). The methods may comprise (i) providing an input symbol stream (IB) of input symbols (Bj), the input symbol stream (IB) being representative for the data signal (U) to be converted and (ii) applying to consecutive disjunct partial input symbol sequences (IBp) of a number of p consecutive input symbols (IBj) covering said input symbol stream (IB), a distribution matching process (DM) to generate and output a final output symbol stream (OB) or a preform thereof, wherein the distribution matching process (DM) may be formed by a preceding shell mapping process (SM) and a succeeding amplitude mapping process (AM), wherein said shell mapping process (SM) may be configured to form and output to said amplitude mapping process (AM) for each of said consecutive partial input symbol sequences (IBp) a sequence (sq) of a number of q shell indices (s), and wherein said amplitude mapping process (AM) may be configured to assign to each shell index (s) a tuple of amplitude values.

Abstract: A method for encoding a packet in a broadcasting system supporting an Internet Protocol (IP)-based multimedia service is provided. The method includes dividing a data stream into data payloads, generating a Motion Picture Expert Group (MPEG) Media Transport (MMT) packet by adding a first header to each of the data payloads, and generating a source packet by adding an MMT packet header to the MMT packet and performing Forward Error Correction (FEC) encoding on the header-added MMT packet. The MMT packet header includes type information of the MMT packet.

Abstract: A memory system may include: a memory device including a plurality of memory blocks each having a plurality of pages; and a controller suitable for controlling the memory device to perform program operations in the pages, the memory device may check program voltage distributions of the programmed pages, and may check fail bits in the programmed pages, and the controller may confirm a partial program success in the program operations, and may perform a copy operation for first data corresponding to the partial program success, in the memory blocks.

Abstract: One embodiment provides a technique of adjusting a gate voltage to be applied to at least one MOS capacitor and an amount of electric charge to be stored in the MOS capacitor so as to determine sensitivity of a change in the amount of electric charge stored in the MOS capacitor, and exposing the MOS capacitor to an electric field for a predetermined amount of time and then reading an electron inflow or outflow result due to the electric field so as to interpret the intensity and the direction of the electric field, thereby measuring the intensity and the direction of the electric field.

Abstract: An information transmission method for reducing Peak to Average Power Ratio (PAPR), a transmitting terminal and a receiving terminal are provided, to solve the technical problem that it is difficult for a transmitting terminal to reliably transmit side information to a receiving terminal by using conventional methods for reducing PAPR. The method includes: scrambling an initial data block according to a predetermined scrambling mode to obtain a scrambled target data block; determining a scrambling mode index corresponding to the predetermined scrambling mode according to a predetermined relation between scrambling mode indexes and scrambling modes; generating side information carrying the determined scrambling mode index based on the scrambling mode index; and transmitting the side information and the target data block to a receiving terminal.

Abstract: In general, data is susceptible to errors caused by faults in hardware (i.e. permanent faults), such as faults in the functioning of memory and/or communication channels. To detect errors in data caused by hardware faults, the error correcting code (ECC) was introduced, which essentially provides a sort of redundancy to the data that can be used to validate that the data is free from errors caused by hardware faults. In some cases, the ECC can also be used to correct errors in the data caused by hardware faults. However, the ECC itself is also susceptible to errors, including specifically errors caused by faults in the ECC logic. A method, computer readable medium, and system are thus provided for securing against errors in an ECC.

Abstract: One embodiment provides a wireless microphone comprising a microphone body a plurality of antennas positioned at different locations of the microphone body. Each of the plurality of antennas is configured to wirelessly transmit data. The wireless microphone further comprises a sensor configured to detect an object within proximity of an antenna of the plurality of antennas that obstructs the antenna, and a controller configured to switch antenna operation of the wireless microphone from the antenna to another antenna of the plurality of antennas in response to the object detected.

Abstract: Fault detection for real-time visual-inertial odometry motion tracking. A fault detection system allows immediate detection of error when the motion of a device cannot be accurately determined. The system includes subdetectors that operate independently and in parallel to a main system on a device to determine if a condition exists which results in a main system error. Each subdetector covers a phase of a six-degrees of freedom (6DOF) estimation. If any of the subdetectors detect an error, a fault is output to the main system to indicate a motion tracking failure.

Abstract: Repairing missing frames in a video includes obtaining video data from an image capture system, applying a first neural network model to the video data to detect that one or more frames are missing, where the first neural network model has been trained to detect missing frames based on training data in which an artificial gap has been introduced. In response to detecting that the one or more frames are missing, a second model is applied to the video data to generate one or more replacement frames. The one or more replacement frames are based on at least a first frame prior to the detected dropped one or more frames, and a second frame after the detected dropped one or more frames. Modified video data is generated using the plurality of frames and the replacement frames.

Abstract: In a general aspect, quantum computing system performance is tested. Systems and methods for testing hardware in a quantum computing system are described. The methods may include certification/decertification of data produced by the quantum computing system, detection of faults, correction of errors and/or recalibration/replacement of the quantum computing system or a quantum computing subsystem.

Abstract: A method for generating a data directory can include allocating a first page for storing a first segment of a log recording changes applied to data subsequent to a checkpoint. When the first page reaches maximum capacity, a second page can be allocated for storing a second segment of the log. A third page can be allocated for storing a first page list that includes a first page reference to the second data page. A fourth page serving as a restart page can be updated. The fourth page can store a second page list of data pages storing the data directory. The fourth page can be updated to add, to the second page list, a second page reference to the data page. Crash recovery at the computing node can be performed based on the data directory. Related systems and articles of manufacture are also provided.

Abstract: Systems and methods for improving isolation between a cosite transmitter-receiver system. The transmitter may send a first plurality of transmit signals from multiple transmit ports. The first plurality of transmit signals may be related to one another by a first set of complex weights. The receiver may detect channel-impaired versions of the first plurality of transmit signals at one or more receive ports. The receiver may analyze channel-impaired versions of the first plurality of transmit signals to estimate channel state information. The transmitter may use the channel state information to determine a second set of complex weights which will reduce the power received at one or more ports of the receiver when applied to a second plurality of transmit signals. The second set of complex weights may vary with frequency.

Abstract: A failover method, apparatus and system to implement fast failover between a primary processor and a secondary processor, where the method includes receiving, by a first device, transaction content of a transaction and transaction status data of the transaction, the transaction status data being used to resume the transaction when the transaction is interrupted by a failure of a second device, and continuing to process, by the first device, the transaction according to the transaction content and the transaction status data when detecting that the second device fails.

Abstract: Provided is a method of transmitting and receiving data by a user equipment (UE), the method including receiving, by the UE, a first data stream including at least one of transmission data and a first error correction code regarding the transmission data, obtaining a second error correction code based on the transmission data obtained from the received first data stream, and transmitting a second data stream including at least one of recovered transmission data and the obtained second error correction code.

Abstract: A method for iteratively decoding read bits in a solid state storage device. The read bits are encoded with a Q-ary LDPC code defined over a binary-extension Galois field GF(2r) and having length N. The method comprises determining a binary Tanner graph of the Q-ary LDPC code based on a Q-ary Tanner graph of the Q-ary LDPC code, and based on a binary coset representation of the Galois field GF(2r).

Abstract: When a base station has reason to increase the extent of MU-MIMO service that it can provide or in other contexts, the base station could select at least one of the base station's served UEs to have its MIMO rank reduced, with the selecting being based at least on a determination that the selected UE has had a threshold high rate of data retransmissions such as a threshold high rate of HARQ retransmissions for instance.

Abstract: Techniques are described for wireless communication. One method includes receiving, at a user equipment (UE), a transport block (TB) that includes a plurality of code block groups (CBGs); determining CBG failure information identifying a set of one or more CBGs in the TB that failed to decode at the UE; determining a compressed representation of the CBG failure information; and transmitting, in response to receiving the TB, hybrid automatic repeat request (HARQ) information including the compressed representation of the CBG failure information. The compressed representation of the CBG failure information includes fewer bits of information than the CBG failure information.

Abstract: A terminal apparatus includes a coding unit configured to divide a transport block into one or more code blocks and generate coded bit(s) by coding the one or more code blocks; and a transmitter configured to transmit the coded bit(s) by using a channel, wherein multiplex bit(s) are given based on at least coupling of the coded bit(s) generated by coding of the one or more code blocks, the coding unit maps the multiplex bit(s) to a matrix in a first-axis prioritized manner and reads the multiplex bit(s) from the matrix in the first-axis prioritized manner or in a second-axis prioritized manner, and whether the first axis or the second axis is prioritized in a case that the multiplex bit(s) are read from the matrix is given based on at least whether a signal waveform applied to a prescribed channel is an OFDM.

Abstract: A non-volatile memory device driving method, applicable to a non-volatile memory device comprising a row decoder and a memory array, comprises: utilizing the row decoder to transmit multiple word line signals to multiple word lines of the memory array; according to an address, utilizing the row decoder to switch a selected word line signal of the multiple word line signals from a predetermined voltage level to a program voltage level; utilizing the row decoder to switch at least one support word line signal of the multiple word line signals from the predetermined voltage level to a first pass voltage level; when the selected word line signal is remained at the program voltage level, utilizing the row decoder to switch the at least one support word line signal from the first pass voltage level to a higher second pass voltage level.

Abstract: This application discloses a computing system configured to identify a channel in an electronic device is configured to transmit signals encoding data with more than two value levels in response to a correlated test input. The computing system can determine probabilities of value level changes in the transmitted signals based on an encoding for the correlated test input, and measure a step response of the channel. The computing system can perform statistical simulation or analysis on the channel based, at least in part, on the step response of the channel and the determined probabilities of value level changes in the transmitted signals, which can predict a signal integrity of the channel configured to transmit the signals based, at least in part, on the determined probabilities of value level changes in the transmitted signals.

Abstract: This application discloses a computing system configured to identify that a test input for a channel in an electronic device conforms to protocol having a correlated bit pattern. The computing system can determine transition probabilities for bits in the test input based on the protocol having the correlated bit pattern, and measure a step response of the channel. The computing system can perform statistical simulation or analysis on the channel based, at least in part, on the step response of the channel and the transition probabilities for bits in the test input, which can predict a signal integrity of the channel. The computing system can generate an eye diagram or a develop a bit error rate corresponding to the signal integrity of the channel.

Abstract: Certain aspects of the present disclosure relate to jumbo MSDU delivery. Certain aspects of the present disclosure provide an apparatus for wireless communications. The apparatus includes at least one processing system configured to split a first media access control (MAC) service data unit (MSDU) into a first plurality of MAC protocol data units (MPDUs), each having a unique MPDU sequence number and a separate MSDU sequence number associated with the first MSDU, and a first interface configured to output the first plurality of MPDUs for transmission to a recipient.

Abstract: Implementations of encoding techniques are disclosed. The encoding technique, such as a Data bus Inversion (DBI) technique, is implementable in a vertically-stacked memory module, but is not limited thereto. The module can be a plurality of memory integrated circuits which are vertically stacked, and which communicate via a bus formed in one embodiment of channels comprising Through-Wafer Interconnects (TWIs), but again is not limited thereto. One such module includes spare channels that are normally used to reroute a data signal on the bus away from faulty data channels. In one disclosed technique, the status of a spare channel or channels is queried, and if one or more are unused, they can be used to carry a DBI bit, thus allowing at least a portion of the bus to be assessed in accordance with a DBI algorithm. Depending on the location and number of spare channels needed for rerouting, DBI can be apportioned across the bus in various manners.

Abstract: An exemplary system, method and computer-accessible medium for removing noise and Gibbs ringing from a magnetic resonance (“MR”) image(s), can be provided, which can include, for example, receiving information related to the MR image(s), receiving information related to the MR image(s), and removing the Gibbs ringing from the information by extrapolating data in a k-space from the MR image(s) beyond an edge(s) of a measured portion of the k-space. The data can be extrapolated by formatting the data as a regularized minimization problem(s). A first weighted term of the regularized minimization problem(s) can preserve a fidelity of the extrapolated data, and a second weighted term of the regularized minimization problem(s) can be a penalty term that can be based a norm(s) of the MR image(s), which can be presumed to be sparse.

Abstract: A relay device may include a plurality of communication circuits and a state control portion. The relay device may relay the data among a plurality of buses, each of which connecting one or more nodes. The plurality of communication circuits may perform transmission and reception of the data, and transition among a plurality of states including a transmission enabled state and a transmission disabled state. The plurality of communication circuits may be connected to the plurality of buses in one to one manner. The state control portion may cause a specific communication circuit to transition from the transmission enabled state to the transmission disabled state when a relay transition time has elapsed from an occurrence of predetermined event. The specific communication circuit may represent at least one of the plurality of communication circuits to which at least one of the plurality of buses connecting the specific node is connected.

Abstract: An apparatus includes an encoder circuit block configured to receive input data. The encoder circuit block is configured to generate a plurality of parity bits from the input data and order the input data and the plurality of parity bits to generate encoded data. The encoder circuit block is configured to generate each of the plurality of parity bits based upon selected bits of the input data and orders the input data and the plurality of parity bits so that a decoder circuit block configured to decode the encoded data is able to perform operations including, at least in part, detecting a no bit error, detecting and correcting a single bit error, detecting a double bit error, detecting and correcting an adjacent double bit error, and detecting an adjacent triple bit error. The operations are independent of a number of memory banks used to store the encoded data. The decoder circuit block may also correct an adjacent triple bit error.

Abstract: Methods, systems and computer program products for root cause analysis using provenance data are provided herein. A computer-implemented method comprises computing a plurality of provenance paths for at least one of a plurality of data elements in a curation flow and a plurality of groups of data elements in the curation flow, analyzing the computed provenance paths to determine one or more errors in the curation flow, and outputting the one or more errors in the curation flow to at least one user. The analyzing comprises at least one of identifying which of the computed provenance paths are partial provenance paths, and identifying one or more output records associated with the curation flow, wherein the one or more output records comprise incorrectly curated data, and identifying the computed provenance paths that respectively correspond to the one or more output records comprising the incorrectly curated data.

Abstract: A method of determining locations for social media postings may include: retrieving, by communicating with at least one application programming interface (API) of a social media system over one or more first communication networks, at least one social media posting; determining at least one location mention in the at least one social media posting; determining at least one location based on the at least one location mention; determining a primary location from the at least one location; storing, in at least one database on a non-transitory machine-readable storage medium, at least one set of geo-coordinates for the primary location in at least one posting object for the at least one social media posting; and outputting, by communicating with a user system over one or more second communication networks, the at least one social media posting with the stored at least one set of geo-coordinates for display on the user system.

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Abstract: Example implementations described herein are directed to detection of historical anomalous events that are similar to currently occurring events in a transmission power system based on phasor management unit (PMU) data to provide information to grid operators with online decision support. From the high-resolution time synchronized PMU data, the historical events can be quickly retrieved and compared to the currently occurring event so that operators can be provided with remedy actions that were attempted in response to the historical events. Utilization of PMU information for such decision support may compliment operation practices relying on supervisory control and data acquisition (SCADA) measurements by allowing a much fast response to the currently occurring event. Accurate identification of similar, historical events can advise grid operators of the cause of disturbances and provide ideas for response.

Abstract: A data correction filter includes an equalizer circuit, first, second, and third asynchronous comparators, an error amplifier, a multiplexer, a delay circuit, first and second exclusive-OR gates, and first and second integrator circuits. The first asynchronous comparator is coupled to the equalizer circuit. The second and third asynchronous comparators are coupled to the equalizer circuit and the error amplifier. The multiplexer is coupled to the first, second, and third asynchronous comparators. The delay circuit is coupled to the first asynchronous comparator. The first exclusive-OR gate is coupled to the delay circuit and the multiplexer. The second exclusive-OR gate is coupled to the first asynchronous comparator and the multiplexer. The first integrator circuit is coupled to first exclusive-OR gate and the equalizer circuit. The second integrator circuit is coupled to the second exclusive-OR gate and the error amplifier.

Abstract: Devices and techniques for correcting for power loss in NAND memory devices are disclosed herein. The NAND memory devices may comprise a number of physical pages. For example, a memory controller may detect a power loss indicator at the NAND flash memory. The memory controller may identify a last-written physical page and determine whether the last-written physical page comprises more than a threshold number of low-read-margin cells. If the last-written physical page comprises more than the threshold number of low-read-margin cells, the memory controller may provide a programming voltage to at least the low-read-margin cells.

Abstract: A first controller in a distributed network obtains, concurrently with a second controller in the distributed network, a system requirement and a message from a logical bus. The first controller and the second controller are communicatively coupled to the logical bus, and the first controller is communicatively coupled to a first portion of the network components and the second controller is communicatively coupled to a second portion. A processor associated with the first controller solves, concurrently with the second controller, the system requirement and the solving includes applying a solver to generate new configurations of the network components. The new configurations generated by the first controller are identical to the new configurations generated by the second controller. The first controller extracts configurations relevant to the first portion of the network components and applies the configurations to the first portion of the network components.

Abstract: A method of producing a set of coded bits from a set of information bits for transmission between a first node (110, 115) and a second node (110, 115) in a wireless communications system (100), the method comprises generating (904) a codeword vector by encoding the set of information bits with a low-density parity-check code, wherein the codeword vector is composed of systematic bits and parity bits. The method comprises performing (908) circular buffer-based rate matching on the generated codeword vector to produce the coded bits for transmission, wherein the circular buffer-based rate matching comprises puncturing a first plurality of systematic bits.

Abstract: A method and system for packet retransmission that includes transmitting or receiving, by a transceiver, a plurality of packets. Next, a determination is made for a memory allocation between a retransmission function and one or more of an interleaving and a deinterleaving function, wherein the memory allocation is based on at least one communication parameter. Then, an identification of at least one packet of the plurality of packets as a packet that should not be retransmitted is performed.

Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.

Abstract: A decoding method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: when first data is read from a first upper physical programming unit of a first physical programming unit group by using a second voltage selected from a first read voltage group, and a first error bit count of the first data is not greater than a first error bit count threshold, recording the second voltage; when a second data is read from a first lower physical programming unit of a second physical programming unit group by using a fourth voltage selected from a second read voltage group, and a second error bit count of the second data is not greater than a second error bit count threshold, recording the fourth voltage; generating a lookup table according to the second voltage and the fourth voltage; and performing a decoding operation according to the lookup table.

Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method.

Abstract: Techniques are described for joint encoding and decoding of information symbols. In one embodiment, a method for joint encoding includes, in part, obtaining a sequence of information symbols, generating a plurality of cyclic codewords each corresponding to a portion of the sequence of information symbols, jointly encoding the plurality of cyclic codewords to generate at least one combined codeword, and providing the combined codeword to a device. The at least one combined codeword may be generated through Galois Fourier Transform (GFT).

Abstract: Disclosed herein are example embodiments of protocols to distill magic states for T-gates. Particular examples have low space overhead and use an asymptotically optimal number of input magic states to achieve a given target error. The space overhead, defined as the ratio between the physical qubits to the number of output magic states, is asymptotically constant, while both the number of input magic states used per output state and the T-gate depth of the circuit scale linearly in the logarithm of the target error. Unlike other distillation protocols, examples of the disclosed protocol achieve this performance without concatenation and the input magic states are injected at various steps in the circuit rather than all at the start of the circuit. Embodiments of the protocol can be modified to distill magic states for other gates at the third level of the Clifford hierarchy, with the same asymptotic performance.

Abstract: There is disclosed in an example, a processor, having: decode circuitry to decode instructions from an instruction stream; a data cache unit including circuitry to cache data for the processor; and a compute unit having an approximate matrix multiplication (AMM) circuit comprising: a data receptor to receive a weight vector w and an input vector x, both of size N, and a compression regulating parameter n; and a factorizor circuit to factorize w into w?B·s, by computing a binary factorized matrix B of size N×n, and a dictionary vector s of size n. In an example, the factorization follows a dual minimization procedure, the time complexity of which is on average linear with N.

Abstract: A decoder includes multiple variable-node circuits and logic circuitry. The variable-node circuits hold variables of an Error Correction Code (ECC), defined by a set of check equations over multiple variables corresponding to the variable-node circuits. The logic circuitry is configured to receive a code word encoded using the ECC, to hold, prior to decoding in a sequence of iterations, a scheduling scheme that specifies, for each iteration, whether each of the variable-node circuits is to be processed or skipped in that iteration, to perform the iterations in the sequence, including selecting for processing, in each iteration, only variable-node circuits specified for processing in that iteration, to determine for each selected variable-node circuit, a count of unsatisfied check equations in which the respective variable participates, and to make a decision on flipping a binary value of the variable based on the count and apply the decision by the respective variable-node circuit.

Abstract: Methods for use in identifying optimal storage units for storage of data in a dispersed storage network (DSN) having geographically distributed storage units. In operation, a data object to be stored is received by a computing device functioning. When selecting from multiple sets of storage units servicing multiple geographic regions for placement of the data, the computing device biases its decision based on additional properties of the storage request or of the requestor. In one example, the primary or “home” location of the requestor is determined from metadata received from an authentication authority. Alternatively, the home location information may be derived from a store data request received from the requestor. Following a determination that the originating location of the storage request differs from the home location, the computing device selects storage units in relatively closer proximity to the home location as compared to a current location of the requestor.

Abstract: Duplicate bug report detection using machine learning algorithms and automated feedback incorporation is disclosed. For each set of bug reports, a user-classification of the set of bug reports as including duplicate bug reports or non-duplicate bug reports is identified. Also for each set of bug reports, correlation values corresponding to a respective feature, of a plurality of features, between bug reports in the set of bug reports is identified. Based on the user-classifications and the correlation values, a model is generated to identify any set of bug reports as including duplicate bug reports or non-duplicate bug reports. The model is applied to classify a particular bug report and a candidate bug report as duplicate bug reports or non-duplicate bug reports.

Abstract: In a general aspect, randomized compiling techniques for quantum computing are described. In some aspects, an initial quantum-logic gate sequence is received. A modified quantum-logic gate sequence is generated by applying virtual random gates to the initial quantum-logic gate sequence, such that the initial quantum-logic gate sequence is logically equivalent to the modified quantum-logic gate sequence. The modified quantum-logic gate sequence can be provided to a quantum information processor for execution.

Abstract: Duplicate bug report detection using machine learning algorithms and automated feedback incorporation is disclosed. For each set of bug reports, a user-classification of the set of bug reports as including duplicate bug reports or non-duplicate bug reports is identified. Also for each set of bug reports, correlation values corresponding to a respective feature, of a plurality of features, between bug reports in the set of bug reports is identified. Based on the user-classifications and the correlation values, a model is generated to identify any set of bug reports as including duplicate bug reports or non-duplicate bug reports. The model is applied to classify a particular bug report and a candidate bug report as duplicate bug reports or non-duplicate bug reports.

Abstract: An exit pattern is sent to initiate exit from a partial width state, where only a portion of the available lanes of a link are used to transmit data and the remaining lanes are idle. The exit pattern is sent on the idle lanes, the exit pattern including an electrical ordered set (EOS), one or more fast training sequences (FTS), a start of data sequence (SDS), and a partial fast training sequence (FTSp). The SDS includes a byte number field to indicate a number of a bytes measured from a previous control interval of the link, and an end of the SDS is sent to coincide with a clean flit boundary on the active lanes. The partial width state is exited based on the exit pattern and data is sent on all available lanes following the exit from the partial width state.

Abstract: A request is received to access physical information of a memory unit included in a memory device. A determination is made whether the physical information is available in a physical information table present in a memory cache. If the physical information of the memory unit is available in the table, the physical information is accessed from the table. If the physical information is not available in the table, a global directory in the memory cache is accessed, which indicates locations in a non-volatile memory that store the total number of the physical information blocks. From the global directory, a particular location in the non-volatile memory storing a particular physical information block that includes the physical information of the memory unit is determined. The particular physical information block is loaded into the table and the physical information of the memory unit is accessed from the particular physical information block.

Abstract: Methods and apparatus deduplicate and erasure code a message in a data storage system. One example apparatus includes a first chunking circuit that generates a set of data chunks from a message, an outer precoding circuit that generates a set of precoded data chunks and a set of parity symbols from the set of data chunks, a second chunking circuit that generates a set of chunked parity symbols from the set of parity symbols, a deduplication circuit that generates a set of deduplicated data chunks by deduplicating the set of precoded chunks or the set of chunked parity symbols, an unequal error protection (UEP) circuit that generates an encoded message from the set of deduplicated data chunks, and a storage circuit that controls the data storage system to store the set of deduplicated data chunks, the set of parity symbols, or the encoded message.