Abstract: A controller communicates with a plurality of multi-chip memory packages. Each multi-chip memory package comprises a plurality of memory dies, each having a respective plurality of memory blocks, some of which are good and some of which are bad. The controller determines a number of good blocks in each memory die. Based on the determined number of good blocks in each memory die, the controller selects a memory die from each of the multi-chip memory packages to access in parallel, wherein the selected memory dies are not necessarily all in the same relative position in each multi-chip package. The controller then creates a metablock from a set of good blocks from each of the selected memory dies, wherein a maximum number of metablocks that can be created across the selected memory dies is determined by a lowest number of good blocks in the selected memory dies.

Abstract: A method includes, in a decoder of an Error Correction Code (ECC), maintaining only aggregated information regarding a set of messages, a function of which is to be reported from a first node to a second node of the decoder. The function of the set is determined and reported using the aggregated information. After reporting the function, one of the messages in the set is replaced with a new message. The aggregated information is updated to reflect the set having the new message, and the function of the set having the new message is determined and reported using the updated aggregated information.

Abstract: Each of (n?1) 2-bit checking units, where n is an integer larger than or equal to 4, receives n-bit redundant encoded data generated from 1-bit input data, and outputs 2-bit check data based on a result of comparison between bits of the encoded data, combinations of the bits differing in each comparison. An all-bit checking unit outputs all-bit check data based on exclusive ORs of all-bit of the encoded data. An error detecting unit detects errors in the encoded data on the basis of the (n?1) sets of 2-bit check data and the all-bit check data, and outputs the input data on the basis of the result of error detection.

Abstract: Systems, devices, processors, and methods are described which may be used for the reception of a wireless broadband signal at a user terminal from a gateway via satellite. A physical layer header may be identified, the header including a number of subcode blocks. A phase may be estimated for each of the subcode blocks, and intra-header phase differences may be calculated. The intra-header phase differences may be used to calculate a frequency error, which may be corrected. Frequency errors may be monitored and, when such errors fall below a threshold level, an alternative inter-frame frequency error tracking method may be used.

Abstract: A hybrid drive is disclosed comprising a head actuated over a disk, and a non-volatile semiconductor memory (NVSM). A write command is received from a host, the write command comprising data. First and second error correction code (ECC) symbols are generated over the data, wherein the second ECC symbols are different than the first ECC symbols. The data and first ECC symbols are written to the NVSM, and the second ECC symbols are written to the disk.

Abstract: A method begins by a processing module dispersed storage error encoding secret data in accordance with first dispersed storage error encoding parameters to produce at least one set of encoded secret slices and dispersed storage error encoding data in accordance with second dispersed storage error encoding parameters to produce a plurality of sets of encoded data slices. The method continues with the processing module determining an inter-dispersing function for outputting the sets of encoded secret slices and the plurality of sets of encoded data slices, and for a set of the plurality of encoded data slices: identifying at least one encoded data slice of the set of encoded data slices based on the inter-dispersing function, replacing the at least one encoded data slice with at least one encoded secret slice to produce a mixed set of encoded slices, and outputting the mixed set of encoded slices.

Abstract: One aspect of the present invention concerns the management of processing resource allocations for a Turbo receiver, where such resources are consumed from a finite resource budget within a defined processing time interval. The contemplated Turbo receiver attempts to allocate more processing resources to those demodulation and/or Turbo decoding tasks that make more valuable contributions with respect to the ultimate goal of successfully decoding all data streams that are of interest in a received signal. The advantageous management approach allows the Turbo receiver to obtain better results for a given consumption of processing resources, and further permits the Turbo receiver to quit upon either achieving a successful outcome within a defined processing time interval or exhausting the budgeted resources.

Abstract: Devices, systems, methods, and other embodiments associated with generating a moving average are described. In one embodiment, a method calculates, using at least an accumulator, an average value of M sequential data values is calculated, where M is an integer. The M sequential data values are delayed before passing a delay output. The method detects a data value with an error in the M sequential data values that are delayed and controls the accumulator to correct the average value of the M sequential data values as a function of the error.

Abstract: A method includes receiving a signal, which carries data that is encoded with an Error Correction Code (ECC), and correcting the received signal with an adaptive receiver loop. Soft input metrics for the data are computed over the corrected signal. The ECC is decoded using a decoder, which estimates soft output metrics based on the soft input metrics, by operating the decoder in an alternating pattern of external iterations that update one or more of the soft input metrics based on one or more of the soft output metrics, and internal iterations that update the soft output metrics but not the soft input metrics. The adaptive receiver loop is adjusted in a schedule that is defined relative to the pattern of the external and the internal iterations of the decoder.

Abstract: An electronic circuit (200) for use with an accessing circuit (110) that supplies a given address and a partial write data portion and also has dummy cycles. The electronic circuit (200) includes a memory circuit (230) accessible at addresses, an address buffer (410), a data buffer (440) coupled to the memory circuit (230), and a control circuit (246) operable in the dummy cycles to read data from the memory circuit (230) to the data buffer (440) from a next address location in the memory circuit (230) and to store that next address in the address buffer (410).

Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) read data from a region of a memory circuit during a read scrub of the region and (ii) generate a plurality of statistics based on (a) the data and (b) one or more bit flips performed during an error correction of the data. The memory circuit is generally configured to store the data in a nonvolatile condition. One or more reference voltages may be used to read the data. The second circuit may be configured to (i) update a plurality of parameters of the region based on the statistics and (ii) compute updated values of the reference voltages based on the parameters.

Abstract: Provided is a method of performing hybrid automatic repeat request (HARQ) of a receiver in a wireless communication system. The method includes: receiving data in a transmission time interval (TTI) unit consisting of a plurality of consecutive subframes; and transmitting acknowledgment (ACK)/non-acknowledgment (NACK) for the received data, wherein the data is received using a plurality of redundancy versions respectively allocated to the plurality of subframes, and the ACK/NACK is transmitted with an interval of a predetermined processing delay from a transmission time of a specific redundancy version among the plurality of redundancy versions.

Abstract: Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D2) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. A 1/(1+D) precoder may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.

Abstract: A digital broadcasting system and a method of processing data are disclosed, which are robust to error when mobile service data are transmitted. To this end, additional encoding is performed for the mobile service data, whereby it is possible to strongly cope with fast channel change while giving robustness to the mobile service data.

Abstract: According to some embodiments, a message generated by a downstream device is received at upstream device. The message may, for example, be received via a peripheral interface and may not require a response. It may then be determined that an error is associated with the message, and an alert message may be sent from the upstream device to the downstream device via the peripheral interface.

Abstract: A transmitter device that repeatedly transmits an identical frame includes a circuitry that generates the frame and transmits the frame a plurality of times. The frame includes marking areas that divide the frame into a plurality of frame segments having different lengths. The marking area is formed in the frame by part of the frame and is distinguishable from other parts of the frame. The marking area does not change data content transmitted by the frame. The frame segments obtained from the identical frame that is repeatedly transmitted by the circuitry are combined to reconstruct a complete frame identical to the frame transmitted by the transmitter device.

Abstract: Disclosed is a display device including a first storage unit having driving data for driving a display panel and a first check SUM data on the driving data stored therein, a second storage unit for retrieving the driving data and the first check SUM data from the first storage unit and storing the driving data and the check SUM data in response to the instruction of a ROM interface, and a data error detection/correction unit generating a second check SUM data with reference to the driving data stored in the second storage unit.

Abstract: A cost function is obtained. For each of a plurality of groups of nodes, the cost function is evaluated by obtaining, for a given group of nodes, one or more reliability values associated with the given group of nodes; the one or more reliability values include sign and magnitude. For a given group of nodes, a reliability value with a smallest magnitude is selected where the evaluated cost function for the given group of nodes is set to the smallest magnitude. One of the plurality of groups of nodes is selected based at least in part on the evaluated cost functions. Error correction decoding related processing is performed on the selected group of nodes.

Abstract: Systems, methods and apparatus are described to interleave LDPC coded data for reception over a mobile communications channel, such as, for example, a satellite channel. In exemplary embodiments of the present invention, a method for channel interleaving includes segmenting a large LDPC code block into smaller codewords, randomly shuffling the code segments of each codeword and then convolutionally interleaving the randomly shuffled code words. In exemplary embodiments of the present invention, such random shuffling can guarantee that no two consecutive input code segments will be closer than a defined minimum number of code segments at the output of the shuffler. In exemplary embodiments of the present invention, by keeping data in, for example, manageable sub-sections, accurate SNR estimations, which are needed for the best possible LDPC decoding performance, can be facilitated based on, for example, iterative bit decisions.

Abstract: Various embodiments of the present invention provide systems and methods for stochastic stream decoding of binary LDPC codes. For example, a data decoder circuit is discussed that includes a number of variable nodes and check nodes, with serial connections between the variable nodes and the check nodes. The variable nodes are each operable to perform a real-valued computation of a variable node to check node message for each neighboring check node. The check nodes are operable to perform a real-valued computation of a check node to variable node message for each neighboring variable node. The messages are passed iteratively between the variable nodes and the check nodes.

Abstract: Retransmission techniques are disclosed. These techniques may be used in networks employing contention-based access schemes, such as CSMA. For instance, a device may receive a corrupted packet from a transmitting device, and determine a cause of the corruption. When the determined cause of the corruption is an in-network packet collision, the device allows the transmitting device to send a retransmission of the packet in accordance with a contention-based access scheme. However, when the determined cause of the corruption is other than an in-network packet collision, the device provides retransmission assistance to the transmitting device. This retransmission assistance may include a channel reservation for a retransmission, and/or one or more link adaptation suggestions for the transmitting device.

Abstract: TTI bundling is included for Msg3 transmissions in LTE communications. A reserved group of preambles or reserved set of random access preamble transmission opportunities are used to indicate user equipment (UE) need of uplink (UL) transmission of a TTI-bundled Msg3. The UE transmits the same redundancy version for transmissions within a TTI bundle as the eNB expects even if any of the transmissions are dropped due to collisions with an Msg3 transmission. In addition, co-existence of TTI bundling and UL semi-persistent scheduling (SPS) for TDD DL/UL configurations is provided using SPS intervals which are multiples of various fixed time periods.

Abstract: Mechanisms are provided for broadcasting data to a plurality of receiver devices. A data broadcast transmission rate and a level of error correction to be used when broadcasting data are determined based on prior feedback received from the plurality of receiver devices. The feedback comprises channel condition information specifying conditions of one or more connections of a channel over which data was previously broadcast to the receiver devices. Data to be broadcast to the plurality of receivers is encoded in accordance with the determined level of error correction. The encoded data is broadcast at the determined data broadcast transmission rate over the channel to the plurality of receiver devices.

Abstract: An apparatus for performing sequence detection on a stream of incoming bits comprises a memory and circuitry coupled to the memory. The circuitry is operative, for each bit of the stream of incoming bits, to overwrite a first binary number presently stored in the memory with a second binary number, and to provide an output indicative of when the second binary number is equal to a predetermined value. The output indicative of when the second binary number is equal to the predetermined value is, in turn, indicative of when a binary number constructed by the stream of incoming bits is divisible by a prescribed integer.

Abstract: An encoder creates an (p,k,n) n-state codeword with p n-state symbols of which k n-state symbols are data symbols, an n-state symbol being represented by a signal with n>2, p>2 and k>(p-k). Intermediate states of an encoder in forward and in reverse direction are provided in a comparative n-state expression and implemented on a processor. A plurality of signals representing a codeword with at least one n-state symbol in error is processed by the processor by evaluating the comparative n-state expression. A partial result of an expression is determined after a symbol has been received. An error location and an error magnitude are determined. The error is corrected by the processor.

Abstract: The specification describes data processes for analyzing large data steams for target anomalies. “Sequential dependencies” (SDs) are chosen for ordered data and present a framework for discovering which subsets of the data obey a given sequential dependency. Given an interval G, an SD on attributes X and Y, written as X?G Y, denotes that the distance between the Y-values of any two consecutive records, when sorted on X, are within G. SDs may be extended to Conditional Sequential Dependencies (CSDs), consisting of an underlying SD plus a representation of the subsets of the data that satisfy the SD. The conditional approximate sequential dependencies may be expressed as pattern tableaux, i.e., compact representations of the subsets of the data that satisfy the underlying dependency.

Abstract: Dynamic pipeline cache error correction includes receiving a request to perform an operation that requires a storage cache slot, the storage cache slot residing in a cache. The dynamic pipeline cache error correction also includes accessing the storage cache slot, determining a cache hit for the storage cache slot, identifying and correcting any correctable soft errors associated with the storage cache slot. The dynamic cache error correction further includes updating the cache with results of corrected data.

Abstract: A programmatic time-gap defect correction apparatus and method corrects errors which may go undetected by a computer system. Buffer underruns or overruns, which may incur errors in data transfers, yet remain undetected and uncorrected in a computer system, are corrected by an error avoidance module in accordance with the invention. Bytes transferred to and from buffers, used by an I/O controllers to temporarily store data while being transferred between synchronous and asynchronous devices, are counted and an error condition is forced based on the count. If the count exceeds the capacity of the buffer, an error condition is forced, thereby reducing chances that errors are incurred into the data transfer.

Abstract: A data processing apparatus has error detection units each configured to generate an error signal if a first and second sample of a signal associated with execution of an instruction differ. Error value generation circuitry generates an error value showing if any of the error detection units have generated the error signal. Error value stabilisation circuitry performs a stabilisation procedure comprising re-sampling the error value to remove metastability. Error recovery circuitry initiates re-execution of the instruction if the error value is asserted. Count circuitry holds a counter value in association with the error value, the counter value set to a predetermined value when the error value is generated and decremented each time the error value is re-sampled prior to reaching the error value stabilisation circuitry. The error value bypasses the stabilisation procedure if the counter value is zero before the error value reaches the error value stabilisation circuitry.

Abstract: An efficient coding and modulation system for transmission of digital data over plastic optical fibers is disclosed. The digital signal is coded by a three-level coset coding. The spectral efficiency of the system is configurable by selecting the number of bits to be processed in each of the levels. The first level applies to the digital data a binary BCH coding and performs coset partitioning by constellation mapping and lattice transformations. Similarly, second level applies another binary BCH coding, which may be performed selectably in accordance with the desired configuration by two BCH codes with substantially the same coding rate, operating on codewords of different sizes. The third level is uncoded. The second and third levels undergo mapping and lattice transformation. After an addition of the levels, a second-stage lattice transformation is performed to obtain a zero-mean constellation. The symbols output from such three-level coset coder are then further modulated.

Abstract: A method for reducing uncorrectable errors of a memory device regarding Error Correction Code (ECC) includes: performing majority vote according to data read at different times at a same address in order to generate majority vote data corresponding to the address; and checking whether the majority vote data has any uncorrectable error in order to determine whether to output the majority vote data as data of the address. For example, the method further includes: within the data read at different times at the same address, temporarily storing all of the data except for data of a last time into buffering regions/buffers, respectively, with the majority vote data being temporarily stored into a second buffering region/buffer to utilize a latest generated portion within the majority vote data to replace a latest retrieved portion within data in the second buffering region/buffer. An associated memory device and the controller thereof are further provided.

Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.

Abstract: Improved apparatus, systems and methods, such as those for testing an error correction code (ECC) encoder/decoder for solid-state memory devices, are provided. In one or more embodiments, the improved systems and methods deliberately inject errors into memory storage areas of memory devices to test the operation of the ECC encoder/decoder.

Abstract: A method and/or apparatus are provided for protecting control information during broadcasts in a system where primary and second mobile broadcast control messages (PMBCM and SMBCM) are utilized. In order to protect the SMBCM, a first hash information instance is computed based on hashes for each a plurality of control data blocks for the SMBCM. The first hash information instance is appended to the PMBCM. Error-correcting code words are generated for the plurality of hashes for the plurality of control data blocks for the SMBCM. These error-correcting code words are appended to the control data blocks of the SMBCM. A receiver uses the first hash instance information in the PMBCM to determine if any control data blocks of the SMBCM are corrupt. If so, the error-correcting code words may be used to reconstruct the corrupted hash(es) for the control data block(s) in order to authenticate the remaining control data blocks.

Abstract: A method, a recording terminal, a server, and a system for repairing media file recording errors are disclosed in embodiments of the present invention. The method includes: generating description information about a recording error when a recording terminal identifies the recording error in live recording of a media file; sending a recording error repair request that carries the description information to a network device; and repairing the media file recorded by the recording terminal according to repair information when receiving the repair information sent by the network device according to the description information. With the present invention, the recording errors are repaired through a bidirectional network between the recording terminal and the network device, and reliability of repairing the recording errors is ensured.

Abstract: A soft decision threshold control system and method may be used with a forward error correction (FEC) scheme to adjust or tune one or more soft decision thresholds in response to one or more bit value averages for the threshold(s) and in response to a bit error rate (BER). The bit value average for a soft decision threshold generally refers to an average number of binary values (e.g., logic ones and/or zeros) occurring in a bit stream detected using the soft decision threshold. For different BER levels in a particular system, for example, one or more of the soft decision thresholds may have a predetermined bit value average, which has been determined to provide a certain level of performance (e.g., an optimum performance). Thus, one or more of the soft decision thresholds may be adjusted such that the bit value averages for the soft decision thresholds are adjusted as a function of the BER.

Abstract: Systems and methods for processing and decoding TCM/BCM-coded signal vectors. A multi-dimensional signal vector is received by, for example, a TCM or BCM decoder. The TCM/BCM decoder identifies the closest signal points in the signal constellation set, or “nearest neighbors,” for each dimension of the received signal vector. The TCM/BCM decoder then forms a test set that includes a plurality of multi-dimensional test vectors, where each dimension of each test vector is based on an identified nearest neighbor. In particular, each test point in the test set is based on a different combination of the nearest neighbors. The TCM/BCM decoder can compute branch metrics based on only the test points in the test set, and can make detection decisions using the computed branch metrics.

Abstract: A counter configuration operates in cooperation with a delay configuration such that the counter configuration counts an input interval based on a given clock speed and a given clock interval while the delay configuration provides an enhanced data output that is greater than what would otherwise be provided by the given clock speed. The counter configuration counts responsive to a selected edge in the clock interval. An apparatus in the form of a correction arrangement and an associated method are configured to monitor at least the delay configuration output for detecting a particular time relationship between an endpoint of the input interval and a nearest occurrence of the selected clock edge in the given clock signal that is indicative of at least a potential error in the enhanced data output and determining if the potential error is an actual error for subsequent use in correcting the enhanced data output.

Abstract: A circuit and method are provided for providing a value representing the number of leading zero bits in an input data word. The input data word contains random data. The input data word is logically divided into odd and even bit positions. The circuit includes a first comparator circuit comparing data in the odd bit positions to data in the even bit positions. The circuit further includes a second comparator circuit comparing the data in the odd bit positions to a result of a logical operation performed on the data in the odd and even bit positions. The circuit further includes a half-width leading zero counting circuit that provides the value representing the number of leading zero bits in the input data word. The comparator circuits provide a correction bit value concatenated to the value.

Abstract: Error correction code (ECC) checkbits are generated for each write access to a memory address based on both the data to be written (the write data) and the memory address. The ECC checkbits are stored with the write data at the memory device associated with the memory address. In addition, the memory device can selectively perform error detection and correction for write accesses using the ECC checkbits. For example, the memory device can include an ECC control register that stores control information to selectively enable and disable error detection and correction for write accesses. In an embodiment, error detection and correction can be selectively enabled and disabled for different sizes of write data.

Abstract: A scheme of enhanced block coding based on small size block code is provided. Such is achieved by obtaining extended basis sequences for a (32, O) code with O=1, 2, . . . 12; selecting an offset starting value that produces maximum error correction capability in each O value; and generating basis sequences for a (48, O) code based on the obtained extended basis sequences for the (32, O) code with the offset starting value selected based on the selecting step. The offset starting value could be selected as 18, which results in the largest sum of distances.

Abstract: The apparatus and methods allow for correcting data from a sensor due to changes in relative speed of that sensor. The methods and apparatus described use a determined entropy from data associated with across a direction of travel of the sensor together with a determined entropy from data associated with in a direction of travel of the sensor. The determined entropies allow for providing for correcting the data for changes in the relative speed of the sensor. Also, described are methods and apparatus for correcting data from at least first and second sensors of a measurement device, whereby features are correlated from datasets taken from both sensors to determine one or more corresponding signatures. These signatures can then be used to correct the data from first and second sensors.

Abstract: Provided is a method and apparatus for detecting errors generated by a DMB receiver by not processing received audio/video data in realtime. The error detection method includes: calculating a time required to process one frame obtained by dividing received data into frames having a predetermined size; and determining as an error a situation in which the calculated time exceeds time predetermined to process the one frame in realtime and transmitting an error recovering command. Accordingly, subsequent data frames can be normally processed by quickly detecting the error and recovering the error by initializing their associated modules.

Abstract: A method, an apparatus, and a computer program product for matching a rate of data bits to a desired rate by deletion of redundant data bits or repetition of data bits are disclosed. In a non-interleaved matrix of the data bits, a pattern of bits to be deleted or repeated to provide the desired data rate is determined. An address of each bit in the pattern in a manner inverse to the interleaving process is decoded to produce a respective address of the bit in the matrix. The respective bit in the interleaved data bits is deleted or repeated depending upon the respective address. The address decoding is performed in the same manner as a coding of addresses for producing the interleaved data bits from the non-interleaved matrix of the data bits.

Abstract: A flash memory system which includes a flash memory and a memory controller. The flash memory is configured to perform a read operation using a plurality of read levels. The memory controller is configured to recover original data using a counter value provided from the flash memory. The flash memory converts read result values obtained using the plurality of read levels into the counter value to provide the counter value to the memory controller.

Abstract: An A/D conversion unit performs an A/D conversion operation twice during a hold period of an analog value. In a first conversion operation, the A/D conversion unit compares the analog value with a first reference voltage and outputs a comparison result as first converted data. In a second conversion operation, the A/D conversion unit compares the analog value with a second reference voltage and outputs a comparison result as second converted data. The second reference voltage is a voltage obtained by adding or subtracting a minimum resolution voltage to or from the first reference voltage. A digital processing unit averages errors of the first and second converted data by digital processing to detect an A/D conversion error, and feeds back a detection result to the A/D conversion unit as a control value to perform voltage control.

Abstract: A method of notifying on a downstream link (2) of a network element (20) a transmission defect affecting an audio signal coded on an upstream link (1) of said network element. The method comprises a step in which the network element (20) sends, on said downstream link, an audio coded notification signal containing a specific notification pattern. Application to the switchover from an asynchronous link to a synchronous link.

Abstract: Provided are a method and apparatus of performing a HARQ in a multiple carrier system. A receiver determines the size of a soft buffer to be used in an effective HARQ process on the basis of the maximum number of effective HARQ processes over a plurality of component carriers and stores the received transport block in the soft buffer. The present invention enables the performance of a HARQ in an efficient manner by using multiple carriers in the event the size of the soft buffer is limited.

Abstract: To realize prompt and efficient data communication by dynamically changing the optimum MCS and PC. A base station (120) serving as a wireless communication device according to the present invention includes an obtaining unit (220) for obtaining an RSSI and an SINR of a receive signal upon generation of transmission data to be sent to a PHS terminal (110) serving as a wireless communication device to communicate with; a modulation and coding scheme determining unit (224) for determining an MCS, based on the volume of the transmission data; a transmission power determining unit (226) for determining a transmission power, based on the volume of the transmission data, the RSSI, the SINR, and the MCS determined; and a wireless communication unit (214) for sending the transmission data, using the MCS determined and the transmission power determined.

Abstract: Systems and methods for constructing concatenated codes for data storage channels, such as holographic storage channels, are provided. The concatenated codes include an outer BCH code and an inner iteratively decodable code, such as an LDPC code or turbo code. The correction power and coding rate of one or both of the codes may be programmable based on the channel characteristics and the desired SNR coding gain. The correction power and/or coding rate of the inner and/or outer code may also be dynamically adjusted in real-time to compensate for time-varying error conditions on the channel.