Abstract: A method and apparatus for forming an organic semiconductor circuit. A circuit printer is positioned relative to a location on a surface of a composite structure. A number of organic materials is deposited in a pattern on the surface of the composite structure at the location to form the organic semiconductor circuit on the surface of the composite structure at the location.

Abstract: Embodiments of the present invention provide an array of fin-type transistors formed on top of an oxide layer. At least a first and a second of the fin-type transistors have their respective source and drain contacts being formed inside the oxide layer, with one of the contacts of the first fin-type transistor being conductively connected to one of the contacts of the second fin-type transistor by an epitaxial silicon layer, wherein the epitaxial silicon layer is formed on top of a first and a second fin of the first and second fin-type transistors respectively.

Abstract: Embodiment of the present invention provides a method of forming a semiconductor device. The method includes providing a semiconductor substrate; epitaxially growing a silicon-carbon layer on top of the semiconductor substrate; amorphizing the silicon-carbon layer; covering the amorphized silicon-carbon layer with a stress liner; and subjecting the amorphized silicon-carbon layer to a solid phase epitaxy (SPE) process to form a highly substitutional silicon-carbon film. In one embodiment, the highly substitutional silicon-carbon film is formed to be embedded stressors in the source/drain regions of an nFET transistor, and provides tensile stress to a channel region of the nFET transistor for performance enhancement.

Abstract: A barrier infrared detector with absorber materials having selectable cutoff wavelengths and its method of manufacture is described. A GaInAsSb absorber layer may be grown on a GaSb substrate layer formed by mixing GaSb and InAsSb by an absorber mixing ratio. A GaAlAsSb barrier layer may then be grown on the barrier layer formed by mixing GaSb and AlSbAs by a barrier mixing ratio. The absorber mixing ratio may be selected to adjust a band gap of the absorber layer and thereby determine a cutoff wavelength for the barrier infrared detector. The absorber mixing ratio may vary along an absorber layer growth direction. Various contact layer architectures may be used. In addition, a top contact layer may be isolated into an array of elements electrically isolated as individual functional detectors that may be used in a detector array, imaging array, or focal plane array.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first region and a second region. The semiconductor device further includes a first buffer layer formed over the substrate and between first and second isolation regions in the first region and a second buffer layer formed over the substrate and between first and second isolation regions in the second region. The semiconductor device further includes a first fin structure formed over the first buffer layer and between the first and second isolation regions in the first region and a second fin structure formed over the second buffer layer and between the first and second isolation regions in the second region. The first buffer layer includes a top surface different from a top surface of the second buffer layer.

Abstract: One illustrative method disclosed herein includes forming a trench within an isolated region of a bulk semiconductor substrate, forming a region of an insulating material in the trench and forming a semiconductor material within the trench and above the upper surface of the region of insulating material. A substrate disclosed herein includes an isolated substrate region in a bulk semiconductor substrate, a region of an insulating material that is positioned within a trench defined in the isolated substrate region and a semiconductor material positioned within the trench and above the upper surface of the region of insulating material.

Abstract: A MOS transistor includes a pair of impurity regions formed in a substrate as spaced apart from each other, and a gate electrode formed on a region of the substrate located between the pair of impurity regions. Each of the impurity regions is formed of a first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer. The first epitaxial layer is formed of at least one first sub-epitaxial layer and a respective second sub-epitaxial layer stacked on each first sub-epitaxial layer. An impurity concentration of the first sub-epitaxial layer is less than that of the second sub-epitaxial layer.

Abstract: A method of forming a strained semiconductor material that in one embodiment includes forming a cleave layer in a host semiconductor substrate, and contacting a strain inducing material layer on a surface of a of the host semiconductor substrate. A handle substrate is then contacted to an exposed surface of the stress inducing material layer. The transfer portion of the host semiconductor substrate may then be separated from the host semiconductor substrate along the cleave layer. A dielectric layer is formed directly on the transfer portion of the host semiconductor substrate. The handle substrate and the stress inducing material are then removed, wherein the transferred portion of the host semiconductor substrate provides a strained semiconductor layer that is in direct contact with a dielectric layer.

Abstract: First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below ?30° C.

Abstract: A method for manufacturing a distributed feedback laser array includes: forming a bottom separate confinement layer on a substrate; forming a quantum-well layer on the bottom separate confinement layer; forming a selective-area epitaxial dielectric mask pattern on the quantum-well layer; forming a top separate confinement layer on the quantum-well layer through selective-area epitaxial growth using the selective-area epitaxial dielectric mask pattern, the top separate confinement layer having different thicknesses for different laser units; removing the selective-area epitaxial dielectric mask pattern; forming an optical grating on the top separate confinement layer; and growing a contact layer on the optical grating. The present disclosure achieves different emission wavelengths for different laser units without significantly affect emission performance of the quantum-well material.

Abstract: Semiconductor devices with reduced substrate defects and methods of manufacture are disclosed. The method includes forming a dielectric material on a substrate. The method further includes forming a shallow trench structure and deep trench structure within the dielectric material. The method further includes forming a material within the shallow trench structure and deep trench structure. The method further includes forming active areas of the material separated by shallow trench isolation structures. The shallow trench isolation structures are formed by: removing the material from within the deep trench structure and portions of the shallow trench structure to form trenches; and depositing an insulator material within the trenches.

Abstract: The invention provides a method of forming an electronic device from a lamina that has a coefficient of thermal expansion that is matched or nearly matched to a constructed metal support. In some embodiments the method comprises implanting the top surface of a donor body with an ion dosage to form a cleave plane followed by exfoliating a lamina from the donor body. After exfoliating the lamina, a flexible metal support that has a coefficient of thermal expansion with a value that is within 10% of the value of the coefficient of thermal expansion of the lamina is constructed on the lamina. In some embodiments the coefficients of thermal expansion of the metal support and the lamina are within 10% or within 5% of each other between the temperatures of 100 and 600° C.

Abstract: An apparatus for depositing a group III metal nitride film on a substrate, the apparatus comprising a plasma generator to generate a nitrogen plasma from a nitrogen source, a reaction chamber in which to react a reagent comprising a group III metal with a reactive nitrogen species derived from the nitrogen plasma so as to deposit a group III metal nitride on the substrate, a plasma inlet to facilitate the passage of nitrogen plasma from the plasma generator into the reaction chamber and a baffle having one or more flow channels for passage of the nitrogen plasma. The baffle is located between the plasma inlet and the substrate and prevents a direct line of passage for nitrogen plasma between the plasma inlet and the substrate.

Abstract: The present invention relates to a method for relaxing a strained material layer by providing a strained material layer and a low-viscosity layer formed on a first face of the strained material layer; forming a stiffening layer on at least one part of a second face of the strained material layer opposite to the first face thereby forming a multilayer stack; and subjecting the multilayer stack to a heat treatment thereby at least partially relaxing the strained material layer.

Abstract: Provided is a compound semiconductor deposition method of adjusting the luminous wavelength of a compound semiconductor of a ternary or higher system in a nanometer order in depositing the compound semiconductor on a substrate.

Abstract: The semiconductor device is manufactured through the following steps: after first heat treatment is performed on an oxide semiconductor film, the oxide semiconductor film is processed to form an oxide semiconductor layer; immediately after that, side walls of the oxide semiconductor layer are covered with an insulating oxide; and in second heat treatment, the side surfaces of the oxide semiconductor layer are prevented from being exposed to a vacuum and defects (oxygen deficiency) in the oxide semiconductor layer are reduced.

Abstract: In some embodiments of the present invention, methods of using one or more small spot showerhead apparatus to deposit materials using CVD, PECVD, ALD, or PEALD on small spots in a site isolated, combinatorial manner are described. The small spot showerheads may be configured within a larger combinatorial showerhead to allow multi-layer film stacks to be deposited in a combinatorial manner.

Abstract: An object is to provide a semiconductor device including an oxide semiconductor, which has stable electrical characteristics and high reliability. In a manufacturing process of a bottom-gate transistor including an oxide semiconductor layer, heat treatment in an atmosphere containing oxygen and heat treatment in vacuum are sequentially performed for dehydration or dehydrogenation of the oxide semiconductor layer. In addition, irradiation with light having a short wavelength is performed concurrently with the heat treatment, whereby elimination of hydrogen, OH, or the like is promoted. A transistor including an oxide semiconductor layer on which dehydration or dehydrogenation treatment is performed through such heat treatment has improved stability, so that variation in electrical characteristics of the transistor due to light irradiation or a bias-temperature stress (BT) test is suppressed.

Abstract: An optoelectronic semiconductor component comprising a semiconductor layer sequence (3) based on a nitride compound semiconductor and containing an n-doped region (4), a p-doped region (8) and an active zone (5) arranged between the n-doped region (4) and the p-doped region (8) is specified. The p-doped region (8) comprises a p-type contact layer (7) composed of InxAlyGa1-x-yN where 0?x?1, 0?y?1 and x+y?1. The p-type contact layer (7) adjoins a connection layer (9) composed of a metal, a metal alloy or a transparent conductive oxide, wherein the p-type contact layer (7) has first domains (1) having a Ga-face orientation and second domains (2) having an N-face orientation at an interface with the connection layer (9).

Abstract: The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) descried enable forming an epitaxially grown silicon-containing material without using GeH4 in an etch gas mixture of an etch process for a cyclic deposition/etch (CDE) process. The etch process is performed at a temperature different form the deposition process to make the etch gas more efficient. As a result, the etch time is reduced and the throughput is increased.

Abstract: The present disclosure provides a method of semiconductor fabrication including forming an inter-layer dielectric (ILD) layer on a semiconductor substrate. The ILD layer has an opening defined by sidewalls of the ILD layer. A spacer element is formed on the sidewalls of the ILD layer. A gate structure is formed in the opening adjacent the spacer element. In an embodiment, the sidewall spacer also for a decrease in the dimensions (e.g., length) of the gate structure formed in the opening.

Abstract: A crystal manufacturing apparatus capable of manufacturing a crystal in a desired position on a substrate is provided. A spring has one end fixed to a mount and the other end coupled to a magnetic body. The magnetic body has one end coupled to the spring and the other end coupled to a piston. A coil is wound around the magnetic body and electrically connected between a power supply circuit and a ground node (GND). The piston has a linear member inserted in a cylinder. The cylinder has a hollow columnar shape and a small hole at a bottom surface. The cylinder holds a silicon melt. A substrate is supported by an XY stage to be opposed to the small hole of the cylinder. The power supply circuit passes pulse shaped current through the coil to move the piston in an up-down direction (DR1). As a result, a droplet is discharged toward the substrate from the small hole at an initial speed of 1.02 m/s.

Abstract: A method is for manufacturing a nitride semiconductor laser element including a substrate, a nitride semiconductor layer that is laminated on the substrate and that has a ridge on its surface, an insulating protective film, and an electrode that is electrically connected with the nitride semiconductor layer. The method includes forming the ridge; forming a monocrystalline first film from the side faces of the ridge to the nitride semiconductor layer on both sides of the ridge; and forming a second film containing polycrystalline or an amorphous substance over the first film thereby forming the insulating protective film.

Abstract: A III nitride structure includes a film 108 having a surface composed of a metal formed in a predetermined region on the surface of a substrate 102, and a fine columnar crystal 110 composed of at least a III nitride semiconductor formed on the surface of the substrate 102, wherein the spatial occupancy ratio of the fine columnar crystal 110 is higher on the surface of the substrate 102 where the film 108 is not formed than that on the film.

Abstract: A method for impurity-induced disordering in III-nitride materials comprises growing a III-nitride heterostructure at a growth temperature and doping the heterostructure layers with a dopant during or after the growth of the heterostructure and post-growth annealing of the heterostructure. The post-growth annealing temperature can be sufficiently high to induce disorder of the heterostructure layer interfaces.

Abstract: A method of forming an amorphous silicon film includes: forming a seed layer on a surface of a base by heating the base and supplying an amino silane-based gas to the heated base, forming the amorphous silicon film with thickness for layer growth on the seed layer by heating the base and supplying a silane-based gas containing no amino group to the seed layer on the surface of the heated base, and decreasing a film thickness of the amorphous silicon film by etching the amorphous silicon film formed with thickness for layer growth.

Abstract: There is provided a semiconductor wafer including a base wafer that has an impurity region in which an impurity atom has been introduced into silicon, a plurality of seed bodies provided in contact with the impurity region, and a plurality of compound semiconductors each provided in contact with the corresponding seed bodies and lattice-matched or pseudo-lattice-matched to the corresponding seed bodies. The semiconductor wafer can further include an inhibitor provided on the base wafer and in which a plurality of apertures exposing at least a part of the impurity region are provided.

Abstract: A semiconductor body comprised of a semiconductor material includes a first monocrystalline region of the semiconductor material having a first lattice constant along a reference direction, a second monocrystalline region of the semiconductor material having a second lattice constant, which is different than the first, along the reference direction, and a third, strained monocrystalline region between the first region and the second region.

Abstract: An optical semiconductor element includes: a grating base layer including a projection-recess structure disposed over a substrate; and a grating cover layer including a group III-V semiconductor having three or more elements, wherein the grating cover layer includes a first region which is disposed over recessed portions of the grating base layer and which has a compositional ratio of a group III-V semiconductor having a first refractive index, and a second region which is disposed over projecting portions of the grating base layer and which has a compositional ratio of a group III-V semiconductor having a second refractive index that is smaller than the first refractive index, wherein the grating base layer includes a group III-V semiconductor having a third refractive index that is smaller than the first refractive index.

Abstract: A method for manufacturing optoelectronic devices comprising the steps of: providing a common growth substrate; forming a light-emitting epitaxy structure on the common growth substrate; forming a stripping layer on the light-emitting epitaxy structure; forming a solar cell epitaxy structure on the stripping layer; forming an adhesive layer on the solar cell epitaxy structure; proving a solar cell permanent substrate on the adhesive layer; and removing the stripping layer to form a light-emitting device and a solar cell device separately.

Abstract: A semiconductor component having a low resistance conduction path and a method for manufacturing the semiconductor component. When the semiconductor component is a Schottky diode, one or more trenches are formed in an epitaxial layer of a first conductivity type that is formed over a semiconductor substrate of the first conductivity type. The trenches may extend into the semiconductor material. Epitaxial semiconductor material of a second conductivity type is selectively grown along the sidewalls of the trenches. An anode contact is formed in contact with the epitaxial layer and the selectively grown epitaxial material and a cathode contact is formed in contact with the semiconductor substrate.

Abstract: System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.

Abstract: A method of manufacturing a transistor of a semiconductor device, the method including forming a gate pattern on a semiconductor substrate, forming a spacer on a sidewall of the gate pattern, wet etching the semiconductor substrate to form a first recess in the semiconductor substrate, wherein the first recess is adjacent to the spacer, and wet etching the first recess to form a second recess in the semiconductor substrate.

Abstract: A semiconductor device has memory cell portions and compensation capacitance portions on a single substrate. The memory cell portion and the compensation capacitance portion have mutually different planar surface areas. The memory cell portion and the compensation capacitance portion include capacitance plate electrodes of the same structure. The capacitance plate electrode has a laminated structure including a boron-doped silicon germanium film and a metal film.

Abstract: A transistor device having non-alloyed ohmic contacts formed by a process that improves the contact morphology and reduces metal spiking into the semiconductor layers. During fabrication, a regrowth mask is deposited on the semiconductor device. A portion of the regrowth mask and the epitaxial semiconductor layers is removed, defining areas for selective regrowth of a highly-doped semiconductor material. The remaining portion of the regrowth mask forms a regrowth mask residual layer. After regrowth, ohmic contacts are formed on the regrowth structures without the use of a high-temperature annealing process. The regrowth mask residual layer does not need to be removed, but rather remains on the device throughout fabrication and can function as a passivation layer and/or a spacer layer.

Abstract: An embodiment is a semiconductor structure. The semiconductor structure comprises an epitaxial region, a gate structure, a contact spacer, and an etch stop layer. The epitaxial region is in a substrate. A top surface of the epitaxial region is elevated from a top surface of the substrate, and the epitaxial region has a facet between the top surface of the substrate and the top surface of the epitaxial region. The gate structure is on the substrate. The contact spacer is laterally between the facet of the epitaxial region and the gate structure. The etch stop layer is over and adjoins each of the contact spacer and the top surface of the epitaxial region. A ratio of an etch selectivity of the contact spacer to an etch selectivity of the etch stop layer is equal to or less than 3:1.

Abstract: According to one embodiment, a method includes forming a first SiGe layer having a first profile of a concentration of Ge on a semiconductor substrate, forming a second SiGe layer having a second profile of a concentration of Ge on the first SiGe layer, the second profile lower than a first peak of the first profile, forming a mask layer on the second SiGe layer, etching the first and second SiGe layers by anisotropic etching using the mask layer as a mask to form trenches, selectively removing the first SiGe layer exposed into the trenches to form a cavity under the second SiGe layer, and oxidizing side and lower surfaces of the second SiGe layer exposed in the trenches and the cavity to increase the concentration of Ge in the second SiGe layer.

Abstract: A semiconductor device includes word lines and interlayer insulating layers alternately stacked, a channel layer penetrating the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding the channel layer, and first charge trap layers surrounding the tunnel insulating layer, interposed between the word lines and the tunnel insulating layer, respectively, and doped with first impurities.

Abstract: A substrate capable of achieving a lowered probability of defects produced in a step of forming an epitaxial film or a semiconductor element, a semiconductor device including the substrate, and a method of manufacturing a semiconductor device are provided. A substrate is a substrate having a front surface and a back surface, in which at least a part of the front surface is composed of single crystal silicon carbide, the substrate having an average value of surface roughness Ra at the front surface not greater than 0.5 nm, a standard deviation ? of that surface roughness Ra not greater than 0.2 nm, an average value of surface roughness Ra at the back surface not smaller than 0.3 nm and not greater than 10 nm, standard deviation ? of that surface roughness Ra not greater than 3 nm, and a diameter D of the front surface not smaller than 110 mm.

Abstract: A semiconductor wafer includes a first semiconductor, and a second semiconductor formed directly or indirectly on the first semiconductor. The second semiconductor contains a first impurity atom exhibiting p-type or n-type conductivity, and a second impurity atom selected such that the Fermi level of the second semiconductor containing both the first and second impurity atoms is closer to the Fermi level of the second semiconductor containing neither the first impurity atom nor the second impurity atom, than the Fermi level of the second semiconductor containing the first impurity atom is. For example, the majority carrier of the second semiconductor is an electron, and the Fermi level of the second semiconductor containing the first and second impurity atoms is lower than the Fermi level of the second semiconductor containing the first impurity atom.

Abstract: III-N material grown on a silicon substrate includes a single crystal rare earth oxide layer positioned on a silicon substrate. The rare earth oxide is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the rare earth oxide layer. An inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer. A cap layer of AlN is grown on the final III-N layer and a III-N layer of material with one of an LED structure and an HEMT structure is grown on the AlN cap layer.

Abstract: Various embodiments of the present disclosure pertain to selective photo-enhanced wet oxidation for nitride layer regrowth on substrates. In one aspect, a method may comprise: forming a first III-nitride layer with a first low bandgap energy on a first surface of a substrate; forming a second III-nitride layer with a first high bandgap energy on the first III-nitride layer; transforming portions of the first III-nitride layer into a plurality of III-oxide stripes by photo-enhanced wet oxidation; forming a plurality of III-nitride nanowires with a second low bandgap energy on the second III-nitride layer between the III-oxide stripes; and selectively transforming at least some of the III-nitride nanowires into III-oxide nanowires by selective photo-enhanced oxidation.

Abstract: A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate.

Abstract: An epitaxial structure for a III-Nitride based optical device, comprising an active layer with anisotropic strain on an underlying layer, where a lattice constant and strain in the underlying layer are partially or fully relaxed in at least one direction due to a presence of misfit dislocations, so that the anisotropic strain in the active layer is modulated by the underlying layer.

Abstract: A method of producing a transistor includes providing a substrate including an electrically conductive material layer stack positioned on the substrate. A first electrically insulating material layer is deposited so that the first electrically insulating material layer contacts a first portion of the electrically conductive material layer stack. A second electrically insulating material layer is conformally deposited so that the second electrically insulating material contacts the first electrically insulating layer, and contacts a second portion of the electrically conductive material layer stack, and contacts at least a portion of the substrate.

Abstract: An apparatus and method for making same. Some embodiments include a light-emitting device having a light-emitting active region; a tunneling-barrier (TB) structure facing adjacent the active region; a TB grown-epitaxial-metal-mirror (TB-GEMM) structure facing adjacent the TB structure, wherein the TB-GEMM structure includes at least one metal is substantially lattice matched to the active region; and a conductivity-type III-nitride crystal structure adjacent facing the active region opposite the TB structure. In some embodiments, the active region includes an MQW structure. In some embodiments, the TB-GEMM includes an alloy composition such that metal current injectors have a Fermi energy potential substantially equal to the sub-band minimum energy potential of the MQW. Some embodiments further include a second mirror (optionally a GEMM) to form an optical cavity between the second mirror and the TB-GEMM structure.

Abstract: A method for making epitaxial structure is provided. The method includes providing a substrate having an epitaxial growth surface, growing a buffer layer on the epitaxial growth surface; placing a graphene layer on the buffer layer; epitaxially growing an epitaxial layer on the buffer layer; and removing the substrate. The graphene layer includes a number of apertures to expose a part of the buffer layer. The epitaxial layer is grown from the exposed part of the buffer layer and through the apertures.

Abstract: A vertical GaN-based blue LED has an n-type GaN layer that was grown directly on Low Resistance Layer (LRL) that in turn was grown over a silicon substrate. In one example, the LRL is a low sheet resistance GaN/AlGaN superlattice having periods that are less than 300 nm thick. Growing the n-type GaN layer on the superlattice reduces lattice defect density in the n-type layer. After the epitaxial layers of the LED are formed, a conductive carrier is wafer bonded to the structure. The silicon substrate is then removed. Electrodes are added and the structure is singulated to form finished LED devices. In some examples, some or all of the LRL remains in the completed LED device such that the LRL also serves a current spreading function. In other examples, the LRL is entirely removed so that no portion of the LRL is present in the completed LED device.

Abstract: A seed crystal including mixed phase grains having high crystallinity at a low density is formed under a first condition over an insulating film, and then a first microcrystalline semiconductor film is formed over the seed crystal under a second condition that allows the mixed phase grains to grow and a space between the mixed phase grains to be filled. Then, a second microcrystalline semiconductor film is formed over the first microcrystalline semiconductor film under a third condition that allows formation of a microcrystalline semiconductor film having high crystallinity without increasing the space between the mixed phase grains included in the first microcrystalline semiconductor film.

Abstract: A method of at least partially releasing an epitaxial layer of a material from a substrate. The method comprises the steps of: forming a patterned sacrificial layer on the substrate such that the substrate is partially exposed and partially covered by the sacrificial layer; growing the epitaxial layer on the patterned sacrificial layer by nano-epitaxial lateral overgrowth such that the epitaxial layer is formed above an intermediate layer comprising the patterned sacrificial layer and said material; and selectively etching the patterned sacrificial layer such that the epitaxial layer is at least partially released from the substrate.