Abstract: The present application discloses a semiconductor integrated circuit including a substrate having electrical devices formed thereon, a local interconnection layer formed over the substrate, and a global interconnection layer formed over the local interconnection layer. The local interconnection layer has a first set of conductive structures arranged to electrically connect within the individual electrical devices, among one of the electrical devices and its adjacent electrical devices, or vertically between the devices and the global interconnection layer. At least one of the first set of conductive structures is configured to have a resistance value greater than 50 ohms. The global interconnection layer has a second set of conductive structures arranged to electrically interconnect the electrical devices via the first set conductive structures.

Abstract: The present invention relates to a printed circuit board assembly (10), said printed circuit board assembly comprising: a substrate (100); two or more electronic components which are categorized, wherein each component is secured to the substrate by securing means having a different predetermined thermal-release temperature, depending on which category said component belongs to. The invention furthermore relates to a method of assembling the printed circuit board assembly and a method of disassembling the printed circuit board assembly according to the invention.

Abstract: Disclosed are a light emitting device package and a light unit having the same. The light emitting device package includes a body including a cavity at a first side surface, first and second lead frames in the cavity, a light emitting device connected to the first and second lead frames, a heat radiation pad on a second side surface of the body, a heat radiation frame on a third side surface of the body, and first and second electrode pads disposed on the second side surface of the body and spaced apart from the heat radiation pad.

Abstract: A semiconductor device includes a substrate having a first side and a second side such that the first and second sides face each other, a through via plug penetrating the substrate, an insulating film liner, and an antipollution film. The insulating film liner is between the through via plug and the substrate and the insulating film liner has a recessed surface with respect to the second side. The antipollution film covers the second side and the antipollution film is on the recessed surface and between the through via plug and the substrate.

Abstract: An apparatus including an electronic device having a plurality of substantially collocated components, the plurality of components including an integrated circuit (IC) chip, an energy supply operable to electrically power the IC chip, and an energy harvesting (EH) device operable to convert non-electrical energy to electrical energy supplied to the energy supply. A material substantially encloses at least a portion of at least one of the IC chip, the energy supply, and the EH device.

Abstract: A mounting structure which reduces the mechanical stress added to a low-? material due to warping caused by the difference in thermal expansion coefficients between a chip and a chip support during mounting. This mounting structure includes: a low-? layer formed on top a semiconductor substrate; an electrode layer formed on the low-? layer; a protective layer formed the low-? layer and the electrode layer and having an opening reaching the electrode layer; a first solder layer filling the opening and formed on the electrode layer inside; a second solder layer formed on the first solder layer and having an elastic modulus smaller than the first solder layer; and a support layer connected to the second solder layer and supporting the semiconductor substrate. The protective layer has a greater elastic modulus and a smaller thermal expansion coefficient than an underfill layer formed between the protective layer and the support layer.

Abstract: A method for manufacturing a semiconductor device includes preparing a semiconductor element including electrode pads laid out along the periphery of the semiconductor element in a tetragonal frame-shaped array to form a line of electrode pads along each side of the semiconductor element, preparing a wiring substrate including connection pads corresponding to the electrode pads, applying solder including a bulging central portion on an upper surface of each connection pad, forming pillar-shaped electrode terminals on the electrode pads so that each electrode terminal has an axis separated from a peak of the bulging central portion of the solder on the corresponding connection pad in a longitudinal direction of the corresponding connection pad, and electrically connecting the electrode terminals with the solder to the connection pad.

Abstract: A system and method for packaging light emitting semiconductors (LESs) is disclosed. An LES device is provided that includes a heatsink and an array of LES chips mounted on the heatsink and electrically connected thereto, with each LES chip comprising connection pads and a light emitting area configured to emit light therefrom responsive to a received electrical power. The LES device also includes a flexible interconnect structure positioned on and electrically connected to each LES chip to provide for controlLES operation of the array of LES chips, with the flexible interconnect structure further including a flexible dielectric film configured to conform to a shape of the heatsink and a metal interconnect structure formed on the flexible dielectric film and that extends through vias formed in the flexible dielectric film so as to be electrically connected to the connection pads of the LES chips.

Abstract: An optical transceiver is disclosed, where the optical transceiver includes an optical subassembly (OSA) with a bottom plate for dissipating heat and connected to an electronic circuit with a flexible printed circuit (FPC). The FPC is soldered with the side electrodes of the OSA as forming a solder fillet in the plane electrode, or the FPC is soldered with the plane electrodes of the OSA as forming the solder fillet in the side electrodes, and leaving a limited room for receiving the curved FPC in peripheries of the OSA.

Abstract: There are provided a package substrate, a manufacturing method thereof, and a mold therefor. The method of manufacturing a package substrate includes: preparing a chip component and a substrate; mounting the chip component on a main surface of the substrate; preparing a mold having a cavity and protrusions formed on a ceiling surface thereof; disposing the substrate on a bottom surface of the mold such that the chip component is positioned within the cavity; and forming a resin sealing body that collectively hermetically seals the chip component and the main surface of the substrate by injecting a pressurized liquid resin into the cavity.

Abstract: A mobile terminal includes a first case having a groove recessed along one region, a second case coupled to the first case to cover the one region, and a sealing member filled in the groove, the sealing member closely adhered onto the second case to seal the one region, wherein a volumetric center of the sealing member is located more adjacent to a surface of the sealing member than to an inner side of the sealing member, such that the surface of the sealing member is formed earlier than the inner side of the sealing member to prevent or reduce formation of a weld line on the surface of the sealing member.

Abstract: Very thin flash modules for cameras are described that do not appear as a point source of light to the illuminated subject. Therefore, the flash is less objectionable to the subject. In one embodiment, the light emitting surface area is about 5 mm×10 mm. Low profile, side-emitting LEDs optically coupled to solid light guides enable the flash module to be thinner than 2 mm. The flash module may also be continuously energized for video recording. The module is particularly useful for cell phone cameras and other thin cameras.

Abstract: This disclosure provides systems, methods and apparatus for providing packaged microelectromechanical systems (MEMS) devices. In one aspect, package can include a cover glass joined to a device substrate, the cover glass including integrated electrical connectivity and configured to encapsulate one or more MEMS devices on the device substrate. The cover glass can include one or more spin-on glass layers and electrically conductive routing and interconnects. The package can include a narrow seal surrounding the one or more encapsulated MEMS devices.

Abstract: A semiconductor device includes a metal substrate, semiconductor elements, wires, a control terminal, a main electrode terminal, a control substrate, a cover, a sealing resin, a case, and an insulator. The metal substrate includes a metal plate, an insulating layer formed on the top surface of the metal plate, and electrode patterns provided on the insulating layer. The semiconductor elements are secured to different ones of the electrode patterns by solder. The sealing resin seals the components within the case, such as the semiconductor elements. The insulator covers a portion of the surface of the insulating layer and at least a portion of the edge of each electrode pattern.

Abstract: A printed wiring board includes a core substrate, an electronic component accommodated in the substrate, a first buildup layer laminated on first surface of the substrate and including the outermost interlayer resin insulation layer and the outermost conductive layer formed on the outermost interlayer resin insulation layer of the first buildup layer, and a second buildup layer laminated on second surface of the substrate and including the outermost interlayer resin insulation layer and the outermost conductive layer formed on the outermost interlayer resin insulation layer of the second buildup layer. The outermost interlayer resin insulation layer of the first buildup layer has thermal expansion coefficient which is set lower than thermal expansion coefficient of the outermost interlayer resin insulation layer of the second buildup layer.

Abstract: A semiconductor device package having a cavity formed using film-assisted molding techniques is provided. Through the use of such techniques the cavity can be formed in specific locations in the molded package, such as on top of a device die mounted on the package substrate or a lead frame. In order to overcome cavity wall angular limitations introduced by conformability issues associated with film-assisted molding, a gel reservoir feature is formed so that gel used to protect components in the cavity does not come in contact with a lid covering the cavity or the junction between the lid and the package attachment region. The gel reservoir is used in conjunction with a formed level setting feature that controls the height of gel in the cavity. Benefits include decreased volume of the cavity, thereby decreasing an amount of gel-fill needed and thus reducing production cost of the package.

Abstract: In various embodiments, a chip arrangement is provided. The chip arrangement may include a chip carrier and a chip mounted on the chip carrier. The chip may include at least two chip contacts and an insulating adhesive between the chip and the chip carrier to adhere the chip to the chip carrier. The at least two chip contacts may be electrically coupled to the chip carrier.

Abstract: A semiconductor device includes a die coupled to a substrate, a first memory device coupled to a surface of the die opposite the substrate and a coupling device coupled between the surface of the die opposite the substrate and a second memory device such that the second memory device at least partially overlaps the first memory device. Also disclosed is method of mounting first and second memory devices on a die in an at least partially overlapping manner.

Abstract: A method (70) of forming sensor packages (20) entails providing a sensor wafer (74) having sensors (30) formed on a side (26) positioned within areas (34) delineated by bonding perimeters (36), and providing a controller wafer (82) having control circuitry (42) at one side (38) and bonding perimeters (46) on an opposing side (40). The bonding perimeters (46) of the controller wafer (82) are bonded to corresponding bonding perimeters (36) of the sensor wafer (74) to form a stacked wafer structure (48) in which the control circuitry (42) faces outwardly. The controller wafer (82) is sawn to reveal bond pads (32) on the sensor wafer (74) which are wire bonded to corresponding bond pads (44) formed on the same side (38) of the wafer (82) as the control circuitry (42). The structure (48) is encapsulated in packaging material (62) and is singulated to produce the sensor packages (20).

Abstract: A semiconductor module arrangement includes a semiconductor module having a top side, an underside opposite the top side, and a plurality of electrical connection contacts formed at the top side. The semiconductor module arrangement additionally includes a printed circuit board, a heat sink having a mounting side, and one or a plurality of fixing elements for fixing the printed circuit board to the heat sink. Either a multiplicity of projections are formed at the underside of the semiconductor module and a multiplicity of receiving regions for receiving the projections are formed at the mounting side of the heat sink, or a multiplicity of projections are formed at the mounting side of the heat sink and a multiplicity of receiving regions for receiving the projections are formed at the underside of the semiconductor module. In any case, each of the projections extends into one of the receiving regions.

Abstract: A patterned adhesive layer including holes is employed to attach a coreless substrate layer to a stiffener. The patterned adhesive layer is confined to kerf regions, which are subsequently removed during singulation. Each hole in the patterned adhesive layer has an area that is greater than the area of a bottomside interconnect footprint of the coreless substrate. The patterned adhesive layer may include a permanent adhesive that is thermally curable or ultraviolet-curable. The composition of the stiffener can be tailored so that the thermal coefficient of expansion of the stiffener provides tensile stress to the coreless substrate layer at room temperature and at the bonding temperature. The tensile stress applied to the coreless substrate layer prevents or reduces warpage of the coreless substrate layer during bonding. Upon dicing, bonded stacks of a semiconductor chip and a coreless substrate can be provided without adhesive thereupon.

Abstract: Flip chip packages are described that include two or more thermal interface materials (TIMs). A die is mounted to a substrate by solder bumps. A first TIM is applied to the die, and has a first thermal resistance. A second TIM is applied to the die and/or the substrate, and has a second thermal resistance that is greater than the first thermal resistance. An open end of a heat spreader lid is mounted to the substrate such that the die is positioned in an enclosure formed by the heat spreader lid and substrate. The first TIM and the second TIM are each in contact with an inner surface of the heat spreader lid. A ring-shaped stiffener may surround the die and be connected between the substrate and heat spreader lid by the second TIM.

Abstract: A semiconductor package according to embodiments includes: a semiconductor chip including a front electrode on a front surface thereof and a back electrode on a back surface thereof; a front-side cap portion including an air gap in a portion between the semiconductor chip and the front-side cap portion and a front-side penetrating electrode, and is positioned to face the front surface of the semiconductor chip; a back-side cap portion bonded with a first cap portion to hermetically seal the semiconductor chip, includes an air gap at least in a portion between the semiconductor chip and the back-side cap portion and a back-side penetrating electrode, and is positioned to face the back surface of the semiconductor chip; a front-side connecting portion which electrically connects the front electrode and the front-side penetrating electrode; and a back-side connecting portion which electrically connects the back electrode and the back-side penetrating electrode.

Abstract: Embodiments of the present disclosure are directed towards a circuit board having integrated passive devices such as inductors, capacitors, resistors and associated techniques and configurations. In one embodiment, an apparatus includes a circuit board having a first surface and a second surface opposite to the first surface and a passive device integral to the circuit board, the passive device having an input terminal configured to couple with electrical power of a die, an output terminal electrically coupled with the input terminal, and electrical routing features disposed between the first surface and the second surface of the circuit board and coupled with the input terminal and the output terminal to route the electrical power between the input terminal and the output terminal, wherein the input terminal includes a surface configured to receive a solder ball connection of a package assembly including the die. Other embodiments may be described and/or claimed.

Abstract: A BioMEMS microelectromechanical apparatus and for fabricating the same is disclosed. A substrate is provided with at least one signal conduit formed on the substrate. A sacrificial layer of sacrificial material may be deposited on the signal conduit and optionally patterned to remove sacrificial material from outside the packaging covered area. A bonding layer may be deposited on at least a portion of the signal conduit and on the sacrificial layer when included. The bonding layer may be planarized and patterned to form one or more cap bonding pads and define a packaging covered area. A cap may be bonded on the cap bonding pad to define a capped area and so that the signal conduit extends from outside the capped area to inside the capped area. Additionally, a test material such as a fluid may be provided within the capped area.

Abstract: To enhance the reliability of connection between a semiconductor chip and a metal plate by ensuring sufficiently the thickness of a conductive material interposed between the semiconductor chip and the metal plate. A lead frame is arranged over a jig and a clip frame is arranged over protruding portions provided on the jig. In this state, a heating process (reflow) is performed. In this case, high melting point solders filling first spaces are melted in a state in which the first space is formed between a High-MOS chip and a High-MOS clip and the first space is formed between a Low-MOS chip and a Low-MOS clip. At this time, even when the high melting point solder is melted in the first space, the size (in particular, the height) of the first space does not change and the first space is maintained.

Abstract: Disclosed is a light-emitting diode package according to an embodiment, including; a body having a cavity formed therein, a lead frame placed in the cavity; and a light emitting diode electrically connected to the lead frame while having a slope angle relative to the bottom surface of the cavity, wherein a light emitting part and a non-light emitting part are present on the light emitting diode, and wherein a connection part is provided in a region of the cavity to be connected to at least a region of the non-light emitting part.

Abstract: There is provided a method of fabricating a semiconductor device, the method including: forming a semiconductor component portion at a first surface of a substrate; applying a grinding treatment to a second surface of the substrate that is opposite from the first surface to form a fracture surface; applying a fracture surface removal treatment to predetermined positions of the fracture surface of the second surface; and forming an electrode at the second surface.

Abstract: A semiconductor device includes a base plate having one main surface joined to an insulating substrate on which a semiconductor chip and the like are mounted and a transfer mold resin which is so provided as to cover the one main surface of the base plate, the insulating substrate, the semiconductor chip, and the like and expose the other main surface of the base plate. The coefficient of linear expansion of the base plate is lower than that of copper and the coefficient of linear expansion of the transfer mold resin is not higher than 16 ppm/° C. The transfer mold resin has such scooped shapes as to expose opposed short-side centers and the vicinity of the base plate, respectively. The base plate has mounting holes in portions exposed by the scooped shapes of the transfer mold resin.

Abstract: A stress shield for a plastic integrated circuit package is disclosed. A shield plate is attached by an adhesive to a top surface of an integrated circuit die such that the shield plate covers less than all of the top surface and leaves bond pads exposed. A molding material is applied over the shield plate and the integrated circuit die. The shield plate shields the integrated circuit die from stresses imparted by the molding material.

Abstract: Various packages and methods of forming packages are disclosed. In an embodiment, a package includes a hybrid encapsulant encapsulating a chip attached to a substrate. The hybrid encapsulant comprises a first molding compound and a second molding compound that has a different composition than the first molding compound. In another embodiment, a package includes an encapsulant encapsulating a chip attached to a substrate. A surface of the chip is exposed through the encapsulant. The encapsulant comprises a recess in a surface of a first molding compound proximate the surface of the chip. A thermal interface material is on the surface of the chip and in the recess, and a lid is attached to the thermal interface material.

Abstract: A package structure having an embedded semiconductor component, includes: a chip having an active surface with electrode pads and an inactive surface opposite to the active surface; a first insulating protection layer having a chip mounting area for the chip to be mounted thereon via the active surface thereof; a plurality of connection columns disposed in the first insulating protection layer at positions corresponding to the electrode pads and electrically connected to the electrode pads via solder bumps; an encapsulant formed on one surface of the first insulating protection layer having the chip mounted thereon for encapsulating the chip; and a built-up structure formed on the other surface of the first insulating protection layer and the connection columns. Due to the bending resistance of the encapuslant, the warpage of the built-up structure is prevented.

Abstract: A three dimensional package includes a substrate having a columnar part including a sidewall, and stairs or steps arranged along the sidewall of the columnar part in the form of multiple helixes twisted around the columnar part. Semiconductor integrated circuits (IC dies) are attached on one or both of the supporting surfaces of the stairs. The columnar part, the stairs and the IC dies can be encapsulated with a mold compound.

Abstract: A semiconductor power module includes at least two sub modules. The sub modules include at least one respective transistor having a collector, an emitter, and a gate. The module includes a connection arrangement having a collector terminal unit for connecting the collectors of the at least two sub modules collectively to external circuit components, at least two emitter terminal units for connecting the respective emitters of the at least two sub modules individually to external circuit components, and at least two gate terminal units for connecting the respective gates of the at least two sub modules individually to external circuit components.

Abstract: A light emitting diode (LED) package includes: a main body mounted on a substrate; a light emitting diode that is mounted in the main body and emits light; and a lead frame exposed to allow the main body to be selectively top-mounted or side-mounted. A backlight unit includes: a light guide plate configured to allow a light source to proceed to a liquid crystal panel; a light emitting diode (LED) mounted in a main body mounted on a substrate and generating a light source; and an LED package having a lead frame exposed to allow the main body to be selectively top-mounted or side-mounted, and being mounted on the light guide plate.

Abstract: A housing for a power semiconductor, providing a compartment for installation of a power semiconductor, and including a first and a second terminal. The terminals are for connection of a power semiconductor installed in the compartment, and for leading current to and from the compartment. The housing includes a contact mechanism for bypassing the compartment, the contact mechanism including at least one movable contact arranged for electrically connecting the first and second terminal, the at least one movable contact being movable between a disconnected first position and a connected second position. The contact mechanism further includes a bypass actuator arranged inside the compartment and provided for transforming a pressure from an exploding semiconductor into motion, the bypass actuator is operatively connected to the movable contact and arranged to move the movable contact from the first to the second position when subjected to the pressure of an exploding semiconductor.

Abstract: Disclosed is a light emitting device package. The light emitting device package includes a package body having a first cavity and a second cavity; a plurality of reflective frames comprising a first reflective frame and a second reflective frame on the first cavity and the second cavity, respectively, and each of the first reflective frame and the second reflective frame comprises a bottom frame and at least two side wall frames extending from the bottom frame; and a light emitting device on the first reflective frame, wherein the first reflective frame and the second reflective frame are electrically separated from each other.

Abstract: A semiconductor device includes a circuit pattern over a first surface of a substrate, an insulating interlayer covering the circuit pattern, a TSV structure filling a via hole through the insulating interlayer and the substrate, an insulation layer structure on an inner wall of the via hole and on a top surface of the insulating interlayer, a buffer layer on the TSV structure and the insulation layer structure, a conductive structure through the insulation layer structure and a portion of the insulating interlayer to be electrically connected to the circuit pattern, a contact pad onto a bottom of the TSV structure, and a protective layer structure on a second surface the substrate to surround the contact pad.

Abstract: A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure.

Abstract: An optical semiconductor apparatus includes a lid body bonded to an upper surface of a frame body, the lid body having an opening at a position vertically overlapping with an optical semiconductor device. The lid body has a first portion which is positioned to surround the opening and has an upper surface to which a light-transmissive member is bonded, a second portion which is positioned to surround the first portion, and a third portion which is positioned to surround the second portion and has a lower surface to which the frame body is bonded. The upper surface of the first portion is positioned lower than an upper surface of the third portion. The second portion has a thin-walled portion positioned to surround the first portion, the thin-walled portion having a thickness thinner than that of the first portion as well as thinner than that of the third portion.

Abstract: A surface-mountable electronic device free of leads has a plurality of solderable connection surfaces at its lower side, with at least one of the connection surfaces having a rectangular portion. The outline of this rectangular portion corresponds to a connection surface of the JEDEC Standard MO-236 or of any other standard according to which the respective connection surface should not extend directly up to a side edge of the lower device side. The at least one connection surface furthermore has an extension section which extends, starting from the rectangular portion, in the direction of a side edge of the lower side of the device.

Abstract: An integrated circuit package is provided with a thin-film battery electrically connected to and encapsulated with an integrated circuit die. The battery can be fabricated on a dedicated substrate, on the die pad, or on the integrated circuit die itself.

Abstract: A thin power device comprises a substrate having a first set of first contact pads at a front surface of the substrate electrically connecting to a second set of second contact pads at a back surface of the substrate, a through opening opened from the front surface and through the substrate exposing a third contact pad at the back surface of the substrate, a semiconductor chip embedded into the through opening with a back metal layer at a back surface of the semiconductor chip attached on the third contact pad, and a plurality of conductive structures electrically connecting electrodes at a front surface of the semiconductor chip with the corresponding first contact pads in the first sets of first contact pads.

Abstract: Provided is a semiconductor device and method of fabricating the semiconductor memory device. The semiconductor device may be formed by forming a first welding groove along outside edges of one case of a pair of upper and lower cases, forming a first welding protrusion along outside edges of the other case, the first welding protrusion being formed to correspond to the first welding groove and having a volume larger than a volume of the first welding groove. The method may further include inserting the first welding protrusion into the first welding groove to enclose a memory module in an inner accommodating space of the upper and lower cases, melting the first welding protrusion so that a first portion of the first welding protrusion fills the first welding groove and a second portion of the first welding protrusion fills a space between welding portions of the upper case and the lower case, and solidifying the first and second portions of the first welding protrusion.

Abstract: A stacked multi-chip packaging structure comprises a lead frame, a first semiconductor chip mounted on the lead frame, a second semiconductor chip flipped-chip mounted on the lead frame, a metal clip mounted on top of the first and second semiconductor chips and a third semiconductor chip stacked on the meal clip; bonding wires electrically connecting electrodes on the third semiconductor chip to the first and second semiconductor chips and the pins of the lead frame; plastic molding encapsulating the lead frame, the chips and the metal clip.

Abstract: A method to prevent movable structures within a MEMS device, and more specifically, in recesses having one or more dimension in the micrometer range or smaller (i.e., smaller than about 10 microns) from being inadvertently bonded to non-moving structures during a bonding process. The method includes surface preparation of silicon both structurally and chemically to aid in preventing moving structures from bonding to adjacent surfaces during bonding, including during high force, high temperature fusion bonding.

Abstract: An electronic component manufacturing method that efficiently grinds a cover layer provided on a substrate even when the substrate is warped includes the step of forming first grooves at intervals in a cover layer provided on a substrate by repeating grinding with a rotary blade at a pitch more than a thickness W of the rotary blade. Next, at least portions provided in the cover layer along the first grooves are removed to reduce the thickness of the cover layer by repeating grinding at a pitch equal to or less than the thickness W of the rotary blade.

Abstract: A semiconductor apparatus includes: a package substrate on which a semiconductor device is disposed; a mounting board over which the package substrate is mounted; a first restraint that penetrates through the mounting board and the package substrate, and restrains deformation of the mounting board and the package substrate in a direction in which the mounting board and the package substrate are separated from each other; and a second restraint that is disposed between the mounting board and the package substrate, and restrains deformation of the mounting board and the package substrate in a direction in which the mounting board and the package substrate are closer to each other.

Abstract: A packaged device includes a first die, a second die, and specially spaced and positioned sets of package terminals. The first die includes a pulse-width modulator (PWM), a processor, a timer, high-side drivers, low-side drivers, and a fault protection circuit. The second die includes ultra-high voltage high-side drivers. In an ultra-high voltage application, the PWM and external circuitry together form a switching power supply that generates a high voltage. The high voltage powers external high-side transistors. The processor and timer control the ultra-high voltage high-side drivers, that in turn supply drive signals to the external high-side transistors through the package terminals. External low-side transistors are driven directly by low-side drivers of the first die. If the fault protection circuit detects an excessive current, then the fault protection circuit supplies a disable signal to high-side and low-side drivers of both dice.

Abstract: A method for fabricating a packaging structure having an embedded semiconductor element includes: providing a substrate having opposite first and second surfaces and at least an opening penetrating the first and second surfaces; forming a first metallic frame around the periphery of the opening on the first surface; forming at least an opening inside the first metallic frame by laser ablation; disposing a semiconductor chip in the opening; forming a first dielectric layer on the first and second surfaces and the chip; forming a first wiring layer on the first dielectric layer of the first surface; and forming a first built-up structure on the first dielectric layer and the first wiring layer of the first surface. A shape of the opening is precisely controlled through the first metallic frame around the periphery of the predefined opening region, thereby allowing the chip to be precisely embedded in the substrate.