Abstract: A semiconductor module includes a printed circuit board including an integrated circuit chip, connecting terminals at an edge of the printed circuit board, and signal lines respectively connecting electrical connection pads of the integrated circuit chip to the connecting terminals. The connecting terminals are plated using via-holes of the printed circuit board respectively connected to the signal lines.

Abstract: A thin film lithium-ion battery unit includes a positive current collecting substrate, a positive electrode active material layer on an inner surface of the positive current collecting substrate, a negative current collecting substrate, a negative electrode active material layer on an inner surface of the negative current collecting substrate, a separator between the positive electrode active material layer and the negative electrode active material layer, and electrolyte retained at least in the separator. The positive electrode active material layer, the separator and the negative electrode active material layer constitute a laminated electric core. An outer conductive frame is spaced apart from the positive current collecting substrate and encompasses the positive current collecting substrate.

Abstract: A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region. The chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region. The opening has a first dimension (d1) measured along the long axis and a second dimension (d2) measured along the short axis. In an embodiment, L is greater than d1, and W is less than d2.

Abstract: A semiconductor package may include a first semiconductor chip having a plurality of first bonding pads arranged at a first pitch on a first active surface. The semiconductor package may include one or more reconfigurable package units each including a second semiconductor chip having a plurality of second bonding pads arranged at a second pitch on a second active surface; a semiconductor chip connector arranged spaced apart from the second semiconductor chip and having a plurality of through vias arranged at the first pitch; a molding layer surrounding side surfaces of the second semiconductor chip and the semiconductor chip connector; and redistribution lines formed over the second semiconductor chip, the semiconductor chip connector, and the molding layer.

Abstract: Devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a device includes a first interconnect structure, a first integrated circuit die coupled to the first interconnect structure, and a second integrated circuit die disposed over and coupled to the first integrated circuit die. A second interconnect structure is disposed over the second integrated circuit die. First through-vias are coupled between the first interconnect structure and the second interconnect structure, and second through-vias are coupled between the first integrated circuit die and the second interconnect structure. A molding material is disposed around the first integrated circuit die, the second integrated circuit die, the plurality of first through-vias, and the plurality of second through-vias.

Abstract: A semiconductor package may include a first semiconductor die, external connectors, second semiconductor dies, a mold layer, an outer packaging part, and a terrace-like edge. The external connectors may be disposed over a first surface of the first semiconductor die. The second semiconductor dies may be stacked over a second surface of the first semiconductor die. The mold layer may cover sidewalls of the second semiconductor dies. The outer packaging part may have a groove in which a stack structure of the first and second semiconductor dies are accommodated. The terrace-like edge may be disposed under an edge of the mold layer to expose a sidewall of the first semiconductor die. A portion of an outer sidewall of the mold layer may be in contact with a portion of an inner surface of the outer packaging part, and the inner surface of the outer packaging part may be spaced apart from the sidewall of the first semiconductor die by the terrace-like edge.

Abstract: A semiconductor device includes a chip carrier and a semiconductor die with a semiconductor portion and a conductive structure. A soldered layer mechanically and electrically connects the chip carrier and the conductive structure at a soldering side of the semiconductor die. At the soldering side an outermost surface portion along an edge of the semiconductor die has a greater distance to the chip carrier than a central surface portion. The conductive structure covers the central surface portion and at least a section of an intermediate surface portion tilted to the central surface portion. Solder material is effectively prevented from coating such semiconductor surfaces that are prone to damages and solder-induced contamination is significantly reduced.

Abstract: A flexible display motherboard is disclosed. The motherboard includes a first group of flexible display units, where the first group includes at least one flexible display unit. The motherboard also includes a second group of flexible display units, where the second group includes at least one flexible display unit. The motherboard also includes one or more first grooves between the first and second groups.

Abstract: A semiconductor device includes an external lead-out terminal having an external terminal and an internal terminal connected to a connecting portion of the external terminal. By forming a resin fixed portion linked to a horizontal resin portion in the vicinity of a leading end of the internal terminal, a gap under the internal terminal when cutting the terminal coupling portion off from the internal terminal can be restricted.

Abstract: An array of housings with housing bodies and lenses is molded, or an array of housing bodies is molded and bonded with lenses to form an array of housings with housing bodies and lenses. Light-emitting diodes (LEDs) are attached to the housings in the array. An array of metal pads may be bonded to the back of the array or insert molded with the housing array to form bond pads on the back of the housings. The array is singulated to form individual LED modules.

Abstract: The invention relates to a method for producing an optical module, comprising the following steps: a) providing a chip having an optical element integrated in the chip, wherein the optical element bas a first electrode and a second electrode, and wherein the chip has a first connection contact for the first electrode and a second connection contact for the second electrode, such that an operating voltage for the optical element can be applied between the first connection contact and the second connection contact, and wherein the chip has an optically active side, which is designed to emit and/or to receive radiation; b) connecting the chip to a film, such that the film completely covers the optically active side of the chip, wherein the film is a film made from acrylate, polyarylate, or polyurethane, wherein the film, at least in the region located above the optically active side, is transparent to radiation which.

Abstract: A touch screen panel Active Matrix Organic Light Emitting Diode (AMOLED) display device for decreasing the thickness of a mobile terminal and improving a degree of freedom in design is provided. The touch screen panel AMOLED display device includes a flexible AMOLED disposed on the bottom of a window, and a Chip-On-Film (COF) film connected to the flexible AMOLED and coupled with a flexible AMOLED driver Integrated Circuit (IC). Therefore, the thickness of the touch screen panel AMOLED display device may be decreased, and damage of the AMOLED due to an external shock may be prevented. Additionally, separation of the flexible AMOLED driver IC from a mounting surface may be prevented.

Abstract: A method for manufacturing a semiconductor module includes the step of soldering two or more semiconductor elements having substrate materials and heights different from each other to a metal foil disposed at one side of an insulating substrate; connecting a plurality of wiring members, not interconnecting the semiconductor elements, to front face electrodes of the semiconductor elements through solder so that heights from a surface of the insulating substrate to top faces of the wiring members become same level with each other; inspecting a leakage current while applying electricity on each one of semiconductor elements individually through the wiring members; and connecting the top faces of the wiring members with a bus bar.

Abstract: Several embodiments of microelectronic configurations with logic components and associated methods of manufacturing are disclosed herein. In one embodiment, the configuration includes a substrate with a recess, a first die carried by the substrate wherein the die substantially covers the recess, and a logic component carried by the die in a location exposed by the recess. The logic component can be substantially coplanar with the substrate. The die is electrically connected to a terminal on a one side of the substrate, and the logic component is electrically connected to a terminal on an opposite side of the substrate.

Abstract: Techniques for constructing an electronic module are provided herein. For example, the techniques include orienting at least one die having a top side (e.g., a first side), a bottom side (e.g., a second side) and one or more side walls, on a substrate with the top side of the die proximate the substrate, coating the bottom side and each of the side walls of the die with a stress buffer material, forming a reconstructed wafer by encapsulating the coated die within a mold compound, and removing the substrate to expose the top side of the die.

Abstract: An integrated circuit test device includes a carrying base with a probe station installed thereon, a clamping and positioning mechanism and a cover plate. The clamping and positioning mechanism includes a lower base, an elastic piece, an upper base and a pair of elastic arms. The lower base is arranged corresponding to the probe station. The elastic piece is elastically clamped between the probe station and the lower base. The upper base is stacked on the lower case and disposed with a chip socket. The pair of elastic arms is movably arranged in the chip socket. The cover plate is fixed to the carrying base. The cover plate is disposed with an opening corresponding to the chip socket. A sliding structure (A) is disposed between the pair of elastic arms and the cover plate for enabling the pair of elastic arms to clamp and fix the integrated circuit.

Abstract: The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method.

Abstract: A semiconductor device includes a semiconductor element, a substrate, a lead, and a sealing resin member. The semiconductor element has a first electrode and a second electrode located on opposite sides in the thickness direction. The substrate has an insulating base and a conductive plate. The base has first and second surfaces located on opposite sides in the thickness direction. The conductive plate is bonded to the first surface of the base and electrically connected to the second electrode of the semiconductor element. The lead has an island electrically connected to the first electrode. The sealing resin member covers at least the semiconductor element.

Abstract: A wiring board includes a core substrate including an insulating layer and a conductor layer formed on the insulating layer, and a build-up layer laminated on the substrate and including an inter-layer insulating layer and a conductor layer laminated on the inter-layer. The substrate has opening penetrating through the insulating layer such that surface of the conductor layer in the substrate is forming bottom of the opening, the substrate has a via conductor formed in the opening and including plating filling the opening, the conductor layer in the substrate includes a metal foil, the conductor layer in the build-up layer includes a metal foil, and the metal foil in the substrate has surface in contact with the surface of the insulating layer such that the surface of the metal foil in the substrate has surface roughness smaller than surface roughness of surface of the metal foil in the build-up layer.

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a semiconductor die. A first molding compound covers a back surface of the semiconductor die. A redistribution layer (RDL) structure is disposed on a front surface of the semiconductor die. The semiconductor die is coupled to the RDL structure. A second molding compound is disposed on the front surface of the semiconductor die and embedded in the RDL structure. A passive device is disposed on the second molding compound and coupled to the semiconductor die.

Abstract: A starting logical lane of a logical bus is set to the first or last physical lane of a physical bus. A width of a logical bus is set to half the number of physical lanes. If a fault is absent in the logical bus, the starting logical lane is set to the other of the first and last physical lanes. The width is repeatingly divided by two until it is equal to one lane or the fault is not present in the logical bus. When the fault is absent in the logical bus and the width is greater than one lane, the fault is present within a range of the physical lanes encompassing a contiguous number of the physical lanes and the first or last physical lane.

Abstract: A power electronic package includes a first substrate, a second substrate oppositely disposed from the first substrate, one or more chips disposed between the substrates, and at least three spacers. The spacers control a height variation of the power electronic package and protect the chips and other electronics from experiencing excessive stress. The height of the spacers is determined based on a height of the chips, on a height of solder blocks that connect the chips to the top substrate, and on a height of solder blocks that connect the chips to the bottom substrate.

Abstract: An HVAC Controller may include a first sub-assembly and a second sub-assembly releasably engageble with the first sub-assembly. The first sub-assembly may include a first housing and a printed circuit board capable of being secured relative to the first housing and capable of providing one or more signals. The second sub-assembly may include a second housing and a second printed circuit board capable of being secured relative to the second housing and capable of receiving the one or more signals from the first printed circuit boards when the first sub-assembly is releasably engaging the second sub-assembly. The first printed circuit board and the second printed circuit board each may have one or more component mounted on sides facing one another, the components each extending a distance. The sum of the distances may be greater than a distance spacing the facing sides of the printed circuit boards.

Abstract: A lighting device comprises a solid state light emitter on a circuit board, and an optic held in place relative to the first circuit board, a voltage drop across the emitter at least 60 volts. A lighting device comprises a solid state light emitter on a first circuit board, an optic held in place relative to the first circuit board, and a non-isolated power supply. A lighting device comprises a solid state light emitter on a first circuit board, and a flame-rated optic held in place relative to the first circuit board. An optic, comprising a translucent region, a first dimension not larger than about 10 mm, a second dimension not larger than 15 mm. A flame-rated optic comprising a translucent region, structure configured to hold the optic in place relative to a circuit board. Methods of making lighting devices.

Abstract: An exemplary embodiment of the described technology relates generally to a display apparatus including a plurality of pixels and corresponding to one area of a substrate for displaying an image, and a pad area corresponding to another area of the substrate, the pad area including a lower electrode configured to transmit an electric signal to the pixels, and a plurality of pad electrodes electrically connecting the lower electrode and a driving chip, wherein each of the pad electrodes includes a first contact surface for contacting the lower electrode, a second contact surface for contacting the driving chip, and an oxide layer on a surface of the pad electrode that is exposed to the outside, and that connects the first contact surface and the second contact surface.

Abstract: Disclosed are embodiments of a glass core substrate for an integrated circuit (IC) device. The glass core substrate includes a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.

Abstract: An physical quantity sensor includes a substrate, a piezoelectric resistive element that is disposed on one surface side of the substrate, a wall portion that is disposed on the one surface side of the substrate so as to surround the piezoelectric resistive element in a plan view of the substrate, and a ceiling portion that is disposed on an opposite side to the substrate with respect to the wall portion and forms a cavity along with the wall portion, in which the wall portion includes an insulating layer, and wiring layers that surround the insulating layer together and have higher resistance to an etchant which can etch the insulating layer than resistance of the insulating layer.

Abstract: Aspects of the present disclosure describe MOSFET devices that have snubber circuits. The snubber circuits comprise one or more resistors with a dynamically controllable resistance that is controlled by changes to a gate and/or drain potentials of the one or more MOSFET structures during switching events.

Abstract: A power module providing an improved manufacture yield and having an ensured stable joint strength and accordingly improved reliability is provided. The power module includes: a base portion having one surface on which an electrode portion is formed; a conductor portion disposed to face the one surface of the base portion on which the electrode portion is formed, for making electrical connection with the outside; and an interconnect portion connected to the electrode portion formed on the one surface of the base portion and to the surface of the conductor portion facing the one surface of the base portion for electrically connecting the electrode portion to the conductor portion.

Abstract: Provided is a heat dissipation device. The heat dissipation device includes a thermal conductive plate (1), a shape of which is the same as a shape of a Secure Digital (SD) card. The thermal conductive plate (1) is used to be inserted into an SD card connector, and partially contacts with at least one inner surface of the SD card connector; the thermal conductive plate (1) is made of thermal conductive metallic material, and one or more contacting parts (10) of the thermal conductive plate (1) that contact with the SD card connector are set to be thermal conductive metallic material, and outer surfaces (12), other than the one or more contacting parts (10), of the thermal conductive plate (1) are set to be insulating material. The present technical solution solves the problem that the implementing effect of heat dissipation schemes already existed for terminals is fairly bad in the related technologies, and improves heat conduction and heat dissipation speed.

Abstract: A package includes a first package component having a top surface, a second package component bonded to the top surface of the first package component, and a plurality of electrical connectors at the top surface of the first package component. A molding material is over the first package component and molding the second package component therein. The molding material includes a first portion overlapping the second package component, wherein the first portion includes a first top surface, and a second portion encircling the first portion and molding bottom portions of the plurality of electrical connectors therein. The second portion has a second top surface lower than the first top surface.

Abstract: A semiconductor device is provided that is inexpensively manufactured with variation in high-frequency characteristics suppressed. Internal matching circuit boards are disposed on at least one signal transmission path of an input-side signal transmission path between an input terminal and a semiconductor element and an output-side signal transmission path between the semiconductor element and an output terminal and is provided for matching at least between output impedance of an external circuit connected to the input terminal and input impedance of the semiconductor device or between input impedance of an external circuit connected to the output terminal and output impedance of the semiconductor device, and components are electrically connected by at least one wire causing a change exceeding an allowable value in high-frequency characteristics of the semiconductor device due to a change in wire length and are disposed in contact with each other inside a package.

Abstract: A sensor device and an electronic apparatus by which downsizing and a reduction in costs can be achieved is provided. A sensor device according to an embodiment of the present technology includes a sensor element and a semiconductor element. The semiconductor element includes a first surface, a second surface, and a via-hole. The first surface includes a first terminal on which the sensor element is mounted and is an inactive surface. The second surface includes a second terminal for external connection and is an active surface. The via-hole electrically connects the first surface and the second surface to each other.

Abstract: One aspect of this disclosure is a power amplifier module that includes a power amplifier; a wire bond pad electrically connected to the power amplifier, the wire bond pad including a nickel layer having a thickness that is less than 0.5 um, a palladium layer over the nickel layer, and a gold layer over the palladium layer; and a conductive trace having a top surface with a plated portion and an unplated portion surrounding the plated portion, the wire bond pad being disposed over the plated portion. Other embodiments of the module are provided along with related methods and components thereof.

Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a semiconductor die has a back side and a front side opposite the back side. The back side has a semiconductor substrate and the front side has components formed over the semiconductor substrate in front side layers. A backside layer is formed over the backside of the semiconductor die to resist warpage of the die when the die is heated and a plurality of contacts are formed on the front side of the die to attach to a substrate.

Abstract: An wiring board of the present invention includes an insulating board, a pair of signal external connection pads, a pair of ground external connection pads, a pair of signal through-hole conductors, a pair of around through-hole conductors, a core ground conductor layer having an opening, a via-hole conductor, a strip-shaped wiring conductor, an upper-side signal connection conductor, and a lower-side signal connection conductor, in which the pair of the ground through-hole conductors is arranged across the opening from each other.

Abstract: An embodiment device includes a first die, a second die electrically connected to the first die, and a heat dissipation surface on a surface of the second die. The device further includes a package substrate electrically connected to the first die. The package substrate includes a through-hole, and the second die is at least partially disposed in the through hole.

Abstract: A chip structure for mounting on a clearance area of a printed circuit board includes a packaged chip and a monopole coupling antenna. The packaged chip has an insulating body, an electronic component embedded in the insulating body, and a plurality of grounding pads electrically connected to the electronic component. The monopole coupling antenna has a grounding radiating metal and a monopole radiating metal. The packaged chip is electrically connected to the grounding radiating metal by the grounding pads. The monopole radiating metal is disposed on the insulating body and spaced apart from the electronic component and the grounding radiating metal. The monopole radiating metal is configured to couple the grounding radiating metal and the electronic component by using a feeding circuit to connect the packaged chip and the monopole radiating metal and using a grounding circuit to connect the grounding radiating metal and the printed circuit board.

Abstract: Disclosed herein are a semiconductor package and a method of manufacturing the same, which allows a conductive path to be provided to connect upper and lower portions of the semiconductor package. A semiconductor package according to the present invention includes a semiconductor chip, a substrate including an accommodating portion to accommodate the semiconductor chip, a sealing material configured to mold the semiconductor chip and the substrate to be integrated, a through wiring configured to vertically pass through the substrate, a wiring portion configured to electrically connect the semiconductor chip and one side of the through wiring, and an external connection portion to electrically connected to the other side of the through wiring and configured to be able to be electrically connected to an outside, wherein a wiring layer of the wiring portion is provided to be connected to the through wiring.

Abstract: The present invention relates to a method for manufacturing a TAB tap. The method includes forming a circuit pattern region having input/output terminal pattern on a base film, and forming an exposing region at a convey region having a sprocket hole for exposing the base film. Accordingly, the present invention provides a TAB tape that improves reliability of a product by fundamentally preventing the generation of metal particles by forming exposing regions that expose a base film through selectively etching and removing a metal layer of a convey region formed at both side of a TAB tape and having a sprocket hole, and that prevents short-circuit by partially removing a base film at a predetermined region not having a circuit pattern formed thereon through etching.

Abstract: Methods and apparatus for thinner package on package (“PoP”) structures. A structure includes a first integrated circuit package including at least one integrated circuit device mounted on a first substrate and a plurality of package on package connectors extending from a bottom surface; and a second integrated circuit package including at least another integrated circuit device mounted on a second substrate and a plurality of lands on an upper surface coupled to the plurality of package on package connectors, and a plurality of external connectors extending from a bottom surface; wherein at least the second substrate is formed of a plurality of layers of laminated dielectric and conductors. In another embodiment a cavity is formed on the bottom surface of the first substrate and a portion of the another integrated circuit extends partially into the cavity. Methods for making the PoP structures are disclosed.

Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.

Abstract: A system and method of manufacture of an integrated circuit device system includes: a module interposer having a module first side and a module second side; an outer chip assembly mounted to the module first side; a mirrored chip assembly mounted to the module second side, the mirrored chip assembly below the outer chip assembly; and a carrier attached to the module second side, the carrier includes a carrier first side and a carrier second side, the mirrored chip assembly suspended above the carrier first side.

Abstract: Methods for covalently and indelibly anchoring a polyacrylate polymer using a UV-induced polymerization process in the presence of a photoinitiator to an oxide surface are disclosed herein. The methods and compositions prepared by the methods can be used as indelible marking materials for use on microelectronic packages and as solder and sealant barriers to prevent overspreading of liquids on the oxide surfaces of microelectronic packages. The polyacrylate polymers are covalently linked to the oxide surface by use during the printing and UV-curing process of an adhesion promoter having as a first domain an oxide-reactive silyl group, bonded via a linker to an acrylate-reactive group.

Abstract: A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar.

Abstract: Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a first package having a first package substrate mounted with a lower semiconductor chip, and a second package having a second package substrate mounted with upper semiconductor chips. The second package substrate includes a chip region on which the upper semiconductor chips are mounted, and a connection region provided therearound. The chip region includes a first surface defining a first recess region and a second surface defining a first protruding portion. The upper semiconductor chips are mounted on opposite edges of the second surface and spaced apart from each other to have portions protruding toward the connection region beyond the chip region.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type having a chip region enclosed by a seal ring region. An insulating layer is on the semiconductor substrate. A seal ring structure is embedded in the insulating layer corresponding to the seal ring region. And, a plurality of doping regions are located beneath the first seal ring structure.

Abstract: A bonding material stack for wafer-to-wafer bonding is provided. The bonding material stack may include a plurality of layers each including boron and nitrogen. In one embodiment, the plurality of layers may include: a first boron oxynitride layer for adhering to a wafer; a boron nitride layer over the first boron oxynitride layer; a second boron oxynitride layer over the boron nitride layer; and a silicon-containing boron oxynitride layer over the second boron oxynitride layer.

Abstract: An electronic device has a package and a piezoelectric element accommodated in an accommodating space formed inside the package. The package has a frame-like metallization layer bonding a base substrate and a lid together and electrodes formed on and in the base substrate and electrically connected with the piezoelectric element. The metallization layer is insulated from the electrodes.

Abstract: A semiconductor arrangement includes upper and lower contact plates and basic chip assemblies. Each chip assembly has a semiconductor chip having a semiconductor body with upper and lower spaced apart sides. An individual upper main electrode and an individual control electrode are arranged on the upper side. The chip assemblies have either respectively a separate lower main electrode arranged on the lower side of the semiconductor chip of the corresponding basic chip assembly, or a common lower main electrode, which for each of the chip assemblies is arranged on the lower side of the semiconductor body of that chip assembly. An electrical current between the individual upper main electrode and the individual or common lower main electrode is controllable by its control electrode. The chip assemblies are connected to one another with a material bonded connection by a dielectric embedding compound, forming a solid assembly.