Abstract: A system is provided for protecting a signal within an electronic device. Such a system includes a connector and a printed circuit. The connector has a generally rectangular parallelepiped shape and includes: at its base, at least one solder termination corresponding to a contact region conveying the signal to be protected; and a slot for inserting a printed circuit. The printed circuit is housed in the insertion slot and shaped so that it covers the solder termination.

Abstract: A semiconductor device is made by mounting a semiconductor wafer to a temporary carrier. A plurality of TSV is formed through the wafer. A cavity is formed partially through the wafer. A first semiconductor die is mounted to a second semiconductor die. The first and second die are mounted to the wafer such that the first die is disposed over the wafer and electrically connected to the TSV and the second die is disposed within the cavity. An encapsulant is deposited over the wafer and first and second die. A portion of the encapsulant is removed to expose a first surface of the first die. A portion of the wafer is removed to expose the TSV and a surface of the second die. The remaining portion of the wafer operates as a TSV interposer for the first and second die. An interconnect structure is formed over the TSV interposer.

Abstract: A wiring substrate includes a substrate, a first insulating layer formed on the substrate, wiring patterns formed on a first surface of the first insulating layer, and a second insulating layer formed on the first surface of the first insulating layer. The second insulating layer covers the wiring patterns and includes a first opening that partially exposes adjacent wiring patterns as a pad. A projection is formed in an outer portion of the substrate located outward from where the first opening is arranged. The projection rises in a thickness direction of the substrate.

Abstract: A semiconductor device is made by mounting a prefabricated heat spreader frame over a temporary substrate. The heat spreader frame includes vertical bodies over a flat plate. A semiconductor die is mounted to the heat spreader frame for thermal dissipation. An encapsulant is deposited around the vertical bodies and semiconductor die while leaving contact pads on the semiconductor die exposed. The encapsulant can be deposited using a wafer level direct/top gate molding process or wafer level film assist molding process. An interconnect structure is formed over the semiconductor die. The interconnect structure includes a first conductive layer formed over the semiconductor die, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the first conductive layer and insulating layer. The temporary substrate is removed, dicing tape is applied to the heat spreader frame, and the semiconductor die is singulated.

Abstract: A stacked semiconductor package includes a first semiconductor chip having a first surface and a second surface which faces away from the first surface and including first bonding pads which are formed on the first surface and first through electrodes which pass through the first surface and the second surface; a second semiconductor chip stacked over the second surface of the first semiconductor chip, and including second bonding pads which are formed on a third surface facing the first semiconductor chip and second through electrodes which pass through the third surface and a fourth surface facing away from the third surface and are electrically connected with the first through electrodes; and a molding part formed to substantially cover the stacked first and second semiconductor chips and having openings which expose one end of the first through electrodes disposed on the first surface of the first semiconductor chip.

Abstract: A semiconductor substrate capable of detecting operating current of a MOSFET and diode current in a miniaturized MOSFET such as a trench-gate type MOSFET is provided. A semiconductor substrate includes a main current region and a current sensing region in which current smaller than main current flowing in the main current region flows. The main current region has a source electrode disposed on a main surface, the source electrode being in contact with a p-type semiconductor region (body) and an n+-type semiconductor region (source), and the current sensing region has a MOSFET current detecting electrode and a diode current detecting electrode on a main surface, the MOSFET current detecting electrode being in contact with the p-type semiconductor region (body) and the n+-type semiconductor region (source), the diode current detecting electrode being in contact with the p-type semiconductor region (body).

Abstract: An inductor design on a wafer level package (WLP) does not need to depopulate the solder balls on the die because the solder balls form part of the inductor. One terminal on the inductor couples to the die, the other terminal couples to a single solder ball on the die, and the remaining solder balls that mechanically contact the inductor remain electrically floating. The resulting device has better inductance, direct current (DC) resistance, board-level reliability (BLR), and quality factor (Q).

Abstract: A method for manufacturing a chip package is provided, the method including: forming a layer arrangement over a carrier; arranging a chip including one or more contact pads over the layer arrangement wherein the chip covers at least part of the layer arrangement; and selectively removing one or more portions of the layer arrangement and using the chip as a mask such that at least part of the layer arrangement covered by the chip is not removed.

Abstract: Apparatus and methods for an electronic package incorporating shielding against emissions of electromagnetic interference (EMI). According to an integrated circuit structure, a substrate is on a printed circuit board. An integrated circuit chip is on the substrate. The integrated circuit chip is electrically connected to the substrate. An EMI shielding unit is on the integrated circuit chip and the substrate. The EMI shielding unit comprises a lid covering the integrated circuit chip and portions of the substrate outside the integrated circuit chip. A fill material can be deposited within a cavity formed between the lid and the substrate. The fill material comprises an EMI absorbing material. A periphery of the lid comprises a side skirt, the side skirt circumscribing the integrated circuit chip and the substrate. EMI absorbing material is on the printed circuit board, and a portion of the side skirt is embedded in the EMI absorbing material.

Abstract: A package substrate (or printed circuit board) that includes at least one dielectric layer, a first inductor structure is at least partially located in the dielectric layer, a third interconnect, and a second inductor structure. The first inductor structure includes a first interconnect, a first via coupled to the first interconnect, and a second interconnect coupled to the first via. The third interconnect is coupled to the first inductor structure. The third interconnect is configured to provide an electrical path for a ground signal. The second inductor structure is at least partially located in the dielectric layer. The second inductor is coupled to the third interconnect. The second inductor structure includes a fourth interconnect, a second via coupled to the fourth interconnect, and a fifth interconnect coupled to the second via. The first and second inductor structures are configured to operate with a capacitor as a 3rd harmonic suppression filter.

Abstract: A wireless communication system has a first communication apparatus and a second communication apparatus. The first communication apparatus has an information generator to generate first information associated with a mobile terminal, an encoder to encode the first information, and a first wireless communication module to transmit the encoded first information to the mobile terminal by close range wireless communication. The second communication apparatus has a second wireless communication module to receive the encoded first information transmitted by the mobile terminal and second information, a decoder to decode the encoded first information, a verification module to verify validity of the first information, and an information processing module to process the second information received by the second wireless communication module when the validity is confirmed by the verification module.

Abstract: A power module includes a first substrate, at least two power elements, at least one conductive structure and at least one leadframe. The first substrate includes a first dielectric layer and two first metal layers. The first dielectric layer has at least two concavities and two opposite surfaces, the two first metal layers are respectively disposed on the two surfaces, and the two concavities are respectively formed on the two surfaces. The two power elements are respectively embedded in the two concavities of the first dielectric layer. The two power elements are electrically connected to each other through the conductive structure. The leadframe disposed at the first substrate is electrically connected to the two power elements, and is partially extended outside the first substrate.

Abstract: Various embodiments include wafer level chip scale package (WLCSP) structures and methods of tuning such structures. In some embodiments, the WLCSP structure includes: a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the PCB ground plane; a signal ball contacting the signal PCB trace connection; a chip pad contacting the signal ball, and a signal trace connection on a chip contacting the chip pad.

Abstract: A lightweight radio/CD player for vehicular application is virtually “fastenerless” and includes a case and frontal interface formed of polymer based material that is molded to provide details to accept audio devices such as playback mechanisms (if desired) and radio receivers, as well as the circuit boards required for electrical control and display. The case and frontal interface are of composite structure, including an insert molded electrically conductive wire mesh screen that has been pre-formed to contour with the molding operation. The wire mesh provides EMC, RFI, BCI and ESD shielding and grounding of the circuit boards via exposed wire mesh pads and adjacent ground clips. The PCB architecture integrally forms a resilient beam portion adjacent an edge thereof carrying a grounding pad. The major components and subassemblies are self-fixturing during the final assembly process and self-interconnect by integral guide and connection features effecting “slide lock” and “snap lock” self-interconnection.

Abstract: Provided is an organic EL element, wherein the thickness of the organic EL element can be made small and the width of a seal can be made narrower, and change in light-emitting quality over time can be inhibited. The organic EL element (1) is configured to be provided with: a second electrode (13) provided so as to cover an organic compound layer (12); an inorganic insulation film (15) formed within a prescribed area within a non light-emitting area of a first electrode (11), and formed between the first electrode (11) and the second electrode (13); an inorganic film (14) provided so as to cover the second electrode (13); a sealing resin layer (3) provided so as to cover the inorganic film (14); and a sealing base material (4) provided upon the sealing resin layer (3).

Abstract: A semiconductor light-emitting device (101) includes an LED chip (4), a lead (1) having a main surface (11) on which the LED chip (4) is mounted, and a resin package (5) covering the LED chip (4). The main surface (11) is roughened, and the main surface (11) is held in contact with the resin package (5). These configurations contribute to the downsizing of the semiconductor light-emitting device (101).

Abstract: A vertical probe card includes a bottom substrate, a top substrate, an interposer, a first set of electrically conductive polymer contacts, a second set of electrically conductive polymer contacts, a first anisotropic conductive film, and a second anisotropic conductive film. The interposer is disposed between the bottom substrate and the top substrate. The first set of electrically conductive polymer contacts is disposed on the surface of the bottom substrate opposite to the interposer. The second set of electrically conductive polymer contacts is disposed on the surface of the top substrate opposite to the interposer. The first set of electrically conductive polymer contacts are arranged differently from the second set of electrically conductive polymer contacts. The first anisotropic conductive film is disposed between the bottom substrate and the interposer, and configured to electrically connect the bottom substrate and the interposer.

Abstract: A package for mounting a light emitting device thereon. The package includes a substrate, a light emitting device mounting part including a wiring formed on one surface of the substrate, the wiring including two areas that are arranged facing each other and being separated a predetermined interval apart from each other in a plan view, first and second through-wirings that penetrate the substrate and are provided on the two areas, respectively, each of the first and second through-wirings including one end electrically connected to the light emitting device mounting part and another end exposed from another surface of the substrate. A part of each of the first and second through-wirings includes a maximum part having a plan-view shape that is larger than a plan-view shape of the one end of each of the first and second through-wirings.

Abstract: A method of forming a three-dimensional (3D) chip is provided in which a second chip is present embedded within a first chip. In one embodiment, the method includes forming a first chip including first electrical devices and forming a recess extending from a surface of the first chip. A second chip is formed having second electrical devices. The second chip is then encapsulated within the recess of the first chip. Interconnects are then formed through the first chip into electrical communication with at least one of the second devices on the second chip. A three-dimensional (3D) chip is also provided in which a second chip is embedded within a first chip.

Abstract: A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.

Abstract: A multilayer semiconductor structure having a layout footprint with a first region and a non-overlapping second region and different transistor types fabricated using different channel material. The semiconductor structure comprises a first transistor layer comprising a first type of channel material in the first region but no channel material in the second region. The semiconductor structure further comprises a second transistor layer comprising a second type of channel material in the second region but no channel material in the first region. The second transistor layer is vertically elevated above the first transistor layer. A first transistor is fabricated on the first transistor layer. A second transistor is fabricated on the second transistor layer, and the first transistor is interconnected with the second transistor to form a circuit.

Abstract: A packaged semiconductor device is assembled using a first lead frame upon which a die is mounted and encapsulated and a second lead frame that provides bent leads for the device. By using two different lead frames, an array of the first lead frames can be configured with more lead frames for more devices than a comparably sized lead frame array of the prior art because the first lead frame array does not need to provide the leads for the packaged devices. Instead, the leads are provided by the second lead frame array, which can be attached to the first lead frame array after the dies have been mounted and encapsulated on the first lead frame array.

Abstract: Disclosed is a semiconductor device in which, when two adjacent semiconductor chips are coupled with bonding wires, a short circuit between the adjacent bonding wires can be suppressed. A first bonding wire, a second bonding wire, a third bonding wire, and a fourth bonding wire are lined up in this order along a first side. When viewed from a direction perpendicular to a chip mounting part, a maximum of the space between the first bonding wire and the second bonding wire is larger than that of the space between the second bonding wire and the third bonding wire. Further, a maximum of the space between the second bonding wire and the third bonding wire is larger than that of the space between the third bonding wire and the fourth bonding wire.

Abstract: A power semiconductor module comprising a substrate. The power semiconductor module has first and second DC voltage load current connection elements and first and second power semiconductor components. The first and second power semiconductor components are arranged along a lateral first direction of the substrate. The power semiconductor module has a foil composite having a first metallic foil layer and a structured second metallic foil layer and an electrically insulating foil layer arranged between the first and second metallic foil layers. The first power semiconductor component and the second power semiconductor component are electrically conductively connected to the foil composite and to the substrate. The first and second power semiconductor components are arranged on a common side in relation to the first and second DC voltage load current connection elements. The invention provides a power semiconductor module having a particularly low-inductance construction.

Abstract: Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) wafer; The wafer has a topside surface and an back-side surface, and a plurality of device die having electrical contacts on the topside surface. The method comprises back-grinding, to a thickness, the back-side surface the wafer. A protective layer of a thickness is molded onto the backside of the wafer. The wafer is mounted onto a sawing foil; along saw lanes of the plurality of device die, the wafer is sawed, the sawing occurring with a blade of a first kerf and to a depth of the thickness of the back-ground wafer. Again, the wafer is sawed along the saw lanes of the plurality of device die, the sawing occurring with a blade of a second kerf, the second kerf narrower than the first kerf, and sawing to a depth of the thickness of the protective layer. The plurality of device die are separated into individual device die.

Abstract: A semiconductor package includes a semiconductor chip, a protruding pillar electrode provided on the semiconductor chip, and resin covering the semiconductor chip and the pillar electrode. The resin has a concave part and exposes a front edge portion of the pillar electrode from the resin at the bottom face of the concave part. The front edge portion of the pillar electrode is exposed from the concave part of the resin, which makes it possible to suppress increase in the height of the pillar electrode and to form the pillar electrodes having fine patterns or a narrow pitch.

Abstract: Disclosed is a light emitting device. The light emitting device includes a body having a cavity; first and second lead frames spaced apart from each other in the cavity, a gap part between the first and second lead frames, an adhesive material extending from at least one of sidewalls of the cavity to a top surface of at least one of the first and second lead frames, a light emitting chip on at least one of the first and second lead frames, and a molding member adhering to the adhesive material in the cavity.

Abstract: An integrated circuit packaging system and method of manufacture thereof including: providing a pre-plated leadframe having a contact protrusion and a protective pad on the contact protrusion; forming a contact pad and traces by etching the pre-plated leadframe; applying a trace protection layer on the contact pad, the traces, and the protective pad; removing the protective pad and a portion of the trace protection layer for exposing the contact pad; and depositing an external connector directly on a surface of the contact pad.

Abstract: A semiconductor package may include first and second semiconductor chips stacked one upon the other, and each including, over a bottom surface thereof, first normal pads electrically coupled with first input/output circuits and first dummy pads located over the bottom surface of the first semiconductor chip. The semiconductor package may include first through electrodes passed through the first semiconductor chip, and electrically coupled to the first dummy pads of the first semiconductor chip and the first normal pads of the second semiconductor chip. The semiconductor package may include a substrate configured to support the bottom surface of the first semiconductor chip, and including first coupling pads electrically coupled with the first normal pads and the first dummy pads of the first semiconductor chip, respectively.

Abstract: A light emitting device has a lead frame which has a lead frame body and a plurality of bumper sections raised from the lead frame body. A rectangular case member with a hole is mounted to the lead frame. A light emitting element is placed in the hole of the case member, which is filled with a sealing resin that seals the light emitting element. The bumper sections are arranged on two opposite sides of the case member. Tip surfaces of the bumper sections are at a level higher than or equal to an upper end surface of the case member.

Abstract: An interposer includes a substrate having a contact pad structure and a stud operably coupled to the contact pad structure. A solder ball is seated on the contact pad structure and formed around the stud. The stud is configured to regulate a collapse of the solder ball when a top package is mounted to the substrate.

Abstract: Embodiments of the present invention provide for a transmission circuit that includes a transmission line and a conductive via. The transmission line is electrically coupled to a first conductive via and a second conductive via. The first conductive via includes a first via stub, wherein the transmission line is configured to transmit a signal that is coupled to the first conductive via, and wherein the first via stub extends beyond the transmission line. The second conductive via includes a second via stub, wherein the transmission line is configured to transmit a signal that is coupled to the second conductive via, and wherein the second via stub extends beyond the transmission line. A transmission line stub is electrically coupled to the transmission line or to at least one of the conductive vias, wherein the length of the transmission line stub is configured to suppress a preselected frequency.

Abstract: A wiring substrate includes: a core substrate made of glass and having: a first surface; a second surface opposite to the first surface; and a side surface between the first surface and the second surface; and an insulating layer and a wiring layer, which are formed on at least one of the first surface and the second surface of the core substrate. A plurality of concave portions are formed in the side surface of the core substrate to extend from the first surface to the second surface, and a resin is filled in the respective concave portions.

Abstract: A power electronic system with a cooling device, and a method for producing the system, comprising a plurality of submodules, each submodule having a first planar insulating material body, one first conductor track cohesively connected thereto, one power switch arranged on the conductor track, at least one internal connecting device composed of an alternate layer sequence of at least one electrically conductive film and at least one electrically insulating film, wherein at least one electrically conductive layer forms at least one second conductor track, and comprising external connection elements. In this case, the submodules are arranged cohesively or in a force-locking manner and in a manner spaced apart from one another with their first main surface on the cooling device. At least one second conductor track at least partially covers first conductor tracks of two submodules, electrically connects them to one another and covers an interspace between the submodules.

Abstract: Various embodiments include wafer level chip scale package (WLCSP) structures and methods of tuning such structures. In some embodiments, the WLCSP structure includes: a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the PCB ground plane; a signal ball contacting the signal PCB trace connection; a chip pad contacting the signal ball, and a signal trace connection on a chip contacting the chip pad.

Abstract: Disclosed herein are a power module package and a method for manufacturing the same. According to a preferred embodiment of the present invention, a power module package includes: a metal substrate having an insulating layer and a circuit pattern formed on one surface thereof; at least one first electronic device mounted on the circuit pattern; a lead frame disposed around the metal substrate; a molding area enclosing the metal substrate, the first electronic device, and a portion of the lead frame; and a heat sink including a connection part contacting the insulating layer and a body part disposed on a surface opposite to the first electronic device and including one surface bonded to the connection part and the other surface exposed from an upper surface of the molding area.

Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier.

Abstract: A system and a method of manufacture of an integrated circuit system includes: a supply grid connected to an active component of an integrated circuit die; a high voltage capacitor connected to the supply grid; a low voltage decoupling capacitor connected to the supply grid; a pass gate gating the low voltage decoupling capacitor; and a pass gate control for controlling the pass gate to cause the high voltage capacitor and the low voltage decoupling capacitor to stabilize voltage of the supply grid during activity of the active component.

Abstract: Methods and apparatuses are disclosed for fabricating a printed circuit board (PCB) having electromagnetic interference (EMI) shielding and also having reduced volume over conventional frame-and-shield approaches. Some embodiments include fabricating the PCB by mounting an integrated circuit to the PCB, outlining an area corresponding to the integrated circuit with a number of grounded vias, selectively applying an insulating layer over the PCB such that at least one of the grounded vias are exposed, and selectively applying a conductive layer over the PCB such that the conductive layer covers at least a portion of the integrated circuit and such that the conductive layer is coupled to the at least one of the grounded vias that are exposed.

Abstract: In-process units include upper and lower dielectric substrates and a plurality of microelectronic elements disposed between the upper and lower substrates. Each of the upper and lower substrates includes a plurality of regions. Each region of the upper substrate is aligned with a corresponding region of the lower substrate. At least one of the microelectronic elements is disposed between the upper and lower substrates and each of the regions of the upper and lower substrates has interlayer connection terminals at the surface thereof. Vertically elongated electrical conductors are formed from copper and each extend in a vertical direction away from the surface of a dielectric substrate of one of the upper and lower dielectric substrates and have an end joined with an electrically conductive bonding material to the interlayer connection terminal of the region of an other one of the upper and lower dielectric substrates.

Abstract: A method of fabricating a wiring board includes forming a resist layer, such as a solder or plating resist layer, defining an opening portion on a support board such that a portion of the support board is exposed. An electrode is formed directly on the support board within the opening portion, and the plating resist layer, when used, is removed. An insulating layer is formed on the electrode, as well as the support board or solder resist layer, and a wiring portion connected to the electrode at the insulating layer is also formed. A solder resist layer having an opening portion is then formed on the wiring portion, and the support board is removed to expose a surface of the electrode or a surface of the electrode and insulating layer. Another solder resist layer having an opening portion may then be formed on the exposed surface of the insulating layer.

Abstract: According to one embodiment, a semiconductor power converter includes first and second electrical conductors opposed to each other, first and second semiconductor elements joined to a first joint surface of the first electrical conductor, first and second convex electrical conductors joined to the first and second semiconductor elements, a junction joined to the first and second convex electrical conductors and a second joint surface of the second electrical conductor, power terminals, signal terminals, and an envelope sealing the constituent members. The envelope includes a flat bottom surface which extends perpendicular to the semiconductor elements and in which first and second bottom surfaces of the electrical conductors are exposed.

Abstract: Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing.

Abstract: A controller including a non-volatile memory to store a repair address, and a memory control unit operatively coupled with the non-volatile memory. The memory control unit comprising a memory test function configured to detect a malfunctioning address of primary data storage elements within a memory device. The memory device being another semiconductor device separate from the controller. The memory test function configured to store the repair address in the non-volatile memory, the repair address indicating the malfunctioning address of the primary data storage element.

Abstract: According to a semiconductor device (101), a first switching active element (103) of a normally-on type and a second switching active element (104) of a normally-off type are cascode-connected to each other. This causes an electric current path to be formed. The first and second switching active elements (103, 104) are provided and connected so that loop area of the electric current path is a minimum area in a plan view of the semiconductor device (101).

Abstract: The invention provides a package structure of optical transceiver component, comprising: a metal base; a plurality of pins, at least one optical emitting diode and/or at least one optical receiving diode; wherein the pins are provided and passed through the metal base and insulated with the metal base by using an insulating material; the optical emitting diode and the optical receiving diode are each mounted on the metal base through a sub-mount, respectively. The optical emitting diode/optical receiving diode is connected to the pins neighboring therewith by a wire directly or through the sub-mount, when set the top surface of the pins be a reference level, at least one of the top surfaces of the optical emitting diode, the optical receiving diode, and sub-mount is flush with the reference level.

Abstract: A circuit assembly is disclosed which includes first and second substrates disposed on a heat dissipation base, and first and second semiconductor elements mounted on the first and second substrates. The first and second substrates are wired together, and three main electrode terminals are provided when the first and second semiconductor elements are connected in series, while two main electrode terminals are provided when the first and second semiconductor element are connected in parallel. In both cases, the circuit assembly is covered with a common exterior case so that one portion of each main electrode terminal or one portion of each main electrode terminal is exposed. Parts used in the circuit assembly are shared, and by changing the wiring between the first and second substrates, semiconductor modules with different functions are realized at low cost.

Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a device having a substrate on a back side and components in front side layers is formed. A backside layer is formed over the substrate, the layer resisting warpage of the device when the device is heated. The device is attached to a substrate by heating.

Abstract: A chip package has multiple chips that may be arranged side-by-side or in a staggered, stair step arrangement. The contacts of the chips are connected to interconnect pads carried on the chips themselves or on a redistribution substrate. The interconnect pads desirably are arranged in a relatively narrow interconnect zone, such that the interconnect pads can be readily wire-bonded or otherwise connected to a package substrate.

Abstract: An electrically conducting, vertically displacing microelectromechanical system (MEMS) is formed on a first integrated circuit chip. The first integrated circuit chip is physically connected to a three-dimensional packaging structure. The three-dimensional packaging structure maintains a fixed distance between the first integrated circuit chip and a second integrated circuit chip. A control circuit is operatively connected to the MEMS. The control circuit directs movement of the MEMS between a first position and a second position. The MEMS makes contact with a contact pad on the second integrated circuit chip when it is in the second position forming a conductive path and providing electrical communication between the first integrated circuit chip and the second integrated circuit chip. The MEMS avoids making contact with the contact pad on the second integrated circuit chip when it is in the first position.