Abstract: An organic light emitting device includes a cathode and an optional substrate external to the device. The device further includes at least one film layer disposed on at least one of the cathode or the substrate. The at least one film layer includes at least one of a magnetic, a mixed magnetic material, and combinations thereof. The device further includes an anode and at least one organic layer intermediate the cathode and anode.

Abstract: A method for fabricating a via hole includes forming a first mask pattern on a first surface of a wafer exposing a portion of the first surface of the wafer, forming a passivation region within the wafer by implanting impurities into the exposed portion of the wafer using the first mask pattern as an ion implantation barrier layer, forming an etching stop layer on the first surface of the wafer including the passivation regions, forming a second mask pattern on a second surface of the wafer faces away from the first surface of the wafer, wherein the second mask pattern exposes a portion of the second surface of the wafer over an area between the passivation regions, and forming a via hole by etching the wafer using the second mask pattern as an etching mask.

Abstract: To provide a method of manufacturing a semiconductor device that can be in contact with both of an n-type SiC region and a p-type SiC region and can suppress increase in contact resistance due to oxidation, a method of manufacturing a semiconductor device includes the steps of preparing a SiC layer, and forming an ohmic electrode on a main surface of the SiC layer. The step of forming the ohmic electrode includes the steps of forming a conductor layer which will become the ohmic electrode on the main surface of the SiC layer, and performing heat treatment such that the conductor layer becomes the ohmic electrode. After the step of performing the heat treatment, a temperature of the ohmic electrode when a surface of the ohmic electrode is exposed to an atmosphere containing oxygen is set to 100° C. or lower.

Abstract: Methods of forming metal contacts with metal inks in the manufacture of photovoltaic devices are disclosed. The metal inks are selectively deposited on semiconductor coatings by inkjet and aerosol apparatus. The composite is heated to selective temperatures where the metal inks burn through the coating to form an electrical contact with the semiconductor. Metal layers are then deposited on the electrical contacts by light induced or light assisted plating.

Abstract: The present invention relates to a package having a semiconductor device. The semiconductor device includes a substrate body, a plurality of conductive vias and a plurality of metal pads. The conductive vias are disposed in the through holes of the substrate body. The metal pads are electrically connected to the conductive vias. At least one of the metal pads has at least one curved side wall and at least one reference side wall. The curvature of the curved side wall is different from that of the reference side wall, so as to allow the metal pads to be closer to each other. This arrangement allows the conductive to be closer to each other. Therefore, more conductive vias can be arranged in a limited space.

Abstract: A method for fabricating a backside metallization structure on a semiconductor substrate including moving a printhead having at least one nozzle orifice relative to the semiconductor substrate, and feeding an Al passivation layer ink and an AgAl soldering pad ink through said printhead such that both said Al passivation layer ink and said AgAl soldering pad ink are simultaneously extruded from said at least one nozzle orifice and deposited onto the semiconductor substrate.

Abstract: A semiconductor apparatus includes a semiconductor chip formed on a predetermined area of a wafer, wafer test block formed on an area outside the predetermined area, and signal line for electrically connecting the semiconductor chip to the wafer test block. Through-silicon via is formed to vertically penetrate the signal line.

Abstract: A semiconductor device includes isolation layers arranged in a memory array region and a monitoring region, wherein the isolation layers are positioned in parallel; gate lines arranged to cross the isolation layers in the memory array region, wherein the gate lines are formed in the memory array region; dummy gate lines arranged in a substantially same direction as the isolation layers in the monitoring region, wherein the dummy gate lines are formed in the monitoring region; monitoring junctions arranged between the dummy gate lines and in a substantially same direction as the dummy gate lines, wherein the monitoring junctions are arranged in the monitoring region; and spacers arranged on sidewalls of each of the gate lines and the dummy gate lines, wherein at least one of the monitoring junctions is covered by any one of the spacers.

Abstract: The method of forming a wordline is provided in the present invention. The proposed method includes steps of: (a) providing a plurality of SASTIs with a plurality of first POLY cells deposited thereon; and (b) depositing a first fill-in material having a relatively high etching rate oxide-like material in the plurality of SASTIs and on each side wall of the plurality of first POLY cells.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a first to fourth films over a semiconductor substrate. The method further includes patterning the fourth film to form sparse and dense portions in which patterns of the fourth film are sparse and dense, respectively, and etching the third film by using the patterns of the fourth film as a mask. The method further includes etching the third film by using the patterns of the third and fourth films as a mask so as to expose the first film between the patterns in the sparse portion, and so as to partially remove the second film between the patterns in the dense portion so that the second film between the patterns remains.

Abstract: A semiconductor pressure sensor (720) includes a thin film piezoelectric element (701) which applies strain to a portion of a semiconductor substrate that corresponds to a thin region (402). The thin film piezoelectric element (701) is formed at a distance away from diffusion resistors (406, 408, 410, and 412) functioning as strain gauges and is extended to the proximity of a bonding pad (716A) connected to an upper electrode layer of the thin film piezoelectric element and a bonding pad (716F) connected to a lower electrode thereof. The diffusion resistors (406, 408, 410, and 412) constitute a bridge circuit by metal wiring (722) and diffusion wiring (724). During self-diagnosis, a prescribed voltage is applied to a thin film piezoelectric element (701). If the output difference of the bridge circuit between before and after the voltage application falls outside a prescribed range, it is determined that a breakage occurs in the semiconductor pressure sensor (720).

Abstract: A sensing device (10, 10?) includes a substrate (14), and first and second electrodes (EIC, EICS, EO) established on the substrate (14). The first electrode (EIC, EICS) has a three-dimensional shape, and the second electrode (EO) is electrically isolated from and surrounds a perimeter of the first electrode (EIC, EICS).

Abstract: A semiconductor device includes a first plug formed on a semiconductor substrate and exposed on side and upper surfaces of an upper part thereof and a second plug formed on the first plug to contact the exposed side and upper surfaces of the upper part of the first plug.

Abstract: A method of forming a concave-convex pattern according to an embodiment includes: forming a guide pattern on a base material, the guide pattern having a convex portion; forming a formative layer on the guide pattern, the formative layer including a stacked structure formed by stacking a first layer and a second layer, the first layer including at least one element selected from a first metal element and a metalloid element, the second layer including a second metal element different from the first metal element; selectively leaving the formative layer only at side faces of the convex portions by performing etching on the formative layer; removing the guide pattern; and forming the concave-convex pattern in the base material by performing etching on the base material, with the remaining formative layer being used as a mask.

Abstract: Embodiments relate to a method for making a semiconductor structure, the method comprising: forming a seed layer in direct contact with a dielectric material; forming a masking layer over the seed layer; patterning the masking layer to expose the seed layer; forming a fill layer over the exposed seed layer; and causing the seed layer to react with the dielectric layer to form a barrier layer between the fill layer and the dielectric layer

Abstract: There is provided an electromechanical transducer capable of improving yield and obtaining a cavity having a good internal flatness, and a method of fabricating the same. The electromechanical transducer is fabricated in such a manner that an SOI substrate 209 having an active layer 210 whose surface is planarized on a supporting substrate 201 with a thermal oxide insulating layer 205 interposed therebetween is provided; the active layer is patterned into a cavity shape; insulating films 206 and 207 are formed on the patterned active layer; an etching hole 203 passing through the insulating films and communicating with the active layer is formed; and a cavity 202 is formed by etching away the active layer using the etching hole.

Abstract: A method for contacting an FET device is disclosed. The method includes vertically recessing the device isolation, which exposes a sidewall surface on both the source and the drain. Next, silicidation is performed, resulting in a silicide layer covering both the top surface and the sidewall surface of the source and the drain. Next, metallic contacts are applied in such manner that they engage the silicide layer on both its top and on its sidewall surface. A device characterized as being an FET device structure with enlarged contact areas is also disclosed. The device has a vertically recessed isolation, thereby having an exposed sidewall surface on both the source and the drain. A silicide layer is covering both the top surface and the sidewall surface of both the source and the drain. Metallic contacts to the device engage the silicide on its top surface and on its sidewall surface.

Abstract: A method for fabricating a semiconductor device includes forming first plugs over a substrate, forming contact holes that expose the first plugs, ion-implanting an anti-diffusion material into the first plugs, and forming second plugs filling the contact holes.

Abstract: Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.

Abstract: The present disclosure provides a semiconductor device, including a substrate having a seal ring region and a circuit region, a seal ring structure disposed over the seal ring region, a first passivation layer disposed over the seal ring structure, the first passivation layer having a first passivation layer aperture over the seal ring structure, and a metal pad disposed over the first passivation layer, the metal pad coupled to the seal ring structure through the first passivation layer aperture and having a metal pad aperture above the first passivation layer aperture. The device further includes a second passivation layer disposed over the metal pad, the second passivation layer having a second passivation layer aperture above the metal pad aperture, and a polyimide layer disposed over the second passivation layer, the polyimide layer filling the second passivation layer aperture to form a polyimide root at an exterior tapered edge of the polyimide layer.

Abstract: [Problem] A semiconductor device which achieves a fine pitch, a high throughput and a high connection reliability, especially in flip-chip mounting is provided. A method for manufacturing the semiconductor device and a circuit device using the semiconductor device are also provided. [Means for solving the problem] The semiconductor device has: an electrode; an insulating part having an opening on the electrode; a protruding part formed on the electrode; a protecting part which is formed at the periphery of the protruding part and electrically isolates the protruding part; and a bonding part which is formed on the protecting part by being spaced apart from the protruding part. An upper surface of the protruding part, an upper surface of the protecting part, and an upper surface of the bonding part form the same plane.

Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.

Abstract: Techniques for forming metal silicide contact pads on semiconductor devices are disclosed, and in one exemplary embodiment, a method may comprise depositing a metal layer on and between a plurality of raised silicon-based features formed on a semiconductor substrate, the metal layer comprising metal capable of reacting with external silicon-based portions of the features to form a metal silicide. In addition, such a method may also include depositing a cap layer on the metal layer deposited on and between the plurality of raised silicon-based features, wherein a thickness of the cap layer on the metal layer between the raised features is greater than or equal to a thickness of the cap layer on the metal layer on the raised features. Furthermore, such a method may also include annealing the structure to cause portions of the metal layer to react with portions of the external silicon-based portions of the features to form metal silicide pads on and between the raised features.

Abstract: A semiconductor apparatus includes: an MOS type field effect transistor formed on a semiconductor substrate and having a first gate electrode set at a predetermined impurity concentration; and a charge modulation device formed on the semiconductor substrate and having a second gate electrode set at a predetermined impurity concentration lower than the impurity concentration of the first gate electrode.

Abstract: Provided are a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a semiconductor substrate including a first active region and a second active region, a gate electrode including a silicide layer formed on the first active region and a resistor pattern formed on the second active region. A distance from a top surface of the semiconductor substrate to a top surface of the resistor pattern is smaller than a distance from a top surface of the semiconductor substrate to a top surface of the gate electrode.

Abstract: A method for reducing contact to gate shorts in a semiconductor device and the resulting semiconductor device are described. In one embodiment, a gate is formed on a substrate, a contact is formed on the gate and the substrate, and an insulator is formed between the gate and the contact. The insulator may be formed by oxidizing the gate to form a dielectric between the contact and the gate after the contact is formed on the gate.

Abstract: A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures.

Abstract: A light emitting diode (LED) includes a substrate, a temperature detecting pattern, and a semiconductor structure. The temperature detecting pattern is formed on the substrate. Then the semiconductor structure is formed on the temperature detecting pattern and the substrate. The semiconductor structure includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer. Per above-mentioned structural design, the temperature detecting pattern directly integrated into the LED can measure the actual temperature of PN junction with high precision.

Abstract: According to the present invention, there is provided an electrode structure which includes: a nitride semiconductor layer; an electrode provided over the nitride semiconductor layer; and an electrode protective film provided over the electrode, wherein the nitride semiconductor layer contains a metal nitride containing Nb, Hf or Zr as a constitutive element, the electrode has a portion having a metal oxide containing Ti or V as a constitutive element formed therein, and the electrode protective film covers at least a portion of the electrode, and contains a protective layer having Au or Pt as a constitutive element.

Abstract: A manufacturing method of a single chip semiconductor coating structure includes following steps. Step 1 is providing a single chip semiconductor which has a plurality of surfaces, and two opposite surfaces selected from the plurality of surfaces are manufacturing surfaces and have a conductive area with a pad thereon, respectively. Step 2 is providing a tool to cover one of the conductive areas with the pad. Step 3 is providing a coating step to form an insulating layer on the single chip semiconductor. Step 4 is providing a removing step to remove the insulating layer for exposing the covered conductive area and the pad. Step 5 is forming two electrodes and each of the two electrodes covers the conductive area with the pad.

Abstract: A method of fabricating a landing plug in a semiconductor memory device, which in one embodiment includes forming a landing plug contact hole on a semiconductor substrate having an impurity region to expose the impurity region; forming a landing plug by filling the landing plug contact hole with a polysilicon layer, wherein the landing plug is divided into a first region, a second region, a third region, and a fourth region from a lower portion of the landing plug, and the first region is doped with a first doping concentration that is relatively lowest, the second region is doped with a second doping concentration that is higher than the first doping concentration, the third region is doped with a third doping concentration that is higher than the second doping concentration and the fourth region is not doped; and annealing the resulting product formed with the landing plug.

Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a semiconductor substrate including an active region defined by a device isolation film, a bit line contact plug that is coupled to the active region and that includes a first ion implantation region buried in a first inner void, and a storage node contact plug that is coupled to the active region and includes a second ion implantation region buried in a second inner void. Although the semiconductor device is highly integrated, a contact plug is buried to prevent formation of a void, so that increase in contact plug resistance is prevented, resulting in improved semiconductor device characteristics.

Abstract: A semiconductor device has a UBM (under-bump metallization) structure underlying and electrically connected to a solder bump. The UBM structure has a first metallization layer with a first cross-sectional dimension d1, a second metallization layer with a second cross-sectional dimension d2 formed on the first metallization layer, and a third metallization layer with a third cross-sectional dimension d3 formed on the second metallization layer, in which d1 is greater than d3, and d3 is greater than d2.

Abstract: A semiconductor device with a stable structure having high capacitance by changing the pillar type storage node structure and a method of manufacturing the same are provided. The method includes forming a sacrificial layer on a semiconductor substrate including a storage node contact plug, etching the sacrificial layer to form a region exposing the storage node contact plug, forming a first conductive material within an inner side of the region, burying a second conductive material within the region in which the first conductive material is formed, and removing the sacrificial layer to form a pillar type storage node.

Abstract: A monolithically integrated trench FET and Schottky diode includes a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer. A trench in the Schottky region includes a dielectric layer lining the trench sidewalls, and a conductive electrode having a top surface that is substantially coplanar with a top surface of the semiconductor layer adjacent the trench. An interconnect layer electrically contacts the semiconductor layer in the Schottky region so as to form a Schottky contact with the semiconductor layer.

Abstract: An embodiment of an integrated device, including a chip of semiconductor material wherein an integrated circuit is integrated, is proposed; the integrated device includes a set of contact terminals for contacting the integrated circuit. At least one contact terminal of said set of contact terminals includes a contact layer of metal material being suitable to be directly coupled mechanically to an element external to the chip, and a coupling element for improving an electrical and/or mechanical coupling between the contact layer and the chip. The coupling element includes a coupling layer being formed by a combination between the metal material of the contact layer and the semiconductor material of the chip, with the coupling layer that is directly coupled to the chip and to the contact layer.

Abstract: A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.

Abstract: A semiconductor device and a method for forming the same are disclosed. In the method for manufacturing the semiconductor device, a lower electrode material is deposited over a semiconductor substrate including a lower electrode contact plug so as to form a sacrificial insulation film. After the sacrificial insulation film and a lower electrode material are etched using a dry etching process, additional lower electrode material is deposited and etched back so as to form a lower electrode. As a result, a margin or region between a lower electrode contact plug and the lower electrode can be guaranteed.

Abstract: An optoelectronic device is disclosed which includes a quantum dot layer including plurality of quantum dots which do not have capping layers. This optoelectronic device may be a quantum dot light-emitting device, which includes (1) a substrate which is transparent or translucent, (2) an anode electrical conducting layer which is transparent or translucent, and is located adjacent to the substrate, (3) a planarizing/hole injection layer which is located adjacent to the anode electrical conducting layer, (4) a quantum dot layer including the plurality of quantum dots which do not have capping layers, and (5) a cathode electrical conducting layer which is located adjacent to the quantum dot layer.

Abstract: A semiconductor switch device and a method of manufacturing the semiconductor switch device are provided. The semiconductor switch device includes semiconductor elements on a single semiconductor substrate. At least one of the semiconductor elements constitutes a switch circuit and at least one other of the semiconductor elements constitutes a logic (connection) circuit. Each semiconductor element includes a recess, a gate electrode in the recess, a drain electrode, and a source electrode. In one representative aspect, the gate electrode in the switch circuit can have a rectangular external shape in section, and the gate electrode in the connection circuit has a shape in section other than rectangular.

Abstract: The present disclosure relates to an improved method of providing a Ni silicide metal contact on a silicon surface by electrodepositing a Ni film on a silicon substrate. The improved method results in a controllable silicide formation wherein the silicide has a uniform thickness. The metal contacts may be incorporated in, for example, CMOS devices, MEM (micro-electro-mechanical) devices, and photovoltaic cells.

Abstract: A structure, comprising: a semiconductor structure having an electrically and thermally conductive layer disposed on one surface of the semiconductor structure; an electrically and thermally conductive heat sink; a electrically and thermally conductive carrier layer; a plurality of electrically and thermally nano-tubes, a first portion of the plurality of nano-tubes having proximal ends disposed on a first surface of the carrier layer and a second portion of the plurality of nano-tubes having proximal ends disposed on an opposite surface of the carrier layer; and a plurality of electrically and thermally conductive heat conductive tips disposed on distal ends of the plurality of nano-tubes, the plurality of heat conductive tips on the first portion of the plurality of nano-tubes being attached to the conductive layer, the plurality of heat conductive tips on the second portion of the plurality of nano-tubes being attached to the heat sink.

Abstract: A biocompatible electrode formed from an integrated circuit, the electrode comprising: a semiconductor substrate; and an electrode layer at least partially comprising porous valve metal oxide.

Abstract: A method of making a semiconductor device includes forming a layer over a substrate, forming a plurality of spaced apart features of imagable material over the layer, forming sidewall spacers on the plurality of features and filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature. The method also includes removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the layer using the first feature, the filler feature and the second feature as a mask.

Abstract: The present application describes an semiconductor chip having a substrate, a first conductive pad formed over the substrate, a second conductive pad formed over the substrate and positioned farther from a geometric center of the semiconductor chip than the first conductive pad, a first under bump metallurgy (UBM) structure formed over the first conductive pad, and a second UBM structure formed over the second conductive pad. The first conductive pad and the first UBM structure has a first pad width to UBM width ratio, and the second conductive pad and the second UBM structure has a second pad width to UBM width ratio that is greater than the first ratio.

Abstract: A semiconductor device, includes: a first storage node contact plug penetrating a first interlayer insulation layer and partially protruding above the first interlayer insulation layer; a second storage node contact plug contacting the first storage node contact plug that protrudes above the first interlayer insulation layer; a storage node contacting a top surface of the second storage node contact plug; and a second interlayer insulation layer formed over the first interlayer insulation layer, wherein the second interlayer insulation layer surrounds an outer sidewall at a bottom region of the first storage node, and the second storage node contact plug, and wherein the first storage node contact plug protruding above the first interlayer insulation layer and the second storage node contact plug.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a layer over a substrate. The method includes forming a first opening in the layer that exposes a first region of the substrate. The method includes removing a first oxidation layer formed over the first region through a first sputtering process. The method includes filling the first opening with a conductive material. The method includes forming a second opening in the layer that exposes a second region of the substrate, the second region being different from the first region. The method includes removing a second oxidation layer formed over the second region through a second sputtering process. One of the first and second sputtering processes is more powerful than the other.

Abstract: The present invention relates to a process for realizing a connecting structure in a semiconductor substrate, and the semiconductor substrate realized accordingly. The semi-conductor substrate has at least a first surface, and is foreseen for a 3D integration with a second substrate along the first surface, wherein the 3D integration is subject to a lateral misalignment in at least one dimension having a misalignment value.

Abstract: A semiconductor device according to this embodiment has an electrode (electrode pad) and an insulative film (protective resin film) formed on the electrode and having an opening for exposing the electrode. The semiconductor device further has an under bump metal (UBM layer) formed over the insulative film and connected with the electrode through the opening, and a solder ball formed over the under bump metal, and the contour line at the lower end of the solder ball is situated inside the contour line of the under bump metal, whereby generation of fracture in the insulative film caused by the stress upon mounting the semiconductor device is suppressed even when the solder ball is formed of a lead-free solder.

Abstract: Certain embodiments pertain to local interconnects formed by subtractive patterning of blanket layer of tungsten or other conductive material. The grain sizes of tungsten or other deposited metal can be grown to relatively large dimensions, which results in increased electrical conductivity due to, e.g., reduced electron scattering at grain boundaries as electrons travel from one grain to the next during conduction.