Abstract: A SiC MOSFET has a subject that resistance in the source region is increased when annealing for metal silicidation is performed to a source region before forming the gate insulating film, the metal silicide layer of the source region is oxidized by an oxidizing treatment (including oxynitriding treatment) when the gate insulating film is formed. When a metal silicide layer to be formed on the surface of a SiC epitaxial substrate is formed before forming a gate insulating film interface layer (oxide film), and an anti-oxidation film for the metal silicide is formed on the metal silicide layer, it is possible to suppress oxidation of the metal silicide layer by the oxidizing treatment upon forming the gate insulating film interface layer and the resistance of the source region can be decreased without lowering the channel mobility.

Abstract: The present invention provides a method of manufacturing semiconductor device having metal gate. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench and then a first metal layer and a first material layer are formed in the first trench. Next, the first metal layer and the first material layer are flattened. The second sacrifice gate is removed to form a second trench and then a second metal layer and a second material layer are formed in the second trench. Lastly, the second metal layer and the second material layer are flattened.

Abstract: A method for inducing a tensile stress in a channel of a field effect transistor (FET) includes forming a nitride film over the FET; forming a contact hole to the FET through the nitride film; and performing ultraviolet (UV) curing of the nitride film after forming the contact hole to the FET through the nitride film, wherein the UV cured nitride film induces the tensile stress in the channel of the FET.

Abstract: Another semiconductor device includes a first layer including a plurality of electrically conductive wires, a second layer, a plurality of non-functional via pads are included in the second layer or between the first layer and the second layer. A dangling via is included within a specified area of the first layer. The dangling vias connect one or more of the wires in the first layer to a respective one of the via pads.

Abstract: Disclosed herein is a joining electrode including: an insulating layer; a recessed portion formed in the insulating layer; a covering layer formed on a side surface and a bottom surface of the recessed portion; and a joining metallic layer formed on the covering layer and having an upper surface protruding from a surface of the insulating layer.

Abstract: Provided are a semiconductor device manufacturing method and a substrate processing apparatus that are capable of increasing a work function of a film to be formed, in comparison with a related art. A cycle including (a) supplying a metal-containing gas into a processing chamber where a substrate is accommodated (b) supplying a nitrogen-containing gas into the processing chamber; and (c) supplying one of an oxygen-containing gas, a halogen-containing gas and a combination thereof into the processing chamber, is performed a plurality of times to form a metal-containing film on the substrate.

Abstract: Methods for etching metal nitrides and metal oxides include using ultradilute HF solutions and buffered, low-pH HF solutions containing a minimal amount of the hydrofluoric acid species H2F2. The etchant can be used to selectively remove metal nitride layers relative to doped or undoped oxides, tungsten, polysilicon, and titanium nitride. A method is provided for producing an isolated capacitor, which can be used in a dynamic random access memory cell array, on a substrate using sacrificial layers selectively removed to expose outer surfaces of the bottom electrode.

Abstract: A package substrate is disclosed. The package substrate includes a substrate body having a conductive portion, a plurality of insulation portions and two surfaces opposing to each other; and a plurality of bonding layers for heat dissipation formed on the two surfaces of the substrate body, conducted via the conductive portion and separated from one another by the insulation portions. A method for forming the package substrate is also disclosed.

Abstract: A semiconductor wafer has a contact pad. A first insulating layer is formed over the wafer. A second insulating layer is formed over the first insulating layer and contact pad. A portion of the second insulating layer is removed to expose the contact pad. A first UBM layer is formed over and follows a contour of the second insulating layer and contact pad to create a well over the contact pad. A first buffer layer is formed in the well over the first UBM layer and the contact pad. A second UBM layer is formed over the first UBM layer and first buffer layer. A third UBM layer is formed over the second UBM layer. A bump is formed over the third UBM layer. The first buffer layer reduces stress on the bump and contact pad. A second buffer layer can be formed between the second and third UBM layers.

Abstract: Method for formation of at least one electrical conductor on a semiconductor material (1), characterized in that it comprises the following steps: (E1)—deposition by serigraphy of a first high-temperature paste; (E2)—deposition by serigraphy of a second low-temperature paste at least partially superposed onto the first high-temperature paste deposited during the preceding step.

Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes: forming a stacked body including insulating films stacked alternately with electrode films, a memory hole is made in one portion of the stacked body to extend in a stacking direction, a charge storage layer is provided on an inner surface of the memory hole, a semiconductor member is provided in the memory hole; forming a hard mask on the stacked body, the hard mask has a plurality of holes of mutually different sizes; plugging the smallest of the holes while shrinking the other holes by depositing a mask material; making contact holes by removing a prescribed number of the insulating films and a prescribed number of the electrode films in regions directly under the other holes by performing etching using the mask material and the hard mask as a mask; and filling conductive material into the contact holes.

Abstract: An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to the cathode); and a silicide layer on the fuse link. The silicide layer has a first silicide region adjacent the anode and a second silicide region adjacent the cathode. The second silicide region comprises an impurity not contained within the first silicide region. Further, the first silicide region is thinner than the second silicide region.

Abstract: Embodiments of the invention relate to a silicon semiconductor device, and a conductive thick film composition for use in a solar cell device.

Abstract: A method of manufacturing a semiconductor device includes forming an insulating film on a surface of a semiconductor layer, forming a resist on a surface of the insulating film, the resist having an opening, forming a hardened layer on an inner circumference of the resist by attaching a pattern shrinking agent to the resist, the pattern shrinking agent undergoing a cross-linking reaction with the resist, etching the insulating film using the resist and the hardened layer as masks, removing the hardened layer, and forming a metal layer on a surface of the semiconductor layer, on a surface of the insulating film, and on a surface of the resist. The method further includes removing the resist and the portion of the metal layer on the surface of the resist by lift-off.

Abstract: A method includes forming a pad on an electronic component. The pad comprises conductive material. The method further includes providing passivation material on a surface of the conductive material and removing passivation material from the surface to expose portions of the conductive material to form a bond pad comprising conductive material and passivation material.

Abstract: A method of forming fine patterns in a semiconductor device includes forming narrow-width patterns in a first region and wide-width patterns in a second region, where the widths of the narrow-width patterns are smaller than the resolution limitations in a photolithography process used to make the semiconductor device. The first and second regions may comprise cell array regions, with memory cells in the first region and peripheral circuits for operating the memory cells in the second region. The semiconductor device can be, for example, a NAND FLASH memory device. The semiconductor memory device can be variously classified according to the type of memory cells to be integrated in the cell array region, e.g., a DRAM, an SRAM, a PRAM, a RRAM, an MRAM, and a FRAM. In other embodiments, a MEMS device, an optoelectronic device, or a processor, such as CPU or DSP, may be provided on the semiconductor substrate.

Abstract: A method for opening a one-side contact region of a vertical transistor is provided. The one-side contact region of the vertical transistor is opened using a polysilicon layer, a certain portion of which can be selectively removed by a selective ion implantation process. In order to selectively remove the polysilicon layer formed on one of both sides of an active region, at which the one-side contact is to be formed, impurity ion implantation is performed in a direction vertical to the polysilicon layer by a plasma doping process, and a tilt ion implantation using an existing ion implantation process is performed. In this manner, the polysilicon layer is selectively doped, and the undoped portion of the polysilicon layer is selectively removed.

Abstract: A light emitting device is provided. The light emitting device may include a plurality of light emitting elements formed on a first common electrode, each light emitting element having a first conductive layer formed over the first common electrode. The light emitting device may also include an active layer formed over the first conductive layer, a second conductive layer formed over the active layer, and an insulator formed between adjacent light emitting elements. A plurality of electrodes may be respectively formed on the plurality of light emitting elements, and a second common electrode may couple the plurality electrodes. Such a light emitting structure may improve emission characteristics, heat dissipation and high temperature reliability.

Abstract: A smooth electrode is provided. The smooth electrode includes at least one metal layer having thickness greater than about 1 micron; wherein an average surface roughness of the smooth electrode is less than about 10 nm.

Abstract: Provided are a semiconductor device including a source/drain and a gate formed using a doped polysilicon process, and a method of fabricating the semiconductor device. The method comprises: forming a gate insulating layer on a part of an active region on a first conductivity type epitaxial layer; forming a conductive layer on the epitaxial layer; implanting high concentration impurities of a second conductivity type a first portion of the conductive layer on the gate insulating layer and second portions of the conductive layer on both sides of the first insulating layer; patterning the conductive layer; forming a second insulating layer on the epitaxial layer and high concentration impurity regions of the second conductivity type below the second conductive pattern; and implanting low-concentration impurities of the second conductivity type into the epitaxial layer between a gate structure and the high concentration impurity regions.

Abstract: A nitride-based semiconductor device according to the present disclosure includes a nitride-based semiconductor multilayer structure 20 with a p-type semiconductor region, of which the surface 12 defines a tilt angle of one to five degrees with respect to an m plane, and an electrode 30, which is arranged on the p-type semiconductor region. The p-type semiconductor region is made of an AlxInyGazN (where x+y+z=1, x?0, y?0 and z?0) semiconductor layer 26. The electrode 30 includes an Mg layer 32, which is in contact with the surface 12 of the p-type semiconductor region, and a metal layer 34 formed on the Mg layer 32. The metal layer 34 is formed from at least one metallic element that is selected from the group consisting of Pt, Mo and Pd.

Abstract: A semiconductor device includes: a semiconductor substrate; an interlayer film on the substrate; a surface electrode on the interlayer film; a surface pad on the surface electrode; a backside electrode on the substrate; an element area including a cell portion having a vertical semiconductor element and a removal portion having multiple contact regions; and an outer periphery area. The surface electrode in the removal portion is electrically coupled with each contact region through a first contact hole in the interlayer film. The surface electrode in the cell portion is electrically coupled with the substrate through a second contact hole in the interlayer film. A part of the surface electrode in the removal portion facing each contact region is defined as a contact portion. The surface electrode includes multiple notches on a shortest distance line segment between each contact portion and the surface pad.

Abstract: A thermal printhead die is formed from an SOI structure as a MEMS device. The die has a printing surface, a buried oxide layer, and a mounting surface opposite the printing surface. A plurality of ink delivery sites are formed on the printing surface, each site having an ink-receiving and ink-dispensing structure. An ohmic heater is formed adjacent to each structure, and an under-bump metallization (UBM) pad is formed on the mounting surface and is electrically connected to the ohmic heater, so that ink received by the ink-delivery site and electrically heated by the ohmic heater may be delivered to a substrate by sublimation. A through-silicon-via (TSV) plug may be formed through the thickness of the die and electrically coupled through the buried oxide layer from the ohmic heater to the UBM pad. Layers of interconnect metal may connect the ohmic heater to the UBM pad and to the TSV plug.

Abstract: An integrated circuit (IC) device includes an interposer having a dielectric substrate having a first side, a second side, and an inner aperture, wherein a plurality of electrically conductive traces are on the first side. An IC die includes a topside semiconductor surface having active circuitry and a bottomside surface, wherein the topside semiconductor surface includes a plurality of bond pads, and is attached over the inner aperture onto the interposer. First wirebond interconnects couple respective bond pads to respective electrically conductive traces. A workpiece includes a top workpiece surface including a plurality of contact pads thereon attached to the first side of the interposer. Second interconnects couple respective conductive traces to respective contact pads on the workpiece.

Abstract: Methods, apparatus, and systems for depositing tungsten having tailored stress levels are provided. According to various embodiments, the methods involve depositing high stress or low stress tungsten films. In certain embodiments depositing high stress tungsten involves a multi-stage chemical vapor deposition (CVD) process including a low temperature deposition followed by a high temperature deposition. In certain embodiments depositing low stress tungsten involves a CVD process using a relatively low tungsten precursor flow. Also provided are new classes of high and low stress tungsten films, which may also have low resistivity and/or high reflectivity. Also provided are integration methods involving depositing high or low stress tungsten, for example as contacts and/or metal gates, and semiconductor devices incorporating the tungsten films.

Abstract: A switching element according to the present invention includes an ion-conducting layer, first electrode 11 and second electrode 12 placed in contact with the ion-conducting layer, and third electrode 15 placed in contact with the ion-conducting layer and to control electrical conductivity between the first electrode and the second electrode, wherein the shortest distance between any two of first, second, and third electrodes 11, 12, and 13 is defined by the film thickness of the ion-conducting layer.

Abstract: The method of forming a polysilicon layer is provided. A first polysilicon layer with a first grain size is formed on a substrate. A second polysilicon layer with a second grain size is formed on the first polysilicon layer. The first grain size is smaller than the second grain size. The first polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the second polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved.

Abstract: In a method of forming a conductive pattern structure of a semiconductor device, a first insulating interlayer is formed on a substrate. A first wiring is formed to pass through the first insulating interlayer. An etch stop layer and a second insulating interlayer are sequentially formed on the first insulating interlayer. A second wiring is formed to pass through the second insulating interlayer and the etch stop layer. A dummy pattern is formed to pass through the second insulating layer and the etch stop layer at the same time as forming the second wiring. The second wiring is electrically connected to the first wiring. The dummy pattern is electrically isolated from the second wiring.

Abstract: Embodiments of this invention provide a method to fabricate an electrical contact. The method includes providing a substrate of a compound Group III-V semiconductor material having at least one electrically conducting doped region adjacent to a surface of the substrate. The method further includes fabricating the electrical contact to the at least one electrically conducting doped region by depositing a single crystal layer of germanium over the surface of the substrate so as to at least partially overlie the at least one electrically conducting doped region, converting the single crystal layer of germanium into a layer of amorphous germanium by implanting a dopant, forming a metal layer over exposed surfaces of the amorphous germanium layer, and performing a metal-induced crystallization (MIC) process on the amorphous germanium layer having the overlying metal layer to convert the amorphous germanium layer to a crystalline germanium layer and to activate the implanted dopant.

Abstract: A dynamic and end-user configurable controlled impedance interconnect line includes a plurality of conductive pixels, a plurality of thin-film transition material interconnects to electrically connect adjacent conductive pixels in the plurality of conductive pixels, and a plurality of addressable pixel interconnect actuators to selectively heat a respective plurality of the thin-film transition material interconnects. The plurality of addressable pixel interconnect actuators is operable to selectively heat a respective plurality of the thin-film transition material interconnects to form an interconnect line.

Abstract: The formation of the conductive wire of a chip package consists of a plurality of steps. Coat a first dielectric layer on the pad-mounting surface and a slot is formed on each bonding pad correspondingly. Then coat a second dielectric layer and produce a wiring slot corresponding to each bonding pad and the slot thereof. Next each wiring slot is filled with electrically conductive metal so as to form a conductive wire. Later Coat a third dielectric layer and a corresponding slot is formed on one end of each conductive wire while this slot is filled with electrically conductive metal to form a solder point. The above steps can further be repeated so as to form an upper-layer and a lower-layer conductive wire. Thereby precision of the chip package, use efficiency of the wafer and yield rate of manufacturing processes are all improved.

Abstract: A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive.

Abstract: A method is described which includes providing a substrate and forming a first spacer material layer abutting a gate structure on the substrate. A second spacer material layer is formed adjacent and abutting the gate structure and overlying the first spacer material layer. The first spacer material layer and the second spacer material layer are then etched concurrently to form first and second spacers, respectively. An epitaxy region is formed (e.g., grown) on the substrate which includes an interface with each of the first and second spacers. The second spacer may be subsequently removed and the first spacer remain on the device decreases the aspect ratio for an ILD gap fill. An example composition of the first spacer is SiCN.

Abstract: The present invention provides systems, methods and apparatus for manufacturing a memory cell. The invention includes forming a feature having sidewalls in a first dielectric material; forming a first conductive material on the sidewalls of the feature; depositing a layer of a second dielectric material on the conductive material; and exposing the second dielectric material to oxidizing species and ultraviolet light to oxidize the second dielectric material. Numerous additional aspects are disclosed.

Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor body with a horizontal surface. An epitaxy hard mask is formed on the horizontal surface. An epitaxial region is formed by selective epitaxy on the horizontal surface relative to the epitaxy hard mask so that the epitaxial region is adjusted to the epitaxy hard mask. A vertical trench is formed in the semiconductor body. An insulated field plate is formed in a lower portion of the vertical trench and an insulated gate electrode is formed above the insulated field plate. Further, a method for forming a field-effect semiconductor device is provided.

Abstract: Semiconductors are electrochemically etched in solutions containing sources of bifluoride and nickel ions. The electrochemical etching may form pores in the surface of the semiconductor in the nanometer range. The etched semiconductor is then nickel plated.

Abstract: A three-dimensional integrated circuit includes a semiconductor device, an insulator formed on the semiconductor device, an interconnect formed in the insulator, and a graphene device formed on the insulator.

Abstract: An IC package is provided. The IC package comprises a leadframe comprising a metal strip(222) partially etched on a first side. The leadframe may be configured for an IC chip to be mounted thereon and for a plurality of bonding areas(218) to be electrically coupled to the leadframe and the IC chip. The IC chip, the bonding areas, and a portion of the metal leadframe are covered with an encapsulation compound, with a plurality of contact pads(206) protruding from the bottom surface of the leadframe. The bottom surface of the leadframe may be etched one or more times during the manufacturing process to reduce the depth of the undercutting. A method for manufacturing an IC package is also provided.

Abstract: A silicon carbide substrate having a substrate surface is prepared. An insulating film is formed to cover a part of the substrate surface. A contact electrode is formed on the substrate surface, so as to be in contact with the insulating film. The contact electrode contains Al, Ti, and Si atoms. The contact electrode includes an alloy film made of an alloy containing Al atoms and at least any of Si atoms and Ti atoms. The contact electrode is annealed such that the silicon carbide substrate and the contact electrode establish ohmic connection with each other. Thus, in a case where a contact electrode having Al atoms is employed, insulation reliability of the insulating film can be improved.

Abstract: An integrated circuit device is described that includes a 3D memory comprising a plurality of self-aligned stacks of word lines orthogonal to and interleaved with a plurality of self-aligned stacks of bit lines. Data storage structures such as dielectric charge storage structures, are provided at cross points between word lines and bit lines in the plurality of self-aligned stacks of word lines interleaved with the plurality of self-aligned stacks of bit lines.

Abstract: A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.

Abstract: A surface-emitting semiconductor laser device is provided that includes an edge-emitting laser formed in various layers of semiconductor material disposed on a semiconductor substrate, a polymer material disposed on the substrate laterally adjacent the layers in which the edge-emitting laser is formed, a diffractive or refractive lens formed in or on an upper surface of the polymer material, a side reflector formed on an angled side reflector facet of the polymer material generally facing an exit end facet of the laser, and a lower reflector disposed on the substrate beneath the polymer material. Laser light passes out of the exit end facet and propagates through the polymer material before being reflected by the side reflector toward the lower reflector. The laser light is then re-reflected by the lower reflector towards the lens, which directs the laser light out the device in a direction that is generally normal to the upper surface of the substrate.

Abstract: Methods for fabricating a metal silicide layer and for fabricating a semiconductor device having such a metal silicide layer are provided wherein, in an embodiment, the method includes the steps of forming a metal layer on a substrate, performing a first thermal process on the substrate to allow the substrate and the metal layer to react with react other to form a first pre-metal silicide layer, removing an unreacted portion of the metal layer, and performing a second thermal process on the substrate to change the first pre-metal silicide layer into a second pre-metal silicide layer and then to melt the second pre-metal silicide layer to change the second pre-metal silicide layer into a metal silicide layer.

Abstract: Embodiments of an ohmic contact structure for a Group III nitride semiconductor device and methods of fabrication thereof are disclosed. In one embodiment, the ohmic contact structure has less than or equal to 5%, more preferably less than or equal to 2%, more preferably less than or equal to 1.5%, and even more preferably less than or equal to 1% degradation for 1000 hours High Temperature Soak (HTS) at 300 degrees Celsius. In another embodiment, the ohmic contact structure additionally or alternatively has less than or equal to 10% degradation, more preferably less than or equal to 7.5% degradation, more preferably less than or equal to 6% degradation, more preferably less than or equal to 5% degradation, and even more preferably less than 3% degradation for 1000 hours High Temperature operating Life (HToL) at 225 degrees Celsius and 50 milliamps (mA) per millimeter (mm).

Abstract: In one embodiment, a method of forming a semiconductor device includes forming a well region within a substrate. A plurality of transistors is formed within and/or over the well region. The method further includes forming a first discharge device within the substrate. The first discharge device is coupled to the well region and a low voltage node. During subsequent processing, the first discharge device discharges charge from the well region.

Abstract: A semiconductor substrate includes a via-hole that extends from a first surface to a second surface. An electrode pad layer that serves as the bottom of the via-hole is disposed on the second surface. An insulating layer is formed on the first surface of the semiconductor substrate and the sidewall of the via-hole. A metal layer is formed on the first surface of the semiconductor substrate and the sidewall of the via-hole with the insulating layer interposed therebetween and is directly formed on the bottom of the via-hole. An inclined surface is formed on the sidewall of the via-hole such that the bottom of the via-hole has a smaller opening size than the open end of the via-hole. The inclined surface has asperities.

Abstract: A package substrate includes a core board having a through hole; a circuit layer formed on the core board; a metallic ring disposed on the core board surrounding a contour of the through hole, the metallic ring having opening portions positioned opposite to each other, making the metallic ring having a disconnected manner; and an embedded component installed in the through hole. When the embedded component is deviated in the through hole to allow the electrodes to be in contact with the metallic ring, the electrodes are prevented from coming into contact with the same section of the metallic ring to thereby avoid short circuit.

Abstract: A semiconductor device includes a plurality of first conductive patterns separated by a damascene pattern, a second conductive pattern buried in the damascene pattern, and a spacer including an air gap between the second conductive pattern and the first conductive patterns.

Abstract: A method of manufacturing a semiconductor device, wherein a first substrate where first electrode pads are formed and a second substrate where second electrode pads are formed are stacked and the first electrode pads and the corresponding second electrode pads are electrically connected thereby forming the semiconductor device is disclosed. The method includes steps of performing a first hydrophilic treatment with respect to the first electrode pads; supplying liquid to a surface where the first electrode pads are formed in the first substrate; and placing the second substrate on the first substrate to which the liquid is supplied so that the surface where the first electrode pads are formed opposes a surface where the second electrode pads are formed, thereby aligning the first electrode pads and the second electrode pads by the liquid that gathers in the first electrode pads that have been subject to the first hydrophilic treatment.

Abstract: There are provided a method of fabricating a thin metal film electrode and a thin metal film electrode fabricated by the same. The method of fabricating a thin metal film electrode according to an embodiment of the present invention includes applying a metal paste including a metal powder and a dispersant to a substrate to form a thin metal film; and subjecting the thin metal film to reduction firing in an atmosphere containing an organic acid and an aqueous solution in a ratio ranging from 10:90 to 90:10.