Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a dielectric layer having first and second regions. The first region comprises wide features and the second region comprises narrow features. A depth delta exists between bottoms of the wide and narrow features. A non-conformal layer is formed on the substrate and it lines the wide and narrow trenches in the first and second regions. The non-conformal layer is removed. Removing the non-conformal layer reduces the depth delta between the bottoms of the wide and narrow features in the first and second region.

Abstract: Disclosed herein is a display device, including: a substrate; a circuit part configured to include a drive element formed over the substrate; a planarization insulating layer configured to be formed on the circuit part; an electrically-conductive layer configured to be formed on the planarization insulating layer and include a plurality of first electrodes and an auxiliary interconnect; an aperture-defining insulating layer configured to insulate the plurality of first electrodes from each other and have an aperture through which part of the first electrode is exposed; a plurality of light emitting elements configured to be formed by stacking the first electrode, an organic layer including a light emitting layer, and a second electrode in that order; and a separator configured to be formed by removing the planarization insulating layer at a position surrounding a display area in which the plurality of light emitting elements connected to the drive element are disposed.

Abstract: An organic light emitting display includes data lines and scan lines intersecting each other, a scan driving unit for supplying a scan signal to the scan lines, a data driving unit for supplying a data signal to the data lines, and pixels defined at intersection points of the data and scan lines, each pixel having an organic light emitting diode, a first TFT with an inverted staggered top gate structure and connected to the organic light emitting diode, the first TFT including an oxide semiconductor as an active layer, and a second TFT with an inverted staggered bottom gate structure and configured to receive the scan signal from the scan lines, the second TFT including an oxide semiconductor as an active layer.

Abstract: Techniques for fabricating nanowire/microwire-based solar cells are provided. In one, a method for fabricating a solar cell is provided. The method includes the following steps. A doped substrate is provided. A monolayer of spheres is deposited onto the substrate. The spheres include nanospheres, microspheres or a combination thereof The spheres are trimmed to introduce space between individual spheres in the monolayer. The trimmed spheres are used as a mask to pattern wires in the substrate. The wires include nanowires, microwires or a combination thereof A doped emitter layer is formed on the patterned wires. A top contact electrode is deposited over the emitter layer. A bottom contact electrode is deposited on a side of the substrate opposite the wires.

Abstract: Disclosed herein are a substrate for a package and a method for manufacturing the same. The substrate for the package according to the present invention includes: a base substrate; a photosensitive insulating layer formed on one surface of the base substrate and having a roughness formed on a surface thereof; and a seed layer formed on one surface of the photosensitive insulating layer.

Abstract: A minute electrode, a photoelectric conversion device including the minute electrode, and manufacturing methods thereof are provided. A plurality of parallel groove portions and a region sandwiched between the groove portions are formed in a substrate, and a conductive resin is supplied to the groove portions and the region and is fixed, whereby the groove portions are filled with the conductive resin and the region is covered with the conductive resin. The supplied conductive resin is not expanded outward, and the electrode with a designed width can be formed. Part of the electrode is formed over the region sandwiched between the groove portions, thus, the area of a cross section in the short axis direction can be large, and a low resistance in the long axis direction can be obtained.

Abstract: A through-silicon via fabrication method includes etching a plurality of through holes in a silicon plate. An oxide liner is deposited on the surface of the silicon plate and on the sidewalls and bottom wall of the through holes. A metallic conductor is then deposited in the through holes. In another version, which may be used concurrently with the oxide liner, a silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate.

Abstract: A method of manufacturing a semiconductor device begins by fabricating an n-type metal oxide semiconductor (NMOS) transistor structure on a semiconductor wafer. The method continues by forming an optically reflective layer overlying the NMOS transistor structure, forming a layer of tensile stress inducing material overlying the optically reflective layer, and curing the layer of tensile stress inducing material by applying ultraviolet radiation. Some of the ultraviolet radiation directly radiates the layer of tensile stress inducing material and some of the ultraviolet radiation radiates the layer of tensile stress inducing material by reflecting from the optically reflective layer.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array unit and an alignment mark unit. The cell array unit includes a first memory string, a second memory string and a device isolation insulating layer. The first string is provided on a major surface of a semiconductor layer. The second string is juxtaposed with the first memory string. The device isolation insulating layer partitions the first and second memory strings from each other. The mark unit juxtaposed with the array unit includes a mark unit semiconductor layer and a mark unit insulating layer. The mark unit semiconductor layer is a part of the semiconductor layer. The mark unit insulating layer is juxtaposed with the mark unit semiconductor layer. An upper surface of the mark unit semiconductor layer is included in a plane different from a plane including an upper surface of the mark unit insulating layer.

Abstract: The invention provides a method for manufacturing a semiconductor device that comprises placing a metallic gate layer over a gate dielectric layer where the metallic gate layer has a crystallographic orientation, and re-orienting the crystallographic orientation of the metallic gate layer by subjecting the metallic gate layer to a hydrogen anneal.

Abstract: A method is provided for fabricating a high-K metal gate MOS device. The method includes providing a semiconductor substrate having a surface region, a gate oxide layer on the surface region, a sacrificial gate electrode on the gate oxide layer, and a covering layer on the sacrificial gate electrode, an inter-layer dielectric layer on the semiconductor substrate and the sacrificial gate electrode. The method also includes planarizing the inter-layer dielectric layer to expose a portion of the covering layer atop the sacrificial gate electrode, implanting nitrogen ions into the inter-layer dielectric layer until a depth of implantation is deeper than a thickness of the portion of the covering layer atop the sacrificial gate electrode and polishing the inter-layer dielectric layer to expose a surface of the sacrificial gate electrode, removing the sacrificial gate electrode, and depositing a metal gate.

Abstract: A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconducive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy.

Abstract: A semiconductor substrate having a first lateral dimension is combined with a flexible film piece having a second lateral dimension by arranging the semiconductor substrate in a recess of the film piece. The semiconductor substrate has circuit structures produced using lithography process steps. After the semiconductor substrate has been arranged in the recess of the film piece, a patterned layer of an electrically conductive material is produced above the semiconductor substrate and the film piece using lithography process steps. The patterned layer extends from the semiconductor substrate up to the flexible film piece and forms a number of electrically conductive contact tracks between the semiconductor substrate and the film piece.

Abstract: A slurry composition for chemical mechanical polishing, including 0.1% to 20% by weight of an aminosilane-surface treated polishing agent; 0.001% to 5% by weight of an additive selected from amino acids, amino acid derivatives, salts thereof, and combinations thereof; 0.0001% to 0.5% by weight of a corrosion inhibitor; and 0.01% to 5% by weight of an oxidizing agent, with the balance being a solvent, is provided. The slurry composition for chemical mechanical polishing has a conspicuously high polishing rate for silicon oxide films, is capable of selectively preventing the removal of silicon nitride films, does not cause an imbalance in polishing, gives an excellent degree of planarization, has excellent stability over time and dispersion stability, causes less generation of particles and scratches, and produces very satisfactory polished surfaces of barrier metal films and oxide films.

Abstract: Methods of forming a semiconductor structure including a semiconductor nanowire or epitaxial semiconductor material which extends from at least a surface of source region and the drain region are provided. The methods include converting an upper portion of the source region and the drain region and the semiconductor nanowire or epitaxial semiconductor material into a continuous metal semiconductor alloy. The continuous metal semiconductor alloy includes a lower portion that is contained within an upper surface of each of the source region and the drain region, and a vertical pillar portion extending upwardly from the lower portion.

Abstract: Electrical interconnects for integrated circuits and methods of fabrication of interconnects are provided. Devices are provided comprising copper interconnects having metallic liner layers comprising silver and a second component, such as, lanthanum, titanium, tungsten, zirconium, antimony, or calcium. Methods include providing a substrate having a trench or via formed therein, forming a silver alloy layer, comprising silver and a second component selected from the group consisting of lanthanum, titanium, tungsten, zirconium, antimony, and calcium, onto surfaces of the feature, depositing a copper seed layer, and depositing copper into the feature.

Abstract: Generally, the subject matter disclosed herein relates to sophisticated semiconductor devices and methods for forming the same, wherein the pitch between adjacent gate electrodes is aggressively scaled, and wherein self-aligning contact elements may be utilized to avoid the high electrical resistance levels commonly associated with narrow contact elements formed using typically available photolithography techniques. One illustrative embodiment includes forming first and second gate electrode structures above a semiconductor substrate, then forming a first layer of a first dielectric material adjacent to or in contact with the sidewalls of each of the first and second gate electrode structures.

Abstract: This invention provides a method for chip scale package and a chip scale package structure. The chip scale package structure includes: a semiconductor substrate, on which sets a plurality of contact bonding pads being connected with semiconductor devices; and a plurality of bumps respectively attached to all of the contact bonding pads. The semiconductor substrate is divided into several regions according to different distances from a central point. The contact bonding pads and the bumps in the region which is closest to the central point are the smallest, while the contact bonding pads and the bumps in the region which is farthest to the central point are the largest. The invention effectively improves the situation that the bumps at the edge tend to flake off easily; in addition, it avoids short-circuit caused by bridging between the bumps.

Abstract: A contact structure and a method of forming the contact structure. The structure includes: a silicide layer on and in direct physical contact with a top substrate surface of a substrate; an electrically insulating layer on the substrate; and an aluminum plug within the insulating layer. The aluminum plug has a thickness not exceeding 25 nanometers in a direction perpendicular to the top substrate surface. The aluminum plug extends from a top surface of the silicide layer to a top surface of the insulating layer. The aluminum plug is in direct physical contact with the top surface of the silicide layer and is in direct physical contact with the silicide layer. The method includes: forming the silicide layer on and in direct physical contact with the top substrate surface of the substrate; forming the electrically insulating layer on the substrate; and forming the aluminum plug within the insulating layer.

Abstract: A method for forming conductive vias in a substrate of a semiconductor device component includes forming one or more holes, or apertures or cavities, in the substrate so as to extend only partially through the substrate. A barrier layer, such as an insulative layer, may be formed on surfaces of each hole. Surfaces within each hole may be coated with a seed layer, which facilitates adhesion of conductive material within each hole. Conductive material is introduced into each hole. Introduction of the conductive material may be effected by deposition or plating. Alternatively, conductive material in the form of solder may be introduced into each hole.

Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral circuit region, and an active region defined by a device isolation film, at least one dummy gate formed over the active region to expose a center part and both ends of the active region, a bit line contact plug formed between the dummy gates so as to be coupled to the center part of the active region, and a storage node contact plug that is spaced apart from the bit line contact plug by the dummy gate and is coupled to both ends of the active region. As a result, the problem that the storage node contact hole is not open in the semiconductor device can be solved, resulting in improved semiconductor device characteristics.

Abstract: An embedded component device includes an electronic component including an electrical contact, an upper patterned conductive layer, a dielectric layer between the upper patterned conductive layer and the electronic component, a first electrical interconnect, a lower patterned conductive layer, a conductive via, and a second electrical interconnect. The dielectric layer has a first opening exposing the electrical contact, and a second opening extending from the lower patterned conductive layer to the upper patterned conductive layer. The first electrical interconnect extends from the electrical contact to the upper patterned conductive layer, and fills the first opening. The second opening has an upper portion exposing the upper patterned conductive layer and a lower portion exposing the lower patterned conductive layer. The conductive via is located at the lower portion of the second opening. The second electrical interconnect fills the upper portion of the second opening.

Abstract: Ohmic cathode electrodes are formed on the backside of nonpolar m-plane (1-100) and semipolar (20-21) bulk gallium nitride (GaN) substrates. The GaN substrates are thinned using a mechanical polishing process. For m-plane GaN, after the thinning process, dry etching is performed, followed by metal deposition, resulting in ohmic I-V characteristics for the contact. For (20-21) GaN, after the thinning process, dry etching is performed, followed by metal deposition, followed by annealing, resulting in ohmic I-V characteristics for the contact as well.

Abstract: Embodiments of methods and apparatus are disclosed for obtaining an imaging array or a digital radiographic system including a plurality of pixels where at least one pixel can include a scan line, a bias line, a switching element including a first terminal, a second terminal, and a control electrode where the control electrode is electrically coupled to the scan line; and a photoelectric conversion element including a first terminal electrically coupled to the bias line and a second terminal electrically coupled to the first terminal of the switching element, and a signal storage element formed in the same layers as the scan line, bias line, the data line, the switching element and the photoelectric conversion element. An area of one terminal of the signal storage element can be larger than a surface area of the pixel.

Abstract: A method for fabricating a semiconductor device includes etching a substrate to form a plurality of bodies isolated by a first trench, forming a buried bit line gap-filling a portion of the first trench, etching the top portions of the bodies to form a plurality of pillars isolated by a plurality of second trenches extending across the first trench, forming a passivation layer gap-filling a portion of the second trenches, forming an isolation layer that divides each of the second trenches into isolation trenches over the passivation layer, and filling a portion of the isolation trenches to form a buried word line extending in a direction crossing over the buried bit line.

Abstract: A method for restricting lateral encroachment of the metal silicide into the channel region, comprising: providing a semiconductor substrate, a gate stack being formed on the semiconductor substrate, a source region being formed in the semiconductor on one side of the gate stack, and a drain region being formed in the semiconductor substrate on the other side of the gate stack; forming a sacrificial spacer around the gate stack and on the semiconductor substrate; depositing a metal layer for covering the semiconductor substrate, the gate stack and the sacrificial spacer; performing a thermal treatment on the semiconductor substrate, thereby causing the metal layer to react with the sacrificial spacer and the semiconductor substrate in the source region and the drain region; removing the sacrificial spacer, reaction products of the sacrificial spacer and the metal layer, and a part of the metal layer which does not react with the sacrificial spacer.

Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding. The method includes fabricating a semiconductor device in epitaxial layers on a surface of a silicon carbide substrate and with at least one metal contact for the device on the uppermost surface of the epitaxial layer. The opposite surface of the substrate is then ground and polished until it is substantially transparent. The polished surface of the silicon carbide substrate is then masked to define a predetermined location for at least one via that is opposite the device metal contact and etching the desired via in steps. The first etching step etches through the silicon carbide substrate at the desired masked location until the etch reaches the epitaxial layer. The second etching step etches through the epitaxial layer to the device contacts. Finally, the via is metallized.

Abstract: Silicon wafer processing system, apparatus and method of doping silicon wafers with hot concentrated acid dopant compositions for forming p-n junction and back contact layers during processing into PV solar cells. Highly concentrated acid dopant is atomized with pressurized gas and heated in the range of 80-200° C., then introduced into a concentrated acid vapor processing chamber to apply vapor over 1.5-6 min to wafers moving horizontally on a multi-lane conveyor system through the processing chamber. The wafers are dried and forwarded to a diffusion furnace. An optional UV pre-treatment assembly pre-conditions the wafers with UV radiation prior to dopant application, and doped wafers may be post-treated in a UV treatment module before being fired. The wafers may be cooled in the processing chamber. Post-firing, the wafers exhibit excellent sheet resistance in the 60-95 ?/sq range, and are highly uniform across the wafers and wafer-to-wafer.

Abstract: A chip package includes: a substrate; a drain and a source regions located in the substrate; a gate located on or buried in the substrate; a drain conducting structure, a source conducting structure, and a gate conducting structure, disposed on the substrate and electrically connected to the drain region, the source region, and the gate, respectively; a second substrate disposed beside the substrate; a second drain and a second source region located in the second substrate, wherein the second drain region is electrically connected to the source region; a second gate located on or buried in the second substrate; and a second source and a second gate conducting structure disposed on the second substrate and electrically connected to the second source region and the second gate, respectively, wherein terminal points of the drain, the source, the gate, the second source, and the second gate conducting structures are substantially coplanar.

Abstract: A manufacturing method of a MOS device with memory function is provided, which includes: providing a semiconductor substrate, a surface of the semiconductor substrate being covered by a first dielectric layer, a metal interconnect structure being formed in the first dielectric layer; forming a second dielectric layer overlying a surface of the first dielectric layer and the metal interconnect structure; forming an opening in the second dielectric layer, a bottom of the opening revealing the metal interconnect structure; forming an alloy layer at the bottom of the opening, material of the alloy layer containing copper and other metal; and performing a thermal treatment to the alloy layer and the metal interconnect structure to form, on the surface of the metal interconnect structure, a compound layer containing oxygen element. The compound layer containing oxygen element and the MOS device formed in the semiconductor substrate constitute a MOS device with memory function.

Abstract: A method for forming a semiconductor device includes the following processes. An insulating film is formed over a semiconductor substrate. A hole is formed in the insulating film. A film including ZrAlO is formed over the insulating film and in the hole. Forming the film including ZrAlO may include, but is not limited to, the following processes. A first precursor including zirconium and a second precursor including aluminum are supplied into a reaction chamber at a supply amount ratio of the first precursor to the second precursor in the range from 2.5 to 3.5. The first precursor and the second precursor are exhausted from the reaction chamber. An oxidant is supplied into the reaction chamber to oxidize zirconium and aluminum. The oxidant is exhausted from the reaction chamber.

Abstract: Transistor devices can be fabricated with an integrated diode using a self-alignment. The device includes a doped semiconductor substrate having one or more electrically insulated gate electrodes formed in trenches in the substrate. One or more body regions are formed in a top portion of the substrate proximate each gate trench. One or more source regions are formed in a self-aligned fashion in a top portion of the body regions proximate each gate trench. One or more thick insulator portions are formed over the gate electrodes on a top surface of the substrate with spaces between adjacent thick insulator portions. A metal is formed on top of the substrate over the thick insulator portions. The metal forms a self-aligned contact to the substrate through the spaces between the thick insulator portions. An integrated diode is formed under the self-aligned contact.

Abstract: Embodiments disclosed herein generally relate to an apparatus and a method for placing a substrate substantially flush against a substrate support in a processing chamber. When a large area substrate is placed onto a substrate support, the substrate may not be perfectly flush against the substrate support due to gas pockets that may be present between the substrate and the substrate support. The gas pockets can lead to uneven deposition on the substrate. Therefore, pulling the gas from between the substrate and the support may pull the substrate substantially flush against the support. During deposition, an electrostatic charge can build up and cause the substrate to stick to the substrate support. By introducing a gas between the substrate and the substrate support, the electrostatic forces may be overcome so that the substrate can be separated from the susceptor with less or no plasma support which takes extra time and gas.

Abstract: A method of flattening a substrate includes forming a metal layer on an upper surface of a substrate, forming a photoresist layer covering the substrate and the metal layer, radiating light to the photoresist layer, through a lower surface of the substrate opposite to the upper surface, exposing the metal layer by developing the photoresist layer, exposing the upper surface of the substrate by etching the metal layer, etching the exposed upper surface of the substrate, and removing the photoresist layer.

Abstract: A combinatorial processing chamber is provided. The combinatorial processing chamber is configured to isolate a radial portion of a rotatable substrate support, which in turn is configured to support a substrate. The chamber includes a plurality of clusters process heads in one embodiment. An insert having a base plate disposed between the substrate support and the process heads defines a confinement region for a deposition process in one embodiment. The base plate has an opening to enable access of the deposition material to the substrate. Through rotation of the substrate and movement of the opening, multiple regions of the substrate are accessible for performing combinatorial processing on a single substrate.

Abstract: A vertical semiconductor device includes a first active pillar vertically protruded from a semiconductor substrate; a first vertical gate connected to at least one side of the first active pillar and formed along a direction that crosses a buried bit line; and a first body line connected to at least one side of the first active pillar which is not connected to the first vertical gate.

Abstract: A MEMS resonator according to the invention includes: a substrate; a first electrode formed above the substrate; and a second electrode having a supporting portion which is formed above the substrate and a beam portion which is supported by the supporting portion and arranged above the first electrode, wherein the beam portion has, in plan view, a shape in which the width monotonically decreases in a direction from the supporting portion toward a tip of the beam portion in a region overlapping the first electrode.

Abstract: An electrical connection includes a first wire bonded to adjacent bond pads proximate to an edge of a die and a second wire having one end bonded to a die bond pad distal to the die edge and a second end bonded to a lead finger of a lead frame or a connection pad of a substrate. The second wire crosses and is supported by the first wire. The first wire acts as a brace that prevents the second wire from touching the edge of the die. The first wire also prevents the second wire from excessive lateral movement during encapsulation.

Abstract: A method of manufacturing a wiring structure and a semiconductor device, the method of manufacturing a wiring structure including forming a first insulating interlayer on a substrate; forming a contact plug in an opening in the first insulating interlayer; forming a second insulating interlayer on the contact plug and the first insulating interlayer; removing a portion of the second insulating interlayer to form an opening therethrough such that the opening exposes the contact plug; filling a portion of the opening to form a wiring such that the wiring is electrically connected to the contact plug; and forming a diffusion barrier layer pattern on the wiring such that the diffusion barrier layer pattern fills a remaining portion of the opening.

Abstract: A manufacturing method of a semiconductor structure includes providing a substrate having an upper surface and a bottom surface. First openings are formed in the substrate. An oxidization process is performed to oxidize the substrate having the first openings therein to form an oxide-containing material layer, and the oxide-containing material layer has second openings therein. A conductive material is filled into the second openings to form conductive plugs. A first device layer is formed a first surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs. A second device layer is formed on a second surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs.

Abstract: A method of manufacturing a semiconductor device includes forming a lower film including a cell region and a peripheral circuit region, forming a first sacrificial film on the lower film, the first sacrificial film having trenches in the cell region, forming a second sacrificial pattern on the first sacrificial film, the second sacrificial pattern having line-shaped patterns spaced apart from each other and crossing the trenches in the cell region, and the second sacrificial pattern covering a top surface of the first sacrificial film in the peripheral circuit region, and patterning the first sacrificial film to form upper holes in portions of the trenches exposed by the second sacrificial pattern.

Abstract: A manufacturing method of a semiconductor structure includes providing a substrate having an upper surface and a bottom surface. First openings are formed in the substrate. An oxidization process is performed to oxidize the substrate having the first openings therein to form an oxide-containing material layer, and the oxide-containing material layer has second openings therein. A conductive material is filled into the second openings to form conductive plugs. A first device layer is formed a first surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs. A second device layer is formed on a second surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs.

Abstract: An electronic device includes: a vibrator disposed within a cavity on a substrate and electrically driven; an enclosure wall which has electric conductivity and sections the cavity from an insulation layer surrounding the circumference of the cavity; a first wiring and a second wiring which connect with the vibrator and penetrate the enclosure wall; and a liquid flow preventing portion disposed at the position where the first wiring and the second wiring penetrate the enclosure wall to prevent flow of etchant dissolving the insulation layer from the cavity toward the insulation layer and insulate the first wiring and the second wiring from the enclosure wall.

Abstract: An ohmic electrode for a p-type SiC semiconductor, and a method of forming the ohmic electrode. The ohmic electrode has an ohmic electrode layer, which has an amorphous structure and which is made of a Ti(1?x?y)Si(s)C(y) ternary film of which a composition ratio is within a composition range that is surrounded by two lines and two curves expressed by an expression x=0 (0.35?y?0.5), an expression y=?1.120x+0.5200 (0.1667?x?0.375), an expression y=1.778(x?0.375)2+0.1 (0?x?0.375) and an expression y=?2.504x2?0.5828x+0.5 (0?x?0.1667) and that excludes the line expressed by the expression x=0. The ohmic layer is directly laminated on a surface of a p-type SiC semiconductor.

Abstract: A semiconductor structure and a process thereof are provided. The semiconductor structure includes a semiconductor wafer having a first surface and a second surface opposite to the first surface, through silicon vias and a crack stopping slot. The through silicon vias are embedded in the semiconductor wafer and connected between the first surface and the second surface. The crack stopping slot is located in the periphery of the second surface of the semiconductor wafer. The depth of the crack stopping slot is less than or equal to the thickness of the semiconductor wafer. The process firstly provides a semiconductor wafer having through silicon vias. Then, the aforementioned crack stopping slot is formed at a back side of the semiconductor wafer opposite to the first surface. Next, the semiconductor wafer is thinned from the back side to expose a second end of each through silicon via.

Abstract: In a semiconductor diamond device, there is provided an ohmic electrode that is chemically, and thermally stable, and is excellent in respect of low contact resistance, and high heat resistance. A nickel-chromium alloy, or a nickel-chromium compound, containing Ni, and Cr such as Ni6Cr2 or Ni72Cr18Si10, which is chemically and thermally stable, is formed on a semiconductor diamond by a sputtering process and so forth, to thereby obtain the semiconductor diamond device provided with an excellent ohmic electrode. If heat treatment is applied after forming the nickel-chromium alloy, or the nickel-chromium compound, it is improved in characteristics.

Abstract: According to an embodiment, a method for manufacturing a semiconductor device is provided. The method includes providing a mask layer which is used as an implantation mask when forming a doping region and which is used as an etching mask when forming an opening and a contact element formed in the opening. The contact element is in contact with the doping region.

Abstract: Provided are a semiconductor film including silicon microstructures formed at high density, and a manufacturing method thereof. Further, provided are a semiconductor film including silicon microstructures whose density is controlled, and a manufacturing method thereof Furthermore, a power storage device with improved charge-discharge capacity is provided. A manufacturing method in which a semiconductor film with a silicon layer including silicon structures is formed over a substrate with a metal surface is used. The thickness of a silicide layer formed by reaction between the metal and the silicon is controlled, so that the grain sizes of silicide grains formed at an interface between the silicide layer and the silicon layer are controlled and the shapes of the silicon structures are controlled. Such a semiconductor film can be applied to an electrode of a power storage device.

Abstract: Provided is a method of forming a method of forming a titanium dioxide (TiO2) array using a zinc oxide (ZnO) template. In the method, polymer nanopatterns are formed on the substrate, and monomolecular monolayers are formed between the polymer nanopatterns on the substrate. A seed layer pattern is formed between the monomolecular monolayers on the substrate, and a zinc oxide template is formed by growing zinc oxide on the seed layer.

Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. Also, a bond-on-lead or bond-on-narrow pad or bond on a small area of a contact pad interconnection includes such tapering flip chip interconnects. Also, methods for making the interconnect structure include providing a die having interconnect pads, providing a substrate having interconnect sites on a patterned conductive layer, providing a bump on a die pad, providing a fusible electrically conductive material either at the interconnect site or on the bump, mating the bump to the interconnect site, and heating to melt the fusible material.