Abstract: Devices and methods for forming a self-aligned airgap interconnect structure includes etching a conductive layer to a substrate to form conductive structures with patterned gaps and filling the gaps with a sacrificial material. The sacrificial material is planarized to expose a top surface of the conductive layer. A permeable cap layer is deposited over the conductive structure and the sacrificial material. Self-aligned airgaps are formed by removing the sacrificial material through the permeable layer.

Abstract: Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.

Abstract: A semiconductor device includes a substrate and a gate stack disposed on the substrate. An upper layer of the gate stack is a metal gate conductor and a lower layer of the gate stack is a gate dielectric. A gate contact is in direct contact with the metal gate conductor.

Abstract: A semiconductor structure, and method of forming a semiconductor structure, that includes a gate structure on a semiconductor substrate, in which the gate structure includes a gate conductor and a high-k gate dielectric layer. The high-k gate dielectric layer is in contact with the base of the gate conductor and is present on the sidewalls of the gate conductor for a dimension that is less than ¼ the gate structure's height. The semiconductor structure also includes source regions and drain regions present in the semiconductor substrate on opposing sides of the gate structure.

Abstract: A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.

Abstract: Methods of incorporating impurities into materials can be useful in non-volatile memory devices as well as other integrated circuit devices. Various embodiments provide for incorporating impurities into a material using a discontinuous mask.

Abstract: A method for forming an n-type contact electrode comprising an n-type nitride semiconductor such as AlxInyGazN (with x, y, and z being rational numbers that sum to 1.0 and fulfill the relations 0<x?1.0, 0?y?0.1, and 0?z<1.0) includes: a step in which a first electrode metal layer including at least one metal selected from titanium, vanadium, and tantalum is formed on a layer of the aforementioned n-type semiconductor and then heat-treated at a temperature between 800° C. and 1200° C.; and a step in which a second electrode metal layer is formed on top of the first electrode metal layer and then heat-treated at a temperature between 700° C. and 1000° C. The second electrode metal layer contains a layer comprising a metal, such as aluminum, that has a work function between 4.0 and 4.8 eV and a resistivity between 1.5×10?6 ?·cm and 4.0×10?6 ?·cm.

Abstract: A method of forming integrated circuits includes forming a mask layer over a gate electrode line, wherein the gate electrode line is over a well region of a semiconductor substrate; forming an opening in the mask layer, wherein a portion of the gate electrode line and a well pickup region of the well region are exposed through the opening; and removing the portion of the gate electrode line through the opening.

Abstract: A circuit device is configured with robust circuit connectors. In connection with various example embodiments, an integrated circuit device includes one or more via network layers below a bond pad contact, connecting the bond pad contact with one or more underlying metal layers. Each via network layer includes a plurality of via strips extending about parallel to the bond pad contact and in different directions to structurally support the bond pad contact.

Abstract: A method for forming a semiconductor device includes forming a first field effect transistor (FET) and a second FET on a substrate, the first FET comprising a first interfacial oxide layer, and the second FET comprising a second interfacial oxide layer; encapsulating the first interfacial oxide layer of the first FET; and performing lateral oxidation of the second interfacial oxide layer of the second FET, wherein the lateral oxidation of the second interfacial oxide layer of the second FET converts a portion of the substrate located underneath the second FET into additional interfacial oxide.

Abstract: A method for forming a semiconductor device with improved electromigration (EM) and stress migration (SM) properties. The method includes providing a planarized patterned substrate containing a copper (Cu) metal surface and a low-k dielectric layer surface, selectively depositing a metal cap layer on the Cu metal surface, and modifying the metal cap layer by exposing the metal cap layer to a process gas containing ammonia (NH3) gas without plasma excitation. The method further includes forming a dielectric barrier film on the modified metal cap layer and on the dielectric layer surface, and exposing the dielectric barrier film to a gaseous oxidizing environment, where the dielectric barrier film and the modified metal cap layer prevent oxidation of the Cu metal surface when the dielectric barrier film is exposed to the gaseous oxidizing environment.

Abstract: The disclosure provides methods and structures for preventing exposing polysilicon layer and silicon substrate on the substrate backside to polysilicon etching chemistry during removal of the dummy polysilicon layer in replacement gate structures. A thermal deposition process or processes are used to deposit a dielectric layer for offset spacers and/or a contact etch stop layer (CESL) to cover the polysilicon layer on the substrate backside. Such mechanisms reduce or eliminate particles originated at bevel of substrate backside, due to complete removal of the polysilicon layer at the backside bevel and the resultant etching of silicon substrate.

Abstract: Processes for metal fill in replacement metal gate integration schemes and resultant devices are provided herein. The method includes forming a dummy gate on a semiconductor substrate. The dummy gate includes forming a metal layer between a first material and a second material. The method further includes partially removing the dummy gate to form an opening bounded by a spacer material. The method further includes forming a recess in the spacer material to widen a portion of the opening. The method further includes removing a remaining portion of the dummy gate through the opening to form a trench having the recess forming an upper portion thereof. The method further includes filling the trench and the recess with a replacement metal gate stack.

Abstract: A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are etched to partially remove the etch mask pattern from the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region.

Abstract: A manufacturing method of a metal gate structure includes providing a substrate having at least a first metal oxide layer formed thereon, and transferring the surface of the first metal oxide layer into a second metal oxide layer. The first metal oxide layer includes a metal oxide (M1Ox) of a first metal (M1) and the second metal oxide layer includes a metal oxide ((M1M2Oy) of the first metal and a second metal (M2).

Abstract: The present invention provides a method of fabricating a semiconductor device including forming stop layers (32) that include silicon oxy-nitride films above a semiconductor substrate, forming a cover film (34) between and on the stop layers, in which a top surface of the cover film above a region between the stop layers is higher than top surfaces of the stop layers, and polishing the cover film to the stop layers by using ceria slurry, and also provides a semiconductor device including metal layers (30) provided above a semiconductor substrate, silicon oxy-nitride films (32) provided on the metal layers, and an embedded layer (36) provided between the metal layers to have a top surface substantially coplanar with top surfaces of the silicon oxy-nitride films. According to the present invention, it is possible to provide a semiconductor device having a film of excellent planarization on a surface thereof and fabrication method therefor.

Abstract: Embodiments of the present invention provide a method of forming a semiconductor structure. The method includes creating an opening inside a dielectric layer, the dielectric layer being formed on top of a substrate and the opening exposing a channel region of a transistor in the substrate; depositing a work-function layer lining the opening and covering the channel region; forming a gate conductor covering a first portion of the work-function layer, the first portion of the work-function layer being on top of the channel region; and removing a second portion of the work-function layer, the second portion of the work-function layer surrounding the first portion of the work-function layer, wherein the removal of the second portion of the work-function layer insulates the first portion of the work-function layer from rest of the work-function layer.

Abstract: The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing an O2 flash while shaping gate spacers, and then cleaning and applying a second application of Aqua Regia. Embodiments include sputter depositing a layer of Ni/Pt on a semiconductor substrate, annealing the Ni/Pt layer, wet stripping unreacted Ni, annealing the Ni stripped Ni/Pt layer, stripping unreacted Pt from the annealed Ni/Pt layer, e.g., with Aqua Regia, treating the Pt stripped Ni/Pt layer with an oxygen plasma, cleaning the Ni/Pt layer, and stripping unreacted Pt from the cleaned Ni/Pt layer, e.g., with a second application of Aqua Regia.

Abstract: According to the present invention, a thin film having a desired thickness is formed on an inner sidewall of a step with excellent step coverage in a film forming step and an etching step at least once, respectively. In an embodiment of the present invention, a target material is deposited on a substrate (17) having a concave step (31, 32) having an opening width or opening diameter of 3 ?m or less and an aspect ratio of 1 or more. At this time, a film forming method according to the present invention has a first step of depositing a thin film onto a bottom (33) of the step (31, 32) and a second step of forming a film on an inner sidewall (34) of the step (31, 32) by re-sputtering the thin film deposited on the bottom (33) and the pressure in a process chamber in the second step is set lower than that in the process chamber in the first step and the ratio of anode power to cathode power in the second step is set greater than the power ratio in the first step.

Abstract: A heat dissipation structure for an electronic device includes a body having a first surface and a second surface opposite to the first surface. A silicon-containing insulating layer is disposed on the first surface of the body. An ultrananocrystalline diamond film is disposed on the silicon-containing insulating layer. A first conductive pattern layer is disposed on the silicon-containing insulating layer and enclosed by the ultrananocrystalline diamond film, wherein the ultrananocrystalline diamond film and the first conductive pattern layer do not overlap with each other as viewed from a top-view perspective. A method for fabricating a heat dissipation structure for an electronic device and an electronic package having the heat dissipation structure are also disclosed.

Abstract: A test structure, a method of employing the test structure, and a method of manufacturing the test structure are provided for measuring a contact resistance between a silicide and a semiconductor. The test structure includes a set of silicide layers separated from one another and upon which electrodes from a set of electrodes are placed. One pair of electrodes is employed to force a constant current through the silicide layers and a diffusion layer of a semiconductor substrate of the test structure. Another pair of electrodes determines a potential drop between the silicide layers and the diffusion layer. Based upon the constant current and the potential drop determined, a contact resistance is extracted.

Abstract: A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away.

Abstract: Embodiments of methods for fabricating the semiconductor devices are provided. The method includes forming a metal silicide in an upper portion of a gate electrode structure and in an active semiconductor region laterally adjacent to the gate electrode structure. A first portion of the metal silicide formed in the upper portion of the gate electrode structure is removed.

Abstract: According to certain embodiments, a silicide layer is formed after the fabrication of a functional gate electrode using a gate-last scheme. An initial semiconductor structure has at least one impurity regions formed on a semiconductor substrate, a sacrifice film formed over the impurity region, an isolation layer formed over the sacrifice film and a dielectric layer formed over the isolation film. A via is patterned into the dielectric layer of the initial semiconductor structure and through the thickness of the isolation layer such that a contact opening is formed in the isolation layer. The sacrifice film underlying the isolation layer is then removed leaving a void space underlying the isolation layer. Then, a metal silicide precursor is placed within the void space, and the metal silicide precursor is converted to a silicide layer through an annealing process.

Abstract: Disclosed are a resistive random-access memory (ReRAM) based on resistive switching using a resistance-switchable conductive filler and a method for preparing the same. When a resistance-switchable conductive filler prepared by coating a conductive filler with a material whose resistance is changeable is mixed with a dielectric material, the dielectric material is given the resistive switching characteristics without losing its inherent properties. Therefore, various resistance-switchable materials having various properties can be prepared by mixing the resistance-switchable conductive filler with different dielectric materials. The resulting resistance-switchable material shows resistive switching characteristics comparable to those of the existing metal oxide film-based resistance-switchable materials. Accordingly, a ReRAM device having the inherent properties of a dielectric material can be prepared using the resistance-switchable conductive filler.

Abstract: A method of fabricating a vertical light emitting diode including: growing a low doped first semiconductor layer on a sacrificial substrate; forming an aluminum layer on the low doped first semiconductor; forming an AAO layer having a large number of holes formed therein by anodizing the aluminum layer; etching and patterning the low doped first semiconductor layer using the aluminum layer as a shadow mask, thereby forming grooves; removing the aluminum layer remaining; sequentially forming a high doped first semiconductor layer, an active layer and a second semiconductor layer on the low doped first semiconductor layer with the grooves; forming a metal reflective layer and a conductive substrate on the second semiconductor layer; separating the sacrificial substrate; and forming an electrode pad on the other surface of the low doped first semiconductor layer, the electrode pad filled in the grooves and in ohmic contact with the high doped first semiconductor.

Abstract: Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip that has a first conductor pad and a passivation structure. A second conductor pad is fabricated around but not in physical contact with the first conductor pad to leave a gap. The second conductor pad is adapted to protect a portion of the passivation structure.

Abstract: A method for forming a gate stack of a semiconductor device comprises depositing a gate oxide layer on a channel region of a semiconductor substrate using chemical vapor deposition, atomic layer deposition or molecular layer deposition, depositing a nitride layer on the gate oxide layer, oxidizing the deposited nitride layer, depositing a high-K dielectric layer on the oxidized nitride layer, and forming a metal gate on the high-K dielectric layer.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, plural stacked bodies, an insulating side wall, an interlayer insulating layer, and a contact. Plural stacked bodies are provided on the semiconductor substrate so as to extend in parallel to one another. Each of the plural stacked bodies includes a gate insulating layer, a gate electrode, and an insulating layer. The insulating side wall covers a side face of the gate electrode in an upper end part thereof and does not cover the side face of the gate electrode in a part thereof contacting the gate insulating layer. The interlayer insulating layer is provided on the semiconductor substrate and covers the stacked bodies. The contact is provided in the interlayer insulating layer between the stacked bodies and is connected to the semiconductor substrate.

Abstract: When forming complex metallization systems on the basis of copper, the very last metallization layer may receive contact regions on the basis of copper, the surface of which may be passivated on the basis of a dedicated protection layer, which may thus allow the patterning of the passivation layer stack prior to shipping the device to a remote manufacturing site. Hence, the protected contact surface may be efficiently re-exposed in the remote manufacturing site on the basis of an efficient non-masked wet chemical etch process.

Abstract: Semiconductor devices are formed with a dielectric stack by forming an UV reflecting layer between cured and uncured ULK layers during BEOL processing. Embodiments include forming a first ultra low-k (ULK) layer on a semiconductor element, curing the first ULK layer, forming an ultraviolet (UV) reflecting layer on the first ULK layer, forming a second ULK layer on the UV reflecting layer, and irradiating the second ULK layer with UV light.

Abstract: A laser system may include a first portion of laser host material adapted for amplification of laser radiation and a second portion of laser host material surrounding the first portion which may be adapted for suppression of ASE. The first portion of laser host material and the second portion of laser host material may be respectively doped at a different predetermined concentration of laser ions. A heat exchanger may be provided to dissipate heat from the first portion and the second portion.

Abstract: Non-volatile storage elements having a PN floating gate are disclosed herein. The floating gate may have a P? region near the tunnel oxide, and may have an N+ region near the control gate. In some embodiments, a P? region near the tunnel oxide helps provide good data retention. In some embodiments, an N+ region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also erasing the non-volatile storage elements may be efficient. In some embodiments, having a P? region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.

Abstract: A semiconductor process having a dielectric layer including metal oxide is provided. The semiconductor process includes: A substrate is provided. A dielectric layer including metal oxide is formed on the substrate, wherein the dielectric layer has a plurality of oxygen-related vacancies. A first oxygen-importing process is performed to fill the oxygen-related vacancies with oxygen. Otherwise, three MOS transistor processes are also provided, each of which has a gate dielectric layer including a high dielectric constant, and a first oxygen-importing process is performed to fill the oxygen-related vacancies with oxygen.

Abstract: A layered structure and semiconductor device and methods for fabricating a layered structure and semiconductor device. The layered structure includes: a base layer including a material containing titanium nitride, tantalum nitride, or a combination thereof; a conductive layer including a material containing: tantalum aluminum nitride, titanium aluminum nitride, tantalum silicon nitride, titanium silicon nitride, tantalum hafnium nitride, titanium hafnium nitride, hafnium nitride, hafnium carbide, tantalum carbide, vanadium nitride, niobium nitride, or any combination thereof; and a tungsten layer. The semiconductor device includes: a semiconductor substrate; a base layer; a conductive layer; and a tungsten layer.

Abstract: A gate structure and a method for fabricating the same are described. A substrate is provided, and a gate dielectric layer is formed on the substrate. The formation of the gate dielectric layer includes depositing a silicon nitride layer on the substrate by simultaneously introducing a nitrogen-containing gas and a silicon-containing gas. A gate is formed on the gate dielectric layer, so as to form the gate structure.

Abstract: A manufacturing method of a semiconductor load board is disclosed. The manufacturing method includes a first conductive layer forming step, a first patterning step, a dielectric layer forming step, a drilling step, a second conductive layer forming step, a second patterning step or a two-times patterning step, and a solder connecting step. In a second patterning step or a two-times patterning step, a solder pads is formed in the opening of the dielectric layer, wherein each solder pad has a height higher than the height of the dielectric, and the width of each solder pad is equal to or smaller than the maximum width of the opening, such that wider intervals are provided in the same area and the problems of short circuit failure and electrical interference can be reduced.

Abstract: The present invention provides a method of fabricating a semiconductor device. A substrate is provided. A first region and a second region are defined on the substrate. A first interfacial layer, a sacrifice layer and a sacrifice gate layer are disposed on the first region. The sacrifice layer and the sacrifice gate layer are disposed on the second region of the substrate. Next, a first etching step is performed to remove the sacrifice gate layer in the first region and the second region. Then, a second etching step is performed to remove the sacrifice layer in the first region and the second region to expose the substrate of the second region. Lastly, a second interfacial layer is formed on the substrate of the second region.

Abstract: An aspect of the invention includes a method for forming a semiconductor device with a two-step silicide formation. First, a silicide intermix layer is formed over a source/drain region and a portion of an adjacent extension region. Any spacers removed to accomplish this may be replaced. Dielectric material covers the silicide intermix layer over the source/drain region. A contact opening for a via is etched into the dielectric material. A second silicide contact is formed on the silicide intermix layer, or may be formed within the source/drain region as long as the second silicide contact still contacts the silicide intermix layer.

Abstract: A method for manufacturing a metal gate structure includes providing a substrate having a high-K gate dielectric layer and a bottom barrier layer sequentially formed thereon, forming a work function metal layer on the substrate, and performing an anneal treatment to the work function metal layer in-situ.

Abstract: When forming capacitive structures in a metallization system, such as in a dynamic RAM area, placeholder metal regions may be formed together with “regular” metal features, thereby achieving a very efficient overall process flow. At a certain manufacturing stage, the metal of the placeholder metal region may be removed on the basis of a wet chemical etch recipe followed by the deposition of the electrode materials and the dielectric materials for the capacitive structure without unduly affecting other portions of the metallization system. In this manner, very high capacitance values may be realized on the basis of a very efficient overall manufacturing flow.

Abstract: A semiconductor device includes a first layer and a second layer over the first layer. The first and second layers are configured to form an electron gas layer at an interface of the first and second layers. The semiconductor device also includes an Ohmic contact and multiple conductive vias through the second layer. The conductive vias are configured to electrically couple the Ohmic contact to the electron gas layer. The conductive vias could have substantially vertical sidewalls or substantially sloped sidewalls, or the conductive vias could form a nano-textured surface on the Ohmic contact. The first layer could include Group III-nitride nucleation, buffer, and channel layers, and the second layer could include a Group III-nitride barrier layer.

Abstract: A stacked structure may include semiconductors or semiconductor layers grown on an amorphous substrate. A light-emitting device and a solar cell may include the stacked structure including the semiconductors grown on the amorphous substrate. A method of manufacturing the stacked structure, and the light-emitting device and the solar cell including the stacked structure may involve growing a crystalline semiconductor layer on an amorphous substrate.

Abstract: To form a dielectric layer, an organometallic precursor is adsorbed on a substrate loaded into a process chamber. The organometallic precursor includes a central metal and ligands bound to the central metal. An inactive oxidant is provided onto the substrate. The inactive oxidant is reactive with the organometallic precursor. An active oxidant is also provided onto the substrate. The active oxidant has a higher reactivity than that of the inactive oxidant.

Abstract: A silicon vertical cavity laser with in-plane coupling comprises wafer bonding an active III-V semiconductor material above a grating coupler made on a silicon-on-insulator (SOI) wafer. This bonding does not require any alignment, since all silicon processing can be done before bonding, and all III-V processing can be done after bonding. The grating coupler acts to couple the vertically emitted light from the hybrid vertical cavity into a silicon waveguide formed on an SOI wafer.

Abstract: A semiconductor device includes a gate on a semiconductor substrate. One side wall of the gate may include at least one protrusion and an opposite side wall of the gate may include at least one depression. A contact is formed through an insulating layer disposed over the gate. The contact at least partially overlaps at least one of the protrusions in the gate. A metal layer is disposed on the insulating layer. The metal layer includes a first structure shifted to a first side of the gate. The first structure at least partially overlaps the contact such that the contact electrically couples the first structure to the gate through the insulating layer.

Abstract: A semiconductor device includes a triangle prism pillar having a first, a second, and a third sidewall surface, a bit line contacted with the first sidewall surface of the pillar, and a word line adjacent to the second sidewall surface of the pillar over the bit line.

Abstract: Exemplary metal line structure and manufacturing method for a trench are provided. In particular, the metal line structure includes a substrate, a target layer, a trench and a conductor line. The target layer is formed on the substrate. The trench is formed in the target layer and has a micro-trench formed at the bottom thereof. A depth of the micro-trench is not more than 50 angstroms. The conductor line is inlaid into the trench.

Abstract: An integrated circuit includes a substrate having a first surface and a second surface. At least one conductive structure continuously extends through the substrate. At least one sidewall of the at least one conductive structure is spaced from a sidewall of the substrate by an air gap.

Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described.