Abstract: A semiconductor device according to the invention includes a first Cu interconnect and a first barrier insulating film. a The first barrier insulating film is provided on the first Cu interconnect, and prevents Cu from being diffused from the first Cu interconnect. In addition, the semiconductor device includes a second Cu interconnect and a second barrier insulating film on the first barrier insulating film. The second barrier insulating film is provided on a first Cu interconnect, and prevents Cu from being diffused from the second Cu interconnect. The first and second barrier insulating films are made of a silicon-based insulating film having a branched alkyl group and a carbon-carbon double bond.

Abstract: A method of fabricating a metal silicide layer includes forming a metal layer on a substrate, and forming a pre-metal silicide layer by reacting the substrate with the metal layer by performing a first annealing process on the substrate. The method also includes implanting silicon into the substrate using a gas cluster ion beam (GCIB) process, and changing the pre-metal silicide layer into a metal silicide layer by performing a second annealing process on the substrate.

Abstract: A vertical cavity surface emitting laser capable of high-speed modulation and stabilized control of polarization direction of the laser light is provided, including a resonator which is formed by stacking a semiconductor substrate, a lower mirror layer formed on the upper side of the semiconductor substrate, an active layer formed on the upper side of the lower mirror layer, and an upper mirror layer including an oxidized layer formed on the upper side of the active layer, and a portion of which is formed in a mesa shape from a predetermined position to the upper surface in a height direction; an insulation layer covering the side surface of the mesa-shaped portion of the resonator, and the upper surface of the non-mesa-shaped portion of the resonator; and electrodes being wired on the upper surface of the upper mirror layer and on the lower surface of the semiconductor substrate, respectively.

Abstract: Apparatus and methods for evaporating metal onto semiconductor wafers are disclosed. One such apparatus can include an evaporation chamber that includes a wafer holder, such as a dome, and a test wafer holder that is separate and spaced apart from the wafer holder. In certain implementations, the test wafer can be coupled to a cross beam supporting at least one shaper. A metal can be evaporated onto production wafers positioned in the wafer holder while metal is evaporated on a test wafer positioned in a test wafer holder. In some instances, the production wafers can be GaAs wafers. The test wafer can be used to make a quality assessment about the production wafers.

Abstract: A manufacturing method of a thin film transistor array panel includes forming a gate line including a gate electrode on a substrate; forming a gate insulating layer on the gate line; forming a semiconductor layer on the gate insulating layer; forming a data line including a data conductive layer pattern on the semiconductor layer and crossing the gate line; forming a planarization layer on the data conductive layer pattern; dry-etching the planarization layer to expose a portion of the data conductive layer pattern overlapping the gate electrode; wet-etching the exposed data conductive layer pattern; and exposing a portion of the semiconductor layer overlapping the gate electrode.

Abstract: A semiconductor device includes: element formation regions each including a cell region where a semiconductor element is formed, a termination trench region; and a dicing line region including a groove separating the element formation regions. The termination trench region includes four trenches surrounding four sides of the cell region. Two of the trenches extend longitudinally in parallel to an X direction and the other two trenches extend longitudinally in parallel to a Y direction perpendicular to the X direction. The termination trench region is perpendicularly in contact with longitudinal sides of the dicing line region while the trenches extending longitudinally in parallel to the X direction intersect the trenches extending longitudinally in parallel to the Y direction at four corners of the element formation region, while vertical sections of the termination trench region in a cross direction are opened in four side surfaces of the element formation region.

Abstract: A through substrate via having a low stress is provided. The through substrate via is positioned in a substrate. The through substrate via includes: an outer tube penetrating the substrate; at least one inner tube disposed within the outer tube; a dielectric layer lining on a side wall of the outer tube, and a side wall of the inner tube; a strength-enhanced material filling the inner tube; and a conductive layer filling the outer tube.

Abstract: Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins having substantially vertical sidewalls. In another embodiment, etch characteristics of various materials utilized in fabrication of the semiconductor structure are used to increase an effective gate length (“Leffective”) and a field gate oxide. In yet another embodiment, a V-shaped trench is formed in the semiconductor structure to increase the Leffective and the field gate oxide. Semiconductor structures formed by these methods are also disclosed.

Abstract: A method for fabricating an active device array substrate is provided. First, a substrate having a display area and a sensing area is provided. Then, a first patterned conductor layer is formed on the display area of the substrate. A gate insulator is formed on the substrate. A patterned semiconductor layer, a second patterned conductor layer and a patterned photosensitive dielectric layer are formed on the gate insulator, wherein the second patterned conductor layer includes a source electrode, a drain electrode and a lower electrode, the patterned photosensitive dielectric layer covering the second patterned conductor layer includes an interface protection layer disposed on the source electrode and the drain electrode and a photo-sensing layer disposed on the lower electrode. A passivation layer is then formed on the substrate. After that, a third patterned conductor layer including a pixel electrode and an upper electrode is formed on the passivation layer.

Abstract: Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate.

Abstract: It is an objective to provide a semiconductor device with low leak current. The semiconductor device includes a plurality of ground side electrodes and a plurality of signal side electrodes arranged on a semiconductor substrate in an alternating manner; a plurality of control electrodes arranged respectively between each pair of a ground side electrode and a signal side electrode; a ground side electrode connecting section that connects the ground side electrodes to each other; a signal side electrode connecting section that connects the signal side electrodes to each other; and ground side lead wiring and signal side lead wiring that extend respectively from a region near one end and a region near another end of an arranged electrode section, in which the ground side electrodes and the signal side electrodes are arranged in an arrangement direction, away from the arranged electrode group in the arrangement direction.

Abstract: The applications discloses a semiconductor device comprising a substrate having a first active region, a second active region, and an isolation region having a first width interposed between the first and second active regions; a P-metal gate electrode over the first active region and extending over at least ? of the first width of the isolation region; and an N-metal gate electrode over the second active region and extending over no more than ? of the first width. The N-metal gate electrode is electrically connected to the P-metal gate electrode over the isolation region.

Abstract: The conductive line structure of a semiconductor device including a base; at least one patterned conductive layer formed over the base; a conductive line formed over the at least one patterned conductive layer; a protection layer that encompasses the top surface and sidewall of the conductive line to prevent undercut generated by etching. The structure further comprises an underlying layer under the conductive line. The underlying layer includes Ni, Cu or Pt. The conductive line includes gold or copper. The at least one patterned conductive layer includes at least Ti/Cu. The protection layer includes electro-less plating Sn, Au, Ag or Ni.

Abstract: A semiconductor element includes connection terminals. The connection terminals are each shaped in such a manner that the transverse cross-sectional area in a portion near the leading end thereof decreases toward the leading end. Specifically, the shape of each of the connection terminals is columnar except for the portion near the leading end, and the side surface in the portion near the leading end of the connection terminal is shaped in a tapered form. Furthermore, a metal layer for improving a solder wettability may be formed at least on the side surface shaped in the tapered form, of the connection terminal.

Abstract: A semiconductor device 100 includes: a silicon substrate 102; a first gate 114a including a gate electrode 108 formed on the silicon substrate 102 and sidewalls 112 formed on the sidewalls of the gate electrode 108; a silicide layer 132 formed lateral to the sidewalls 112 of the first gate 114a on a surface of the silicon substrate 102; and a contact 164 which overlaps at least partially in plan view with the first gate 114a and reaches to the silicide layer 132 of the surface of the silicon substrate 102; wherein an insulator film is located between the contact 164 and the gate electrode 108 of the first gate 114a.

Abstract: A semiconductor device manufacture method includes: forming a first film above a semiconductor substrate; forming a first mask film above the first film; patterning the first mask film; executing a plasma process for a side wall of the patterned first mask film to transform the side wall into a transformed layer; after the plasma process, forming a second mask film covering the first mask film; etching the second mask film to remove the second mask film above the first mask film and leave the second mask film formed on the side wall; after the etching the second mask film, removing the transformed layer; and after the removing the transformed layer, etching the first film by using the first mask film and the second mask film as mask.

Abstract: A semiconductor device including two silicon wafers stacked and bonded together with bumps of one wafer electrically coupled with those of the other wafer, in which generation of voids on the junction surface between the silicon wafers is suppressed. Due to a recess made in the surface of a buried conductive film, a cavity is formed in the junction surface between the silicon wafers. The ends of the cavity extend to the periphery of the junction surface between the silicon wafers. This allows the air trapped on the junction surface between the silicon wafers to get out through the cavity, thereby reducing the possibility of generation of voids on the junction surface.

Abstract: According to one embodiment, a memory device includes first and second fin type stacked structures each includes first to i-th memory strings (i is a natural number except 1) that are stacked in a first direction, the first and second fin type stacked structures which extend in a second direction and which are adjacent in a third direction, a first portion connected to one end in the second direction of the first fin type stacked structure, a width in the third direction of the first portion being greater than a width in the third direction of the first fin type stacked structure, and a second portion connected to one end in the second direction of the second fin type stacked structure, a width in the third direction of the second portion being greater than a width in the third direction of the second fin type stacked structure.

Abstract: It is an object of the invention to provide a lightweight semiconductor device having a highly reliable sealing structure which can prevent ingress of impurities such as moisture that deteriorate element characteristics, and a method of manufacturing thereof. A protective film having superior gas barrier properties (which is a protective film that is likely to damage an element if the protective film is formed on the element directly) is previously formed on a heat-resistant substrate other than a substrate with the element formed thereon. The protective film is peeled off from the heat-resistant substrate, and transferred over the substrate with the element formed thereon so as to seal the element.

Abstract: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

Abstract: A method of depositing a metal film on a substrate with patterned features includes placing a substrate with patterned features into a photo-induced chemical vapor deposition (PI-CVD) process chamber. The method also includes depositing a metal film by PI-CVD to fill the patterned features from bottom up.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of bodies isolated by trenches by etching a substrate, forming a buried bit line gap-filling a portion of each trench, forming an etch stop layer on an upper surface of the buried bit line; and forming a word line extended in a direction crossing the buried bit line over the etch stop layer.

Abstract: A semiconductor device that is resin-sealed in a wafer level after a rewiring layer forming process and a metal post forming process forming a metal post are performed on a semiconductor substrate of the semiconductor device includes devices formed on the semiconductor substrate. Further all of the devices are disposed in respective positions other than positions overlapping a peripheral border of the metal post when viewed from a top of the semiconductor substrate.

Abstract: A method of forming a ruthenium-containing film in a vapor deposition process, including depositing ruthenium with an assistive metal species that increases the rate and extent of ruthenium deposition in relation to deposition of ruthenium in the absence of such assistive metal species. An illustrative precursor composition useful for carrying out such method includes a ruthenium precursor and a strontium precursor in a solvent medium, wherein one of the ruthenium and strontium precursors includes a pendant functionality that coordinates with the central metal atom of the other precursor, so that ruthenium and strontium co-deposit with one another. The method permits incubation time for ruthenium deposition on non- metallic substrates to be very short, thereby accommodating very rapid film formation in processes such as atomic layer deposition.

Abstract: A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.

Abstract: According to one embodiment, a semiconductor device manufacturing method comprises defining a region in which absorptance of light illuminated for annealing to a substrate on which a pattern of a semiconductor integrated circuit is formed is not larger than a preset value as a coarse pattern region, locally forming a thin film that enhances light absorptance on the coarse pattern region, and annealing the substrate by illuminating light onto the substrate on which the pattern of the integrated circuit and thin film are formed.

Abstract: Methods of forming features such as word lines of memory circuitry are disclosed. One such method includes forming an initial pitch multiplied feature pattern extending from a target area into only one of a first or second periphery area received on opposing sides of the target area. Thereafter, a subsequent feature pattern is formed which extends from the target array area into the other of the first or second periphery area. The initial and subsequent feature patterns may be used in forming features in an underlying material which extend from the target area to the first and second periphery areas. Other embodiments are disclosed.

Abstract: A process of forming an integrated circuit including an MOS transistor, in which a pre-metal deposition cleanup prior to depositing metal for silicide formation includes an HF etch, a first SC1 etch, a piranha etch and a second SC1 etch, so that a native oxide on the source/drain regions is less the 2 nanometers thick before deposition of the silicide metal. A process of forming a metal silicide layer on an integrated circuit containing an MOS transistor, in which a pre-metal deposition cleanup prior to depositing metal for silicide formation includes an HF etch, a first SC1 etch, a piranha etch and a second SC1 etch, so that a native oxide on the source/drain regions and the MOS gate is less the 2 nanometers thick before deposition of the silicide metal.

Abstract: The use of a monolayer or partial monolayer sequencing process to form conductive titanium nitride produces a reliable structure for use in a variety of electronic devices. In an embodiment, a structure can be formed by using ammonia and carbon monoxide reactant materials with respect to a titanium-containing precursor exposed to a substrate. Such a TiN layer has a number of uses including, but not limited to, use as a diffusion barrier underneath another conductor or use as an electro-migration preventing layer on top of a conductor. Such deposited TiN material may have characteristics associated with a low resistivity, a smooth topology, high deposition rates, excellent step coverage, and electrical continuity.

Abstract: A semiconductor package includes: a supporting substrate; a functioning element and a first joining element formed on a first principal surface of the supporting substrate; a sealing substrate disposed in an opposing relationship to the supporting substrate with the functioning element and the first joining element interposed therebetween; a second joining element provided on a second principal surface of the supporting substrate; a through-electrode provided in and extending through the supporting substrate and adapted to electrically connect the first and second joining elements; and a first electromagnetic shield film coated in an overall area of a side face of the supporting substrate which extends perpendicularly to the first and second principal surfaces.

Abstract: There is provided a method of manufacturing an electronic element for forming the electronic element including one or more wiring layers and an organic insulating layer stacked on a substrate. The method includes a wiring layer formation step of forming the wiring layer on the substrate; an organic insulating layer formation step of forming an organic insulating layer on the wiring layer; and an irradiation step of irradiating a short-circuit portion of the wiring layer through the organic insulating layer with a laser beam having a wavelength transmissive through the organic insulating layer.

Abstract: A method for manufacturing includes the steps of forming a BCB resin region on a semiconductor optical device; processing a surface of the BCB resin region with inductively coupled plasma produced with a high-frequency power supply for supplying ICP power and a high-frequency power supply for supplying bias power, thus forming a silicon oxide film on the surface of the BCB resin region and roughening the surface of the BCB resin region with projections and recesses; and forming an electrode pad on the surface of the BCB resin region in direct contact with the silicon oxide film. The surface roughness of the BCB resin region and the thickness of the silicon oxide film on the surface of the BCB resin region are controlled by adjusting the bias power and the ICP power.

Abstract: A method of fabricating a semiconductor device can be provided by etching sidewalls of a preliminary trench in a substrate that are between immediately adjacent gate electrode structures, to recess the sidewalls further beneath the gate electrode structures to provide recessed sidewalls. Then, the recessed sidewalls and a bottom of the preliminary trench can be etched using crystallographic anisotropic etching to form a hexagonally shaped trench in the substrate.

Abstract: Provided is a semiconductor chip including a back side insulation structure. The semiconductor chip may include a semiconductor layer including an active surface and an inactive surface facing each other; the insulating layer includes a first surface adjacent to the inactive surface and a second surface facing the first surface. The insulating layer is disposed on the inactive surface of the semiconductor layer. A penetrating electrode fills a hole penetrating the semiconductor layer and the insulating layer. The through electrode comprises a protrusive portion protruding from the second surface of the insulating layer.

Abstract: a manufacturing method of a semiconductor substrate includes the following steps: forming a first wiring layer on a substrate; forming an interlayer insulating film having a via hole on the wiring layer; forming carbon nanotubes in the via hole; performing a fluorination treatment entirely to the substrate; forming an embedded film in the via hole having the carbon nanotubes therein; and polishing the substrate to entirely flatten the substrate.

Abstract: A method of providing a metal contact to n-type Gallium Nitride is disclosed. The method does not require high temperatures that often lead to a degradation of semiconductor materials, dielectric films, interfaces and/or metal-semiconductor junctions. The method can be applied at practically any step of a semiconductor device fabrication process and results in high quality ohmic contact with low contact resistance and high current handling capability. Present invention significantly simplifies the fabrication process of semiconductor devices, such as Gallium Nitride-based Light Emitting Diodes and Laser Diodes, while improving the resulting performance of the said devices. The invention can also be applied to improve the performance of electronic devices based on Gallium Nitride material system, especially where an additional annealing step is beneficial during the fabrication process.

Abstract: According to the embodiment, a pad electrode, a protective film, an under barrier metal film, and an electrode wiring portion are provided. The pad electrode is formed on a semiconductor substrate. The protective film is formed on the semiconductor substrate so that a surface of the pad electrode is exposed. The under barrier metal film is formed on the pad electrode and the protective film. The electrode wiring portion is formed on the pad electrode via the under barrier metal film. Moreover, a surface reflectance of the under barrier metal film is 30% or more at a wavelength of 800 nm, and a diameter of the electrode wiring portion is 140 ?m or less.

Abstract: A method of fabricating a semiconductor device and a semiconductor device are provided. The method includes method of fabricating a semiconductor device including providing a semiconductor substrate having a first semiconductor device region and a second semiconductor device region defined therein, forming a first gate structure in the first semiconductor device region, forming a second gate structure in the second semiconductor device region, forming a first trench adjacent to a first side of the first gate structure, forming a second trench adjacent to a first side of the second gate structure, and forming a first semiconductor pattern in the first trench and forming a second semiconductor pattern in the second trench, wherein the first and second trenches have different cross-sectional shapes from each other.

Abstract: A semiconductor device has a substrate, a gate dielectric layer, and a metal gate electrode on the gate dielectric layer. The gate dielectric layer includes an oxide layer having a dielectric constant (k) greater than 4, and silicon concentrated at interfaces of the oxide layer with the substrate and with the metal gate electrode. A method of fabricating a semiconductor device includes forming a removable gate over a substrate with a gate dielectric layer between the removable gate and the substrate, forming a dielectric layer over the substrate and exposing an upper surface of the removable gate, removing the removable gate leaving an opening in the dielectric layer, forming a protective layer on the gate dielectric layer and lining the opening, and forming a metal gate electrode in the opening. The protective layer has a graded composition between the gate dielectric layer and the metal gate electrode.

Abstract: A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads.

Abstract: A graphene transparent electrode, which comprises: at least one graphene sheet; wherein the graphene sheets electrically connect with each other by overlapping with each other, each of the graphene sheets has a diameter from 10 ?m to 1 mm, the quantity of the graphene sheets in the graphene transparent electrode is from 1 to 1000, the electrical resistance of the graphene transparent electrode is 1 ?/cm or below, and the light transmittance of the graphene transparent electrode is 70% or above. A graphene light emitting diode (gLED) and a method of fabricating the same are also disclosed.

Abstract: A photovoltaic module may contain a front contact configured to transfer electrical current from the module.

Abstract: In one aspect, an apparatus may include a metal gate of a transistor. An etch stop layer may be selectively formed over the metal gate. The etch stop layer may include a metal compound. An insulating layer may be over the etch stop layer. A conductive structure may be included through the insulating layer to the metal gate. Methods of making such transistors are also disclosed.

Abstract: A CSP includes: a hard board having a first wiring layer with conductive pads; a plurality of conductive elements disposed on at least a portion of the conductive pads; an electronic component having opposite active and inactive surfaces and being mounted on the hard board via the inactive surface; an encapsulating layer disposed on the hard board for encapsulating the conductive elements and electronic component, the active surface of the electronic component and the surfaces of the conductive elements being exposed through the encapsulating layer; a first dielectric layer and a third wiring layer disposed on the encapsulating layer, the third wiring layer being electrically connected to the conductive elements and the electronic component and further electrically connected to the first wiring layer through the conductive elements, thereby obtaining a stacked connection structure without the need of PTHs and using the hard board as a main structure to avoid warpage.

Abstract: A method of forming metal lines of a semiconductor device includes forming an etch stop layer over a semiconductor substrate over which underlying structures are formed, forming an insulating layer over the etch stop layer, etching the etch stop layer and the insulating layer to form trenches through which the underlying structures are exposed, shrinking the insulating layer by using a thermal treatment process in order to widen openings of the trenches, and filling the trenches with a conductive material.

Abstract: A heat dissipation structure for an electronic device includes a body having a first surface and a second surface opposite to the first surface. A silicon-containing insulating layer is disposed on the first surface of the body. An ultrananocrystalline diamond film is disposed on the silicon-containing insulating layer. A first conductive pattern layer is disposed on the silicon-containing insulating layer and enclosed by the ultrananocrystalline diamond film, wherein the ultrananocrystalline diamond film and the first conductive pattern layer do not overlap with each other as viewed from a top-view perspective. A method for fabricating a heat dissipation structure for an electronic device and an electronic package having the heat dissipation structure are also disclosed.

Abstract: An electrode structure is disclosed for enhancing the brightness and/or efficiency of an LED. The electrode structure can have a metal electrode and an dielectric material formed intermediate the electrode and a light emitting semiconductor material. Electrical continuity between the semiconductor material and the metal electrode is provided by an optically transmissive ohmic contact layer, such as a layer of Indium Tin Oxide. The metal electrode thus can be physically separated from the semiconductor material by one or more of the dielectric material and the ohmic contact layer. The dielectric layer can increase total internal reflection of light at the interface between the semiconductor and the dielectric layer, which can reduce absorption of light by the electrode. Such LED can have enhanced utility and can be suitable for uses such as general illumination.

Abstract: A semiconductor structure includes a semiconductor substrate; a tunneling layer on the semiconductor substrate; a source region adjacent the tunneling layer; and a floating gate on the tunneling layer. The floating gate comprises a first edge having an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion. The semiconductor structure further includes a blocking layer on the floating gate, wherein the blocking layer has a first edge facing a same direction as the first edge of the floating gate.

Abstract: Aspects concerning a method of making electrical contact to a region of semiconductor in which one or more LEDs are formed include that a dielectric region can be formed on a p region of the semiconductor, and that a metallic electrode can be formed on (at least partially on) the region of dielectric material. A transparent layer of a material such as Indium Tin Oxide can be used to make ohmic contact between the semiconductor and the metallic electrode, as the metallic electrode is separated from physical contact with the semiconductor by one or more of the dielectric material and the transparent ohmic contact layer (e.g., ITO layer). The dielectric material can enhance total internal reflection of light and reduce an amount of light that is absorbed by the metallic electrode.

Abstract: A method of producing a solid-state image pickup element includes forming a hole portion, forming a first-conductive type high-concentration impurity region in a bottom wall of the hole portion, and forming a first-conductive type high-concentration impurity-doped element isolation region in a part of a sidewall of the hole portion and connected to the first-conductive type high-concentration impurity region. The method also includes forming a second-conductive type photoelectric conversion region beneath the first-conductive type high-concentration impurity region and adapted to undergo a change in charge amount upon receiving light, and forming a transfer electrode formed on the sidewall of the hole portion through a gate dielectric film.