Abstract: A stacked semiconductor package includes a first die, a second die stacked on a surface of the first die, a heat dissipation layer disposed on the surface, a heat insulation layer disposed on the surface to cover the heat dissipation layer and the first die, a heat sink disposed on the second die, and a heat conduction structure spaced apart from the second die in a lateral direction on the surface to connect the heat dissipation layer to the heat sink.

Abstract: A method of producing optoelectronic semiconductor components includes A) providing a chip carrier with electrical conductor structures on a carrier upper side, B) applying at least one semi-conductor chip configured to produce light on at least one of the electrical conductor structures, C) applying at least one sealing structure to at least one of the electrical conductor structures so that the sealing structure completely surrounds at least one contact area when viewed from the top, and D) producing a mold body directly at the at least one semiconductor chip and directly at the at least one sealing structure by transfer molding or injection molding, wherein, in an injection mold, the at least one sealing structure seals the at least one contact area against a material of the mold body so that the at least one contact area remains free of the mold body.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes: forming a semiconductor feature on a first surface of a substrate; forming a first insulating film on the semiconductor feature; forming a first wiring layer on the first insulating film; forming a second insulating film on the first wiring layer; forming a second wiring layer on the second insulating film; forming a first electrode on the second wiring layer; providing a protective adhesive that covers the first electrode and the second wiring layer; bonding a supporting substrate onto the protective adhesive; polishing a second surface of the substrate opposite to the first surface; removing the supporting substrate from the protective adhesive; and removing at least a portion of the protective adhesive to expose the first electrode.

Abstract: An image sensor package according to an embodiment of the present technology includes: a solid-state image sensor; a transparent substrate; and a package substrate. The solid-state image sensor has a light-receiving surface including a light-reception unit and a first terminal unit, and a rear surface opposite to the light-receiving surface. The transparent substrate faces the light-receiving surface. The package substrate includes a frame portion, a second terminal unit, and a supporting body. The frame portion has a joint surface to be joined to the transparent substrate and includes a housing portion housing the solid-state image sensor. The second terminal unit is to be wire-bonded to the first terminal unit, the second terminal unit being provided in the frame portion. The supporting body is provided in a peripheral portion of the light-receiving surface or at a center portion of the rear surface and partially supports the light-receiving surface or the rear surface.

Abstract: A semiconductor package includes an interposer having multiple connection structures, each including redistribution layers electrically connected to each other, and a passivation layer covering at least a portion of each of the connection structures and filling a space between the connection structures. A first semiconductor chip is disposed on the interposer and has first connection pads, and a second semiconductor chip is disposed adjacent to the first semiconductor chip on the interposer and has second connection pads. The connection structures are independently arranged to each at least partially overlap with one or both of the first and second semiconductor chips, in a stacking direction of the first and second semiconductor chips on the interposer. The redistribution layers of each of the connection structures are electrically connected to at least one of the first and second connection pads via under bump metals.

Abstract: A system includes a semiconductor substrate having a first cavity. The semiconductor substrate forms a pedestal adjacent the first cavity. A device overlays the pedestal and is bonded to the semiconductor substrate by metal within the first cavity. A plurality of second cavities are formed in a surface of the pedestal beneath the device, wherein the second cavities are smaller than the first cavity. In some of these teachings, the second cavities are voids. In some of these teachings, the metal in the first cavity comprises a eutectic mixture. The structure relates to a method of manufacturing in which a layer providing a mask to etch the first cavity is segmented to enable easy removal of the mask-providing layer from the area over the pedestal.

Abstract: A radio frequency (RF) antenna containing element is provided. The RF antenna containing element includes a reinforced metal foil laminate antenna bonded to a carrier layer. The reinforced metal foil laminate antenna includes a metal foil layer bonded to a reinforcement layer. The reinforcement layer can mitigate tearing of the metal foil layer during formation of the antenna.

Abstract: A semiconductor package includes a first chip package including a plurality of first semiconductor dies and a first insulating encapsulant, a second semiconductor die, a third semiconductor die, and a second insulating encapsulant. The plurality of first semiconductor dies are electrically connected to each other, and the first insulating encapsulant encapsulates the plurality of first semiconductor dies. The second semiconductor die and the third semiconductor die are electrically communicated to each other by connecting to the first chip package, wherein the first chip package is stacked on the second semiconductor die and the third semiconductor die. The second insulating encapsulant encapsulates the first chip package, the second semiconductor die, and the third semiconductor die.

Abstract: A semiconductor device includes a composite chip mounted over a wiring substrate, the composite chip including a first area, a second area that is provided independently from the first area, and a third area including a first material between the first and second areas. The first area includes a first circuit formed in the first area, and the second area includes a second circuit formed in the second area. The first area is spaced apart from the second area by the first material.

Abstract: A hearing aid comprising a microphone, a receiver, hearing aid electronics coupled to the microphone and the receiver, and conductive traces overlaying an insulator, the conductive traces configured to interconnect the hearing aid electronics and to follow non-planar contours of the insulator. Examples are provided wherein the insulator includes a hearing aid housing.

Abstract: An object of the present invention is to provide a semiconductor device capable of reducing external stress transmitted to a semiconductor chip through a lead frame. A semiconductor device includes a base plate, a semiconductor element held on the base plate, a housing disposed on the base plate and having a frame shape enclosing the semiconductor element, a terminal section provided in an outer surface of the housing and connectable to an external device, a lead frame that is long and has one end disposed so as to be connectable to the terminal section provided in the housing and another end connected onto the semiconductor element via a bonding material, a sealing material disposed in the housing to seal the lead frame and the semiconductor element, and a fixing section that fixes, in the housing, part of the lead frame to the base plate or the housing.

Abstract: A printable electronic component includes a component substrate and a circuit disposed in or on the component substrate. One or more electrically conductive connection posts protrude from the component substrate. One or more electrically conductive component contact pads are exposed on or over the component substrate on a side of the component substrate opposite the one or more connection posts. The one or more component contact pads and the one or more electrically conductive connection posts are both electrically connected to the circuit. The components can be printed onto a destination substrate and electrically connected to contact pads on the destination substrate through the connection posts. The components can also be printed onto other components and electrically connected through the connection posts and component contact pads to form a three-dimensional electronic structure.

Abstract: A circuit board structure includes a circuit layer structure, an electronic component, and a stopper. The circuit layer structure includes a plurality of dielectric layers and circuits in the dielectric layers. The electronic component is disposed in the circuit layer structure; the electronic component includes a chip and a conductive bump; the chip has a first surface and a second surface that are oppositely disposed, and the first surface of the chip contacts one of the dielectric layers; the conductive bump is on the second surface of the chip and is electrically connected to the chip. The stopper is within the circuit layer structure and abuts against the conductive bump. A method for fabricating a circuit board structure is also provided herein.

Abstract: A portable device including a secondary battery, a plurality of driving components driven by charged power of the secondary battery, a charging unit configured to charge the secondary battery by an input of outside power supplied from outside of the portable device, a plurality of transformation units each configured to output the charged power of the secondary battery at a driving voltage of a corresponding one of the plurality of driving components, a detection unit configured to detect the input of the outside power to the charging unit, and a switching controller configured to switch a state of one of the plurality of transformation units from an operation state to a stopped state responsive to detecting the input of the outside power to the charging unit causing only the corresponding one of the plurality of driving components to stop operation during charging of the secondary battery.

Abstract: A method of forming contacts to an embedded semiconductor die includes embedding a semiconductor die in an encapsulation material, the semiconductor die having a first terminal at a first side of the semiconductor die, forming a first metal mask on a first surface of the encapsulation material, the first metal mask being positioned over the first side of the semiconductor die and exposing a first part of the encapsulation material aligned with the first terminal of the semiconductor die, directing a pressurized stream of liquid toward the first surface of the encapsulation material with the first metal mask, to remove the first exposed part of the encapsulation material and form a first contact opening to the first terminal of the semiconductor die, and forming an electrically conductive material in the first contact opening. Related semiconductor packages are also described.

Abstract: Light-emitting device packages include a package substrate surrounded by a lower molding member, a light-emitting device on the package substrate and surrounded by an upper molding member, a heat conductive pad between a lower surface of the light-emitting device and an upper surface of the package substrate, a first electrode on an upper surface of the light-emitting device, a second electrode on the upper surface of the light-emitting device, a fluorescent material on the upper surface of the light-emitting device, and a plurality of bonding wires electrically connecting the package substrate with separate, respective electrodes of the first electrode and the second electrode.

Abstract: A device and method of utilizing an interconnect bridge to electrically couple two semiconductor dies located on different surfaces. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a substrate to a semiconductor die on a motherboard are shown. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a top surface of a substrate to a semiconductor die on a bottom surface of a substrate are shown. Methods of electrically coupling semiconductor dies on different surfaces using interconnect bridges are shown.

Abstract: A semiconductor device includes: a semiconductor module including a module main body having first and second main surfaces which are opposite to each other, and a terminal protruding from a side surface of the module main body and bent toward the first main surface; a mounting board placed on the first main surface side and connected to the terminal; a heat radiation fin placed on the second main surface side; and a screw fitting a fitting portion of the module main body from the first main surface side to the heat radiation fin, wherein the mounting board is provided with an opening at a portion facing the fitting portion, and a type of a product is printed on the first main surface and exposed from the opening of the mounting board.

Abstract: There is provided a semiconductor device, including: a semiconductor element which includes an element main surface and an element rear surface that face opposite sides in a thickness direction and in which a first electrode and a second electrode are formed on the element main surface; a first conductive member electrically connected to the first electrode; a second conductive member electrically connected to the second electrode; and a sealing resin configured to cover part of the first conductive member, part of the second conductive member, and the semiconductor element.

Abstract: An electronic assembly includes a first printed circuit board (PCB), a second PCB, and a grounding shield. The first PCB includes a first plurality of electronic components and a first conductive layer. The second PCB includes a second plurality of electronic components and a second conductive layer. The grounding shield is electrically connected between the first conductive layer of the first PCB and the second conductive layer of the second PCB to electrically connect the first PCB and the second PCB. The first PCB and the second PCB are arranged in a stack such that the first conductive layer and the second conductive layer mutually shield at least one of the first plurality of electronic components and at least one of the second plurality of electronic components from electromagnetic interference.

Abstract: A power semiconductor module, including a housing; a power semiconductor chip within the housing; power terminals protruding from the housing and electrically interconnected with power electrodes of the semiconductor chip; and auxiliary terminals protruding from the housing and electrically interconnected with a gate electrode and one of the power electrodes; wherein three auxiliary terminals are arranged in a coaxial auxiliary terminal arrangement, which comprises an inner and two outer auxiliary terminals, which are arranged on opposing sides of the inner auxiliary terminal. The inner auxiliary terminal is electrically interconnected with the gate electrode or one of the power electrodes and the two outer auxiliary terminals are electrically connected with the other one of the gate electrode and the one of the power electrodes.

Abstract: An LED chip module includes a first electrode plate and a second electrode plate. A first set of LED chip and a second set of LED chip are respectively set on the first electrode plate and the second electrode plate. The second set of LED chip is electrically connected to the first set of LED chip. A plastic shell is fixedly connected to the first electrode plate and the second electrode plate by injection molding to make the first electrode plate and the second electrode plate keep a predetermined space between each other and make a lower surface of the first electrode plate and a lower surface of the second electrode plate be respectively connected to two different polarity terminals of the power supply to drive the first set of LED chip and the second set of LED chip to emit light.

Abstract: A wiring substrate includes: a substrate; an oxide film including an oxide of one or both of Ti and Zr, the oxide film being formed on a surface of the substrate; an alloy film including an alloy of one or any combination of Ni, Co, and W with Cu, the alloy film being formed on the oxide film; and a Cu layer formed on the alloy film.

Abstract: A semiconductor package and a packaged electronic device are described. The semiconductor package has a foundation layer and a planar filtering circuit. The circuit is formed in the foundation layer to provide EMI/RFI mitigation. The circuit has one or more conductive traces that are patterned to form an equivalent circuit of inductors and capacitors. The one or more conductive traces include planar metal shapes, such as meanders, loops, inter-digital fingers, and patterned shapes, to reduce the z-height of the package. The packaged electronic device has a semiconductor die, a foundation layer, a motherboard, a package, and the circuit. The circuit removes undesirable interferences generated from the semiconductor die. The circuit has a z-height that is less than a z-height of solder balls used to attach the foundation layer to the motherboard. A method of forming a planar filtering circuit in a foundation layer is also described.

Abstract: A three-dimensional stacked integrated circuit (3D SIC) that can have at least a first 3D XPoint (3DXP) die and, in some examples, can have at least a second 3DXP die too. In such examples, the first 3DXP die and the second 3DXP die can be stacked. The 3D SIC can be partitioned into a plurality of columns that are perpendicular to each of the stacked dies. In such examples, when a first column of the plurality of columns is determined as failing, data stored in the first column can be replicated to a second column of the plurality of columns. Also, for example, when a part of a first column of the plurality of columns is determined as failing, data stored in the part of the first column can be replicated to a corresponding part of a second column of the plurality of columns.

Abstract: An illumination device includes a supporting base, and a light-emitting element inserted in the supporting base. The light-emitting element includes a substrate having a supporting surface and a side surface, a light-emitting chip disposed on the supporting surface, and a first wavelength conversion layer covering the light-emitting chip and only a portion of the supporting surface without covering the side surface.

Abstract: A wiring board has a metal-made base having a front surface and a back surface, an insulating frame body bonded to the front surface of the base through a bonding layer made of bonding material, a mounting area where a component is supposed to be mounted on the front surface of the base, and a restriction portion formed by a groove or a protrusion that is provided on the front surface of the base or by a combination of the groove and the protrusion. The restriction portion is arranged in at least a part of an area between the mounting area and the frame body on the front surface in plan view.

Abstract: A power MOSFET includes a substrate, a dielectric layer, solder balls, first and second patterned-metal layers. The substrate includes an active surface, a back surface, a source region and a gate region on the active surface, and a drain region on the back surface. The first patterned-metal layer disposed on the active surface includes a source electrode, a gate electrode, a drain electrode and a connecting trace. The source and gate electrodes electrically connect the source and gate regions. The connecting trace located at an edge of the substrate electrically connects the drain electrode. The dielectric layer disposed on the active surface exposes the first patterned-metal layer. The second patterned-metal layer includes UBM layers covering the source, gate and drain electrodes and a connecting metal layer covering the connecting trace and extending to the edge to electrically connect the drain region. The solder balls are disposed on the UBM layers.

Abstract: A semiconductor package and method of manufacturing the same are provided. A semiconductor package includes an interconnect layer comprising first conductive pads configured as bond pads and second conductive pads configured as test pads, a plurality of conductive pillars over the interconnect layer, and a first semiconductor die bonded to the interconnect layer through the first conductive pads. The semiconductor package also includes an integrated passive device bonded to the interconnect layer through the first conductive pads, wherein the integrated passive device and the first semiconductor die are disposed on a same side of the interconnect layer, a second semiconductor die electrically coupled to the conductive pillars, and an encapsulating material surrounding the first semiconductor die, the integrated passive device and the conductive pillars.

Abstract: A device is provided, including: a first device package including: a first redistribution structure including a first redistribution line and a second redistribution line; a die on the first redistribution structure; a first via coupled to a first side of the first redistribution line; a second via coupled to a first side of the second redistribution line and extending through the second redistribution line; an encapsulant surrounding the die, the first via, and the second via; and a second redistribution structure over the encapsulant, the second redistribution structure electrically connected to the die, the first via, and the second via; a first conductive connector coupled to a second side of the first redistribution line, the first conductive connector disposed along a different axis than a longitudinal axis of the first via; and a second conductive connector coupled to a second side of the second redistribution line, the second conductive connector disposed along a longitudinal axis of the second via.

Abstract: The invention relates to an electrical equipment, in particular for electrical or hybrid vehicles, comprising a casing, said casing comprising a casing element comprising a side wall and defining an inner space. The side wall of the casing element comprises a material offset towards the inner space thereof forming a zone for connecting the positive terminal and the negative terminal of the electrical energy source such that said material offset overlaps the first electrical conductor and the second electrical conductor only making visible, from the outside of said side wall, the positive visible terminal and the negative visible terminal.

Abstract: Disclosed are semiconductor packages and methods of manufacturing the same. The method of manufacturing a semiconductor package may include providing a carrier substrate having a trench formed on a first top surface of the carrier substrate, providing a first semiconductor chip on the carrier substrate, mounting at least one second semiconductor chip on a second top surface of the first semiconductor chip, coating a mold member to surround a first lateral surface of the first semiconductor chip and a second lateral surface of the at least one second semiconductor chip, and curing the mold member to form a mold layer. The trench may be provided along a first edge of the first semiconductor chip. The mold member may cover a second edge of a bottom surface the first semiconductor chip.

Abstract: An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An upper portion of the post extends above an upper surface of the substrate. An exterior surface of the post associated with the upper portion is in contact with a dielectric layer. The dielectric layer is disposed on the upper surface of the substrate and adjacent to the post to provide a dielectric collar for the post. An exterior surface of the dielectric collar is in contact with a conductor layer. The conductor layer is disposed adjacent to the dielectric collar to provide a metal collar for the post, where a top surface of each of the conductor member, the dielectric collar and the metal collar have formed thereon a bond structure for interconnection of the metal collar and the conductor member.

Abstract: Disclosed herein are apparatuses and methods for configuring a circuit board to have a plurality of die having different bottom-side electrical potential. An apparatus comprises a circuit board comprising a metallic base plate, a thermally conductive dielectric, and a plurality of metallic pads. Each of a plurality of die of the apparatus is coupled to a respective one of the plurality of metallic pads, and the plurality of die comprises a first die and a second die. Based on each of the plurality of die being coupled to a respective one of the plurality of metallic foil pads, the first die is configured to exhibit a first bottom-side electrical potential and the second die is configured to exhibit a second bottom-side electrical potential. The apparatus is further configured to conduct heat from the plurality of die away from the plurality of die via at least the metallic base plate, the thermally conductive dielectric, and the plurality of metallic pads.

Abstract: The place and route stage for a hard macro is modified to assign a more robust power-grid tier to a critical path for a hard macro and to assign a less robust power-grid tier to a remainder of the hard macro.

Abstract: A printed circuit board comprises a board main body, a sensor, an external connection pad, and a hollow-structured electrical conductor. The board main body has a top face and a bottom face opposite the top face. The sensor is mounted on one of the top face and the bottom face of the board main body. The external connection pad is provided on the top face or the bottom face of the board main body opposite the sensor. The hollow-structured electrical conductor extends through the board main body and electrically connects the sensor to the external connection pad.

Abstract: A small-scale camera device with heat-dissipating properties includes a pedestal bracket and a camera module mounted on the pedestal bracket. The pedestal bracket includes a top plate and a side plate extending perpendicularly from edges of the top plate. The side plate includes an inner side surface and an outer side surface opposite to the inner side surface. The bottom of the side plate defines a plurality of first receiving recesses, each of the first receiving recesses carries a heat dissipation member.

Abstract: A method for manufacturing a lead frame including: punching a metal plate disposed on a die with a punch in a direction from the metal plate toward a die side to form a punched metal, the punched metal including at least one electrode, at least one hanger lead separated from the at least one electrode, and an outer frame connected to the at least one electrode and the at least one hanger lead; and stamping at least part of a corner of an end of the at least one hanger lead, the corner being on a side corresponding to the die side, with a vertically split mold to form at least one chamfered surface.

Abstract: A semiconductor package is provided which includes a redistribution substrate, an interconnect substrate on the redistribution substrate, a metal layer on the semiconductor chip, a semiconductor chip on the redistribution substrate and in the hole of the interconnect substrate, and a mold layer in a gap between the semiconductor chip and the interconnect substrate. The interconnect substrate includes a hole penetrating thereinside. The interconnect substrate includes base layers and a conductive member extending through the base layers. A top surface of the interconnect substrate is positioned either above or below the level of the top surface of the metal layer.

Abstract: An integrated fan-out package includes a die, an insulating encapsulation, a redistribution circuit structure, conductive terminals, and barrier layers. The insulating encapsulation encapsulates the die. The redistribution circuit structure includes a first redistribution conductive layer on the insulating encapsulation, a first inter-dielectric layer covering the first redistribution conductive layer, and a second redistribution conductive layer on the first inter-dielectric layer. The first redistribution conductive layer includes conductive through vias extending from a first surface of the insulating encapsulation to a second surface of the insulating encapsulation. The first inter-dielectric layer includes contact openings, portions of the second redistribution conductive layer filled in the contact openings are in contact with the first redistribution conductive layer and offset from the conductive through vias.

Abstract: A micro-electromechanical system (MEMS) device includes a support structure comprising a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a conductive layer coupled to the first adhesion layer, a second adhesion layer coupled to the conductive layer, and a barrier layer coupled to the second adhesion layer. The support structure defines a cavity. The MEMS device also includes a III-V membrane coupled to a portion of the support structure. A portion of the III-V membrane is suspended over the cavity defined by the support structure and defines a MEMS structure.

Abstract: Provided is a method for producing a fluorescent material, including: preparing a raw material mixture including a compound containing at least one rare earth element Ln selected from the group consisting of Y, Gd, La, Lu, Sc and Sm, a compound containing at least one Group 13 element selected from Al and Ga, a compound containing Tb, a compound containing Ce and a compound containing Eu, wherein the raw material mixture contains each compound such that each element satisfies a composition represented by the following formula (I): (Ln1-a-b-cTbaCebEUc)3(Al1-dGad)5O12 (I), wherein a, b, c and d satisfy 0.25?a<1, 0.008×10?2?b?1.5×10?2, 0.012×10?2?c?2×10?2, and 0?d?0.85, and heat-treating the raw material mixture to obtain the fluorescent material.

Abstract: A semiconductor package structure having an antenna module includes: a substrate, having at least one via hole running through the substrate; a rewiring layer, disposed on a surface of the substrate; a metal bump, disposed on and electrically connected to the rewiring layer; a semiconductor chip, disposed on and electrically connected to the rewiring layer; a conductive column, filling the via hole; a plastic packaging material layer, surrounding the metal bump and the semiconductor chip; and an antenna module, electrically connected to the metal bump through the conductive column and the rewiring layer.

Abstract: Provided are a method of manufacturing a semiconductor package substrate, a semiconductor package substrate manufactured using the method of manufacturing a semiconductor package substrate, a method of manufacturing a semiconductor package, and a semiconductor package manufactured using the method of manufacturing a semiconductor package. The method of manufacturing a semiconductor package substrate includes forming first grooves or first trenches in a bottom surface of a base substrate having a top surface and the bottom surface and formed of a conductive material; filling the first grooves or trenches with resin; curing the resin; removing exposed portions of the resin overfilled in the first grooves or trenches; etching the top surface of the base substrate to expose at least portions of the resin filled in the first grooves or trenches; and forming a second groove or a second trench in the bottom surface of the base substrate.

Abstract: A first insulation layer includes a concave portion formed in a lower surface thereof. A first wiring layer is formed in the concave portion. A protective insulation layer has an opening configured to expose a part of the first wiring layer and is stacked on the lower surface of the first insulation layer. An adhesion layer is interposed between the first wiring layer and the protective insulation layer and has higher adhesiveness with the protective insulation layer than the first wiring layer. The first wiring layer includes a pad portion formed in the concave portion and a protrusion protruding from a portion of a lower surface of the pad portion into the opening. The adhesion layer is formed to cover the lower surface of the pad portion and a side surface of the protrusion and to expose a lower end face of the protrusion.

Abstract: The invention relates to a method for obtaining a leaktight electronic device according to which provision is made for steps consisting in: a) placing an electronic module (3) inside a mould (100), b) holding said electronic module away from the walls (101) of said mould with the aid of holding claws (200) each exhibiting an end which protrudes towards the interior of the mould, c) injecting into said mould a thermoplastic material able to harden so as to form a leaktight shell, said holding claws retracting towards the exterior of the mould during the injection of said thermoplastic material.

Abstract: An antenna module includes an antenna substrate, a first semiconductor package, disposed on the antenna substrate, including a first connection member including one or more first redistribution layers, electrically connected to the antenna substrate, and a first semiconductor chip disposed on the first connection member, and a second semiconductor package, disposed on the antenna substrate to be spaced apart from the first semiconductor package, including a second connection member including one or more second redistribution layers, electrically connected to the antenna substrate, and a second semiconductor chip disposed on the second connection member. The first semiconductor chip and the second semiconductor chip are different types of semiconductor chips.

Abstract: An electronic device that includes a printed board with a surface over which a heating element is mounted, and a hermetically sealed housing that has thermal conductivity and accommodates the printed board therein. The printed board has a through hole therein, and a projection on a surface of the housing is thermally coupled to the heating element through the through hole.

Abstract: An apparatus is provided which comprises: a processor die; a processor substrate having a region extended away from the processor die, wherein the processor die is mounted on the processor substrate, wherein the extended region has at least one signal interface which is connectable to a top-side connector; and an interposer coupled to the processor substrate and a motherboard.

Abstract: A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.