Abstract: The present disclosure discloses an assembly. The assembly includes a photonic chip and an electrical chip disposed side by side. The assembly also includes mold compound that encapsulates the photonic chip and the electrical chip. The assembly further includes a redistribution layer (RDL) that extends across the top surface of the photonic chip and the top surface of the electrical chip and connects the photonic chip with the electrical chip. Moreover, the photonic chip includes an exposed optical interface for transmitting optical signals between the photonic chip and an external optical device.

Abstract: Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member proximate to the semiconductor die. The support member is at least substantially rigid. The packages can further include an adhesive between the support member and the semiconductor die and adhesively attaching the support member to the semiconductor die. The packages can also include a substrate carrying the semiconductor die and the support member attached to the semiconductor die.

Abstract: Illumination systems with selectively adjustable illumination patterns which reduce the need for a utility or luminaire distributer to stock luminaires with different illumination patterns and reduce the need for pre-planning installations. Implementations may allow scheduled dimming of luminaires, dimming in defined physical directions and scheduled adjustment of light patterns. The efficiency and/or color contrast of a luminaire may be improved by using wavelength shifting material, such as a phosphor, to absorb less desired wavelengths and transmit more desired wavelengths. A transmissive filter may reflect desired wavelengths such as red and green, while passing less desired wavelengths (e.g., blue) toward the wavelength shifting material which emits such as light of more desirable wavelengths.

Abstract: A conversion element for the wavelength conversion of electromagnetic radiation from a first wavelength range to electromagnetic radiation from a second wavelength range, which includes longer wavelengths than the first wavelength range, the conversion element includes: a matrix material, the optical refractive index of which is temperature-dependent, and at least two different types of luminophore particles wherein a multiplicity of luminophore particles of each of the types are distributed in the matrix material, luminophore particles of different types differ from one another in terms of average particle size and/or material, the conversion element, upon excitation by electromagnetic radiation from the first wavelength range emits mixed radiation including electromagnetic radiation from the first and the second wavelength range, and the correlated color temperature and/or the color locus of the mixed radiation remain(s) substantially the same when the matrix material is at a temperature of between 25° C.

Abstract: When a plating layer is formed on through holes in semiconductor packages, first and second stacked bodies are stacked with first and second cavities formed in the first and second stacked bodies facing the inner side and are bonded together by applying adhesive to peripheral regions so that the cavities of the first and second stacked bodies form sealed spaces, and the through holes are formed such that part of the first and second stacked bodies including the bonding surface remains. Then, the through holes are plated to form the plating layer, the peripheral regions are removed as cutting allowances, i.e., removal regions, and the first and second stacked bodies are divided into a plurality of pieces along dicing lines to form semiconductor packages.

Abstract: A method of transmit power control in a mobile telecommunications device is provided. One of a plurality of signal paths providing different output power and different gains is assigned in a first gain adjustment and a first power measurement in a current time slot. The same one of the signal paths is assigned in at least a second gain adjustment and a second power measurement in the same current time slot.

Abstract: An electronic device includes a package, a plurality of external leads extending outside the package, a first die within the package having one or more first contacts electrically coupled to at least a first one of the external leads, and a second die within the package having one or more second contacts electrically coupled to at least a second one of the external leads. A capacitive coupling may be positioned between the first and second die to allow electrostatic discharge (ESD) current to flow between the first die and the second die in response to an ESD event and to electrically isolate the first and second die from each other in the absence of the ESD event.

Abstract: A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and at least one deep well within the at least one device layer. A protective layer is disposed over the at least one deep well, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 106 Ohm-cm.

Abstract: A package structure, an electronic device and a method for manufacturing the package structure are presented. The package structure comprises: a substrate (100), a sensing module (200) disposed on an upper surface of the substrate (100) and electrically connected to the substrate (100), and a package colloid (300) disposed on the upper surface of the substrate (100) and coating at least one portion of the sensing module (200), wherein the sensing module (200) comprises a capacitive sensor (210) and an optical sensor (220), and the package colloid (300) comprises at least one portion of a photic zone (310) disposed corresponding to the optical sensor (220). Thus, the capacitive sensor and the optical sensor can be packaged in one package structure, so as to improve the degree of integration of the package structure and save the package space.

Abstract: A method includes forming a multi-stacked electronic device having two or more electronic components, each of the electronic components includes a leadframe, the leadframes of each electronic component are physically joined together using a non-solder metal joining process to form a joint, and the joint is located outside a solder connection region.

Abstract: A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and a first member is fixed to a chip mounting surface side between a peripheral portion of the semiconductor chip and a peripheral portion of the chip mounting part. Also, the first member is sealed by the resin. Also, a length of the first part of the chip mounting part in the first direction is larger than a length of the semiconductor chip in the first direction, in a plan view.

Abstract: A combination underfill-dam and electrical-interconnect structure for an opto-electronic engine. The structure includes a first plurality of electrical-interconnect solder bodies. The first plurality of electrical-interconnect solder bodies includes a plurality of electrical interconnects. The first plurality of electrical-interconnect solder bodies, is disposed to inhibit intrusion of underfill material into an optical pathway of an opto-electronic component for the opto-electronic engine. A system and an opto-electronic engine that include the combination underfill-dam and electrical interconnect structure are also provided.

Abstract: A power module assembly has a plurality of electrically conducting layers, including a first layer and a third layer. One or more electrically insulating layers are operatively connected to each of the plurality of electrically conducting layers. The electrically insulating layers include a second layer positioned between and configured to electrically isolate the first and the third layers. The first layer is configured to carry a first current flowing in a first direction. The third layer is configured to carry a second current flowing in a second direction opposite to the first direction, thereby reducing an inductance of the assembly. The electrically insulating layers may include a fourth layer positioned between and configured to electrically isolate the third layer and a fifth layer. The assembly results in a combined substrate and heat sink structure. The assembly eliminates the requirements for connections between separate substrate and heat sink structures.

Abstract: Tamper-respondent assemblies and methods of fabrication are provided which include a multi-layer stack having multiple discrete component layers stacked and electrically connected together via a plurality of electrical contacts in between the component layers. Further, the tamper-respondent assembly includes a tamper-respondent electronic circuit structure embedded within the multi-layer stack. The tamper-respondent electronic circuit structure includes at least one tamper-respondent sensor embedded, at least in part, within at least one component layer of the multiple discrete component layers of the multi-layer stack. The tamper-respondent electronic circuit structure defines a secure volume within the multi-layer stack. For instance, the tamper-respondent electronic circuit structure may be fully embedded within the multi-layer stack, with monitor circuitry of the tamper-respondent electronic circuit structure residing within the secure volume within the multi-layer stack.

Abstract: A driver assembly comprises several semiconductor switches that are arranged in a plane so that distances between adjacent semiconductor switches in the plane are equally large, and so that each semiconductor switch has the same number of adjacent semiconductor switches.

Abstract: A semiconductor device includes a heat radiation cooling base, a first insulating substrate including first and second copper patterns disposed on lower and upper surfaces thereof, respectively, a semiconductor chip including a first main electrode and a control electrode disposed on a first principal surface, and a second main electrode disposed on a second principal surface thereof, and a second insulating substrate including third and fourth copper patterns disposed on lower and upper surfaces thereof, respectively. The second main electrode is bonded to the second copper pattern. The third copper pattern is bonded to at least one of the first main electrode and the control electrode of the semiconductor chip. The third copper pattern and the fourth copper pattern are electrically connected to each other.

Abstract: A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and at least one deep well within the at least one device layer. A protective layer is disposed over the at least one deep well, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 106 Ohm-cm.

Abstract: A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate includes depositing a first-side UBM layer on a first surface of the substrate, and forming a plurality of first-side metal bumps on the first surface of the substrate after the first-side UBM layer is deposited. The method includes forming a second-side UBM layer on a second side of the substrate, and the first surface and the second surface are opposite of each other. The method includes forming a plurality of second-side metal bumps on the second surface of the substrate after the second-side UBM layer is deposited. The method includes removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed. The method includes reflowing the plurality of first-side metal bumps and the plurality of second side metal bumps.

Abstract: A crack-stopping structure includes a semiconductor wafer comprising a plurality of dies defined by a plurality of scribe line regions, a plurality of metal patterns formed in the scribe line regions, and a plurality of groups of through silicon holes (TSHs) formed in the scribe line regions. The wafer further includes a front side and a back side, and the TSHs respectively include at least a bottom opening formed in the bottom side of the wafer. The groups of TSHs are formed between the metal patterns and the dies.

Abstract: Disclosed herein is a slim LED package. The slim LED package includes first and second lead frames separated from each other, a chip mounting recess formed on one upper surface region of the first lead frame by reducing a thickness of the one upper surface region below other upper surface regions of the first lead frame, an LED chip mounted on a bottom surface of the chip mounting recess and connected with the second lead frame via a bonding wire, and a transparent encapsulation material protecting the LED chip while supporting the first and second lead frames.

Abstract: An electronic package includes a semiconductor die, conductive pillars extending outwardly from the semiconductor die, and a liquid crystal polymer (LCP) body surrounding the semiconductor die and having openings therein receiving respective ones of the conductive pillars. A first interconnect layer is on the LCP body and contacts the openings. Conductive bodies are in the openings to connect the conductive pillars to the first interconnect layer.

Abstract: A light emitting device may include a substrate; a body which is disposed on the substrate and has a first hole having a predetermined size and a light emitting chip which is disposed within a cavity formed by the substrate and the first hole of the body. A cap may be disposed on the body and may have a second hole having a predetermined size. A transparent window may be disposed in the second hole. A lower portion of the cap is divided into a first surface and a second surface more projecting downwardly than the first surface, and at least a portion of the first surface is attached and fixed to the body.

Abstract: A method of forming an electrical device that includes forming ohmic contacts to a type III-V semiconductor substrate, and depositing a dielectric layer on the ohmic contacts and an exposed surface of the type III-V semiconductor substrate. A nanotube is positioned on a surface of the high-k dielectric that is overlying the type III-V semiconductor substrate and is between the ohmic contacts using chemical recognition. The dielectric layer is removed so that the nanotube is repositioned directly on the type III-V semiconductor substrate to provide an Schottky contact to a channel region of the type III-V semiconductor substrate.

Abstract: A power semiconductor module includes an insulated wiring board; semiconductor elements mounted on one main surface of the insulated wiring board; a heat radiation board bonded to another main surface of the insulated wiring board; a plurality of fins including a first group of fins each having one end fixed to the another main surface of the heat radiation board and another end with a free end; and a water jacket housing the plurality of fins and allowing coolant to flow among the plurality of fins. The plurality of fins further includes a second group of fins as reinforced fins each having one end fixed to the another main surface of the heat radiation board and another end bonded to the water jacket.

Abstract: A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate.

Abstract: A semiconductor device includes: a semiconductor element; a laminated substrate including an insulating plate and a circuit board which is arranged on the front surface of the insulating plate and on which the semiconductor element is arranged; a lead terminal provided via solder in a major electrode of the front surface of the semiconductor element; and a sealing resin for sealing the semiconductor element, the laminated substrate, and the lead terminal, wherein a value of “Young's modulus of the sealing resin×(linear expansion coefficient of the lead terminal?linear expansion coefficient of the sealing resin)” is equal to or greater than ?26×103 (Pa/° C.) and equal to or less than 50×103 (Pa/° C.).

Abstract: A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture.

Abstract: A semiconductor device includes a first die, a second die bonding to the first die thereby forming a bonding interface, and a pad of the first die and exposed from a polymeric layer of the first die. The semiconductor device further has a conductive material on the pad and extended from the pad in a direction parallel to a stacking direction of the first die and the second die. In the semiconductor device, the conductive material extended to a top surface, which is vertically higher than a backside of the second die, wherein the backside is a surface opposite to the bonding interface.

Abstract: A power module includes a substrate, a first sub-module and a second sub-module. The substrate includes plural first conducting parts, plural second conducting parts and a third conducting part. The first sub-module is disposed on the substrate, and includes a first semiconductor switch, a first diode, a first electrode, a second electrode and a third electrode. The first electrode and the second electrode are electrically connected with the corresponding first conducting parts. The third electrode is electrically connected with the third conducting part. The second sub-module is disposed on the substrate, and includes a second semiconductor switch, a second diode, a fourth electrode, a fifth electrode and a sixth electrode. The fourth electrode and the fifth electrode are electrically connected with the corresponding second conducting parts. The sixth electrode is electrically connected with the third conducting part.

Abstract: A method for fabricating an integrated fan-out package is provided. The method includes the following steps. A plurality of conductive posts are placed in apertures of a substrate. A carrier having an adhesive thereon is provided. The conductive posts are transferred to the carrier in a standing orientation by adhering the conductive posts in the apertures to the adhesive. An integrated circuit component is mounted onto the adhesive having the conductive posts adhered thereon. An insulating encapsulation is formed to encapsulate the integrated circuit component and the conductive posts. A redistribution circuit structure is formed on the insulating encapsulation, the integrated circuit component, and the conductive posts, wherein the redistribution circuit structure is electrically connected to the integrated circuit component and the conductive posts. The carrier is removed. At least parts of the adhesive are removed (e.g. patterned or entirely removed) to expose surfaces of the conductive posts.

Abstract: A physical quantity sensor includes: a physical quantity sensor chip which detects a physical quantity and generates an electrical signal; a package which has an internal space and accommodates the physical quantity sensor chip in the internal space; and a first wire which connects the package and the physical quantity sensor chip together. The physical quantity sensor chip is moored in the internal space by the first wire.

Abstract: A portable electronic device includes a touch input apparatus including a touch panel installed on a surface of a display, the touch panel has a lead part projecting at the end of a detecting section, which includes a matrix area A where X value detection lines and Y value detection lines are arranged in matrix, and a lead area B where a plurality of lead lines extending from the matrix area A in the same direction as the X value detection lines to reach the lead part are arranged, wherein a first touch input section is formed by the matrix area A of the touch panel, and a second touch input section is formed by the lead area B.

Abstract: A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and at least one deep well within the at least one device layer. A protective layer is disposed over the at least one deep well, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 106 Ohm-cm.

Abstract: The semiconductor device includes a semiconductor element, a main lead and a resin package. The semiconductor element includes an obverse surface and a reverse surface spaced apart from each other in a thickness direction. The main lead supports the semiconductor element via the reverse surface of the semiconductor element. The resin package covers the entirety of the semiconductor element. The resin package covers the main lead in such a manner that a part of the main lead is exposed from the resin package. The semiconductor element includes a part that does not overlap the main lead as viewed in the thickness direction.

Abstract: An intergrated circuit (IC) package includes a die, a package substrate coupled to the die, and a first electrostatic discharge (ESD) protection component coupled to the package substrate, where the first electrostatic discharge (ESD) protection component is configured to provide package level electrostatic discharge (ESD) protection. In some implementations, the first electrostatic discharge (ESD) protection component is embedded in the package substrate. In some implementations, the die includes an internal electrostatic discharge (ESD) protection component configured to provide die level electrostatic discharge (ESD) protection. In some implementations, the internal electrostatic discharge (ESD) protection component and the first electrostatic discharge (ESD) protection component are configured to provide cumulative electrostatic discharge (ESD) protection for the die.

Abstract: A waterproof electronic device includes: an electronic component module having an electronic component including a semiconductor element, a heat dissipating member provided on the electronic component in a thermally conductive manner, and an insulating material that surrounds the electronic component in such a manner that one surface of the heat dissipating member is exposed; and a waterproof film that is formed at least on whole surfaces in regions of the electronic component module that are to be immersed in a coolant.

Abstract: An OLED package structure includes a substrate, a package lid arranged opposite to the substrate, an OLED device arranged between the substrate and the package lid and mounted to the substrate, and enclosure resin located between the substrate and the package lid and bonding the substrate and the package lid together. The package lid includes a recess formed therein at a location corresponding to the OLED device. The recess includes therein a plurality of corrugation projection structures arranged therein and extending outwards from a bottom of the recess. Desiccant is attached to the bottom of the recess in an area between two adjacent ones of the corrugation projection structures.

Abstract: Readily modifiable and customizable, low-area overhead interconnect structures for forming connections between a system-in-a-package module and other components in an electronic device. One example may provide an interposer for providing an interconnection between a system-in-a-package module and other components in an electronic device. Another may provide a plurality of conductive pins or contacts to form interconnect paths between a module and other components.

Abstract: A semiconductor die that may include a substrate; an epitaxial layer; a metal layer; a first transistor; and a metal via that surrounds the first transistor, extends between the metal layer and the substrate, and penetrates the substrate.

Abstract: A printed circuit board, an in-circuit test structure and a method for producing the in-circuit test structure thereof are disclosed. The in-circuit test structure comprises a via and a test pad. The via passes through the printed circuit board for communicating with an electrical device to be tested on the printed circuit board. The test pad is formed on an upper surface of the printed circuit board and covering the via, wherein a center of the via deviates from a center of the test pad. In the in-circuit test, the accuracy of the test data can be improved by means of the in-circuit test structure provided by the present invention, and thus the reliability of the test result is ensured. Also, the test efficiency of the in-circuit test is improved.

Abstract: A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and at least one deep well within the at least one device layer. A protective layer is disposed over the at least one deep well, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 106 Ohm-cm.

Abstract: Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film.

Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.

Abstract: A package on package may include: a first printed circuit board (PCB); a bottom package which includes a first chip die and a second chip die attached to the first PCB; a top package which includes a second PCB and a third chip die attached to the second PCB, and is overlaid over the bottom package; and/or first stack connection solder balls and second stack connection solder balls which are electrically connected between the first PCB and the second PCB, and are formed only around two sides facing each other among sides of the bottom package.

Abstract: An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The metal layer and the hollow metal pillar are electrically connected.

Abstract: A semiconductor package interconnect system may include a conductive pillar having a core, a first layer surrounding the core, and a second layer surrounding the first layer. The core may be composed of a drawn copper wire, the first layer may be composed of nickel, and the second layer may be composed of a solder. A method for manufacturing a semiconductor package with such a conductive pillar may include placing a plurality of conductive pillars on a substrate using a stencil process.

Abstract: A semiconductor package includes a leadframe having a clip foot portion, the clip foot portion having a first tie bar, a conductive clip situated over the leadframe, the conductive clip including a first lock fork having at least two prongs around the first tie bar so as to secure the conductive clip to the clip foot portion of the leadframe. The conductive clip includes a second lock fork having at least two prongs around a second tie bar of the clip foot portion. The conductive clip is electrically coupled to the clip foot portion of the leadframe. The clip foot portion of the leadframe includes exposed leads. The semiconductor package also includes at least one semiconductor device situated on the leadframe. The at least one semiconductor device is coupled to a driver integrated circuit situated on the leadframe.

Abstract: The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method.

Abstract: A bonding film has at least a left longitudinal branch, and a lower latitudinal branch; a first bonding area is configured in a first branch, and a second bonding area is configured in a second branch. A plurality of outer top metal pads and a plurality of inner top metal pads are exposed on a top surface within each bonding area. A central chip is configured in a central area of the bonding film and is electrically coupled to the inner top metal pad, and at least two peripheral chips are configured neighboring to the central chip and electrically coupled to the outer top metal pads. Each of the inner top metal pads is electrically coupled to a corresponding outer top metal pad through an embedded circuitry. The central chip communicates with the peripheral chips through the inner top metal pad, embedded circuitry, and outer top metal pad of the bonding film.

Abstract: PoP devices and methods of forming the same are disclosed. A PoP device includes a first package structure and a second package structure. The first package structure includes a first chip, and a plurality of active through integrated fan-out vias and a plurality of dummy through integrated fan-out vias aside the first chip. The second package structure includes a plurality active bumps bonded to the plurality of active through integrated fan-out vias, and a plurality of dummy bumps bonded to the plurality of dummy through integrated fan-out vias. Besides, a total number of the active through integrated fan-out vias and the dummy through integrated fan-out vias at a first side of the first chip is substantially the same as a total number of the active through integrated fan-out vias and the dummy through integrated fan-out vias at a second side of the first chip.