Abstract: A method for forming passivated through wafer vias, passivated through wafer via structures, and passivated through wafer via design structures. The method includes: forming a through wafer via in a semiconductor substrate, the through wafer via comprising an electrical conductor extending from a top of the semiconductor substrate to a bottom surface of the semiconductor substrate; and forming a doped layer abutting all sidewalls of the electrical conductor, the doped layer of a same dopant type as the semiconductor substrate, the concentration of dopant in the doped layer greater than the concentration of dopant in the semiconductor substrate, the doped layer intervening between the electrical conductor and the semiconductor substrate.

Abstract: A system and method for forming photoresists over semiconductor substrates is provided. An embodiment comprises a photoresist with a concentration gradient. The concentration gradient may be formed by using a series of dry film photoresists, wherein each separate dry film photoresist has a different concentration. The separate dry film photoresists may be formed separately and then placed onto the semiconductor substrate before being patterned. Once patterned, openings through the photoresist may have a tapered sidewall, allowing for a better coverage of the seed layer and a more uniform process to form conductive materials through the photoresist.

Abstract: After formation of a semiconductor device on a semiconductor-on-insulator (SOI) layer, a first dielectric layer is formed over a recessed top surface of a shallow trench isolation structure. A second dielectric layer that can be etched selective to the first dielectric layer is deposited over the first dielectric layer. A contact via hole for a device component located in or on a top semiconductor layer is formed by an etch. During the etch, the second dielectric layer is removed selective to the first dielectric layer, thereby limiting overetch into the first dielectric layer. Due to the etch selectivity, a sufficient amount of the first dielectric layer is present between the bottom of the contact via hole and a bottom semiconductor layer, thus providing electrical isolation for the ETSOI device from the bottom semiconductor layer.

Abstract: A method of making templated circuitry employs a template system that includes a template of an insulator material on a carrier having a conductive surface. The template includes multiple levels and multiple regions, wherein a first level exposes the conductive surface of the carrier. A first metal is electrochemically deposited on the conductive surface in first regions of the first level. A circuit material is deposited to cover the first metal. The template is etched until a second level of the template exposes the conductive surface in second regions on opposite sides of the first regions. A second metal is electrochemically deposited on the conductive surface in the second regions. The template of deposited materials is transferred from the carrier to a substrate.

Abstract: A semiconductor device includes a plurality of protrusions formed on a first face of the semiconductor device; first bonding portions formed on upper portions of the plurality of protrusions; second bonding portions formed on side faces of the plurality of protrusions; and third bonding portions formed on the first face between the plurality of protrusions, wherein the semiconductor device is configured to bond to an other semiconductor device through the third from the first bonding portions.

Abstract: In an inverted staggered type TFT (100), contact layers (150a and 150b) that electrically connect a channel layer (140) to source and drain electrodes (160a and 160b), respectively, include n+ amorphous silicon layers (151a and 151b), n+ microcrystalline silicon layers (152a and 152b), and n+ microcrystalline silicon layers (153a and 153b). The n+ microcrystalline silicon layers (152a and 152b) have a lower crystallization rate than the n+ microcrystalline silicon layers (153a and 153b) and are formed between the n+ amorphous silicon layers (151a and 151b) and the n+ microcrystalline silicon layers (153a and 153b). In this case, since the film thickness of incubation layers formed on surfaces of the n+ amorphous silicon layers (151a and 151b) decreases, the resistance value of the contact layers (150a and 150b) decreases. By this, the contact resistance of the TFT (100) decreases and the mobility can be increased.

Abstract: A conductor contact structure includes a conductor line, a dielectric layer and a contact hole. The conductor line includes a first zone and a second zone. The first zone extends along a symmetry axis and is symmetrical with respect to the symmetry axis. The second zone extends along the symmetry axis but is not symmetrical with respect to the symmetry axis. A distance between a first edge of the second zone and the symmetry axis is greater than a distance between a second edge of the second zone and the symmetry axis. A contact hole is formed in the dielectric layer and in communication with the second zone. A diameter of the contact hole is smaller than a distance between the first edge and the second edge of the second zone.

Abstract: A donor silicon wafer may be bonded to a substrate and a lamina cleaved from the donor wafer. A photovoltaic cell may be formed from the lamina bonded to the substrate. An intermetal stack is described that is optimized for use in such a cell. The intermetal stack may include a titanium layer in contact with the lamina, which reacts to form titanium silicide, a non-reactive barrier layer to check the silicide reaction, a low-resistance layer, and an adhesion layer to help adhesion to the receiver element.

Abstract: Methods form an integrated circuit structure by forming at least a portion of a plurality of devices within and/or on a substrate and patterning trenches in an inter-layer dielectric layer on the substrate adjacent the devices. The patterning forms relatively narrow trenches and relatively wide trenches. The methods then perform an angled implant of a compensating material into the trenches. The angle of the angled implant implants a greater concentration of the compensating material in the regions of the substrate at the bottom of the wider trenches relative to an amount of compensating material implanted in the regions of the substrate at the bottom of the narrower trenches. The methods then deposit a metallic material within the trenches and heat the metallic material to form silicide from the metallic material.

Abstract: A method includes depositing a dummy fill material over exposed portions of a substrate and a gate stack disposed on the substrate, removing portions of the dummy fill material to expose portions of the substrate, forming a layer of spacer material over the exposed portions of the substrate, the dummy fill material and the gate stack, removing portions of the layer of spacer material to expose portions of the substrate and the dummy fill material, depositing a dielectric layer over the exposed portions of the spacer material, the substrate, and the gate stack, removing portions of the dielectric layer to expose portions of the spacer material, removing exposed portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer, and depositing a conductive material in the at least one cavity.

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a carrier. The carrier has a first surface and a second surface opposite to the first surface. The carrier includes an inner core layer and an exterior clad layer, and the inner core layer is covered by the exterior clad layer.

Abstract: Pillars having a directed compliance geometry are arranged to couple a semiconductor die to a substrate. The direction of maximum compliance of each pillar may be aligned with the direction of maximum stress caused by unequal thermal expansion and contraction of the semiconductor die and substrate. Pillars may be designed and constructed with various shapes having particular compliance characteristics and particular directions of maximum compliance. The shape and orientation of the pillars may be selected as a function of their location on a die to accommodate the direction and magnitude of stress at their location. A method includes fabricating pillars with particular shapes by patterning to increase surface of materials upon which the pillar is plated or deposited.

Abstract: A method of forming a semiconductor device includes forming a silicide contact region of a field effect transistor (FET); forming a shallow impurity region in a top surface of the silicide contact region; and forming a stressed liner over the FET such that the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, wherein the shallow impurity region comprises one or more impurities, and is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region.

Abstract: A light emitting diode chip includes a substrate, an epitaxial layer, two inclined plane units, and two electrode units. The substrate has top and bottom surfaces. The epitaxial layer is disposed on the top surface of the substrate. Each of the inclined plane units is inclined downwardly and outwardly from the epitaxial layer toward the bottom surface of the substrate, and includes an inclined sidewall formed on the epitaxial layer, and a substrate inclined wall formed on the substrate. Each of the electrode units includes an electrode disposed on the epitaxial layer, and a conductive portion extending from the electrode to the substrate inclined wall along corresponding one of the inclined plane units.

Abstract: Generally, the subject matter disclosed herein relates to methods for forming modern sophisticated semiconductor devices, and more specifically, methods wherein substantially lead-free solder bumps may be formed above a contact layer of a semiconductor chip. One illustrative method disclosed herein includes forming a solder bump above a metallization layer of a semiconductor device, removing an oxide film from a surface of the solder bump, and, after removing the oxide film, performing a solder bump reflow process in a reducing ambient to reflow the solder bump.

Abstract: A microelectronic package may have a plurality of terminals disposed at a face thereof which are configured for connection to at least one external component. e.g., a circuit panel. First and second microelectronic elements can be affixed with packaging structure therein. A first electrical connection can extend from a respective terminal of the package to a corresponding contact on the first microelectronic element, and a second electrical connection can extend from the respective terminal to a corresponding contact on the second microelectronic element, the first and second connections being configured such that a respective signal carried by the first and second connections in each group is subject to propagation delay of the same duration between the respective terminal and each of the corresponding contacts coupled thereto.

Abstract: A method for manufacturing a thin semiconductor package includes providing a lead frame with a removable substrate that has an attaching surface attached to a first surface of the lead frame. The lead frame is formed from an electrically conductive sheet and has leads that extend inwardly from a lead frame boundary towards a central region of the lead frame. A semiconductor die is mounted on the removable substrate at the central region. The semiconductor die has a connection pad surface with die pads on it, and the connection pad surface is attached to the attaching surface of the removable substrate. The lead frame and die are encapsulated with a first encapsulant so that the lead frame is sandwiched between the first encapsulant and the removable substrate. The removable substrate is removed from the lead frame to expose the first surface of the lead frame and then the die pads are electrically connected to respective ones of the leads.

Abstract: A method for larger-area fabrication of uniform silicon nanowire arrays is disclosed. The method includes forming a metal layer with a predetermined thickness on a substrate whose surface has a silicon material by a coating process, the metal layer selected from the group consisting of Ag, Au and Pt; and performing a metal-induced chemical etching for the silicon material by using an etching solution. Accordingly, a drawback that Ag nanoparticles are utilized to perform the metal-induced chemical etching in prior art is solved.

Abstract: A method includes forming an under-bump metallurgy (UBM) layer overlying a substrate, and forming a mask overlying the UBM layer. The mask covers a first portion of the UBM layer, and a second portion of the UBM layer is exposed through an opening in the mask. A metal bump is formed in the opening and on the second portion of the UBM layer. The mask is then removed. A laser removal is performed to remove a part of the first portion of the UBM layer and to form an UBM.

Abstract: Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.

Abstract: A method for fabricating a semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer comprises metal interconnects therein; forming a top metal layer on the dielectric layer; and forming a passivation layer on the top metal layer through high-density plasma chemical vapor deposition (HDPCVD) process.

Abstract: A method for forming a device is disclosed. A substrate having first and second major surfaces is provided. A stress buffer is formed in the substrate. A through silicon via (TSV) contact is formed between the stress buffer. The stress buffer has a depth less than a depth of the TSV contact. The stress buffer alleviates stress created by the difference in coefficient thermal expansion (CTE) between the TSV contact and the substrate.

Abstract: A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.

Abstract: On embodiment is directed to a welding pad capable of receiving a ball-shaped copper wire at its end, including a first copper pad coated with a protection layer and topped with a second pad containing aluminum having dimensions smaller than those of the first pad and smaller than the ball diameter once said ball has been welded to the welding pad.

Abstract: Certain examples relate to improved methods for making patterned substantially transparent contact films, and contact films made by such methods. In certain cases, the contact films may be patterned and substantially planar. Thus, the contact films may be patterned without intentionally removing any material from the layers and/or film, such as may be required by photolithography. In certain example embodiments, an oxygen exchanging system comprising at least two layers may be deposited on a substrate, and the layers may be selectively exposed to heat and/or energy to facilitate the transfer of oxygen ions or atoms from the layer with a higher enthalpy of formation to a layer with a lower enthalpy of formation. In certain cases, the oxygen transfer may permit the conductivity of selective portions of the film to be changed. This advantageously may result in a planar contact film that is patterned with respect to conductivity and/or resistivity.

Abstract: A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.

Abstract: A semiconductor device with reduced defect density is fabricated by forming localized metal silicides instead of full area silicidation. Embodiments include forming a transistor having a gate electrode and source/drain regions on a substrate, forming a masking layer with openings exposing portions of both the gate electrode and source/drain regions over the substrate, depositing metal in the openings on the exposed portions, forming silicides in the openings, and removing unreacted metal and the masking layer.

Abstract: A method of forming a semiconductor device includes forming a dummy metal gate layer including work function metals directly on a base insulator, diffusing the work function metals into the base insulator by annealing, removing the dummy metal gate layer by a wet etching, forming a metal gate on the base insulator, and forming a high-k insulator on the metal gate.

Abstract: In one exemplary embodiment, a method includes: providing a structure having a first layer overlying a substrate, where the first layer includes a dielectric material having a plurality of pores; applying a filling material to an exposed surface of the first layer; heating the structure to a first temperature to enable the filling material to homogeneously fill the plurality of pores; after filling the plurality of pores, performing at least one first process on the structure; after performing the at least one first process, removing the filling material from the plurality of pores by heating the structure to a second temperature to decompose the filling material; and after removing the filling material from the plurality of pores, performing at least one second process on the structure, where the at least one second process is performed at a third temperature that is greater than the second temperature.

Abstract: A method includes forming an opening in a dielectric layer, and forming a silicon rich layer on a surface of the dielectric layer. A portion of the silicon rich layer extends into the opening and contacts the dielectric layer. A tantalum-containing layer is formed over and the contacting the silicon rich layer. An annealing is performed to react the tantalum-containing layer with the silicon rich layer, so that a tantalum-and-silicon containing layer is formed.

Abstract: The present invention proposes the use of a silicon nitride layer on top of a second conductive layer. After a step of etching a second conductive layer, an oxide spacer is formed to define a gap. Then, another silicon nitride layer fills up the gap. After that, the oxide spacer is removed. Later, a first conductive layer is etched to separate the digit line to cell contact line.

Abstract: A method for fabricating a metal-oxide-semiconductor field-effect transistor includes the following steps. Firstly, a substrate is provided. A gate structure, a first spacer, a second spacer and a source/drain structure are formed over the substrate. The second spacer includes an inner layer and an outer layer. Then, a thinning process is performed to reduce the thickness of the second spacer, thereby retaining the inner layer of the second spacer. After a stress film is formed on the inner layer of the second spacer and the source/drain structure, an annealing process is performed. Afterwards, the stress film is removed.

Abstract: A layered structure and semiconductor device and methods for fabricating a layered structure and semiconductor device. The layered structure includes: a base layer including a material containing titanium nitride, tantalum nitride, or a combination thereof; a conductive layer including a material containing: tantalum aluminum nitride, titanium aluminum nitride, tantalum silicon nitride, titanium silicon nitride, tantalum hafnium nitride, titanium hafnium nitride, hafnium nitride, hafnium carbide, tantalum carbide, vanadium nitride, niobium nitride, or any combination thereof; and a tungsten layer. The semiconductor device includes: a semiconductor substrate; a base layer; a conductive layer; and a tungsten layer.

Abstract: Metal contact formation for molecular device junctions by surface-diffusion-mediated deposition (SDMD) is described. In an example, a method of fabricating a molecular device junction by surface-diffusion-mediated deposition (SDMD) includes forming a molecular layer above a first region of a substrate. A region of metal atoms is formed above a second region of the substrate proximate to, but separate from, the first region of the substrate. A metal contact is then formed by migrating metal atoms from the region of metal atoms onto the molecular layer.

Abstract: Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a first polymer film to a side of a semiconductor chip and forming a first underbump metallization structure with at least a portion on the first polymer film. A second polymer film is applied on the first polymer film with an opening exposing a portion of the first underbump metallization structure.

Abstract: An integrated circuit (IC) having a concentric arrangement of stacked vias is disclosed. The IC includes first and second pluralities of signal lines on first and second metal layers, respectively. The second metal layer is arranged between the first metal layer and a silicon layer. The IC also includes a via structure implemented in a predefined area, and connects each of the first and second pluralities of signal lines to circuitry in the silicon layer through respective first and second pluralities of vias. Each via of the first and second pluralities has a center point that extends along a vertical axis from its respective metal layer to the silicon layer. Centers of each of the second plurality of vias are closer to a perimeter of the predefined area than respective centers of any of the first plurality of vias.

Abstract: A microelectronic device comprises a first surface (110, 710), a second surface (120, 720), and a passageway (130, 730) extending from the first surface to the second surface. The passageway contains a plurality of electrically conductive channels (131, 132, 231, 232) separated from each other by an electrically insulating material (133, 1133).

Abstract: A method for forming large substantially defect-free void areas on a semiconductor integrated circuit chip includes processing the chip through the passivation level processing operations then forming one or more openings in a designated blank area of the integrated circuit chip in a separate dedicated etching operation. The one or more openings may constitute 5-10% or more of the total area of the semiconductor chip. The void areas are deep trench openings that extend through the passivation layer and through all of the other material layers in the blank area exposing the substrate surface in one embodiment and through all material layers except for a field oxide layer formed directly on the substrate in another embodiment.

Abstract: A semiconductor structure includes a dielectric layer disposed over a substrate. A metallic line is disposed in the dielectric layer. A through-silicon-via (TSV) structure continuously extends through the dielectric layer and the substrate. A surface of the metallic line is substantially leveled with a surface of the TSV structure.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, wiring lines formed above the semiconductor substrate, and an air gap formed between the adjacent wiring lines. In the semiconductor device, top surfaces and side walls of the wiring lines are covered with the diffusion prevention film, and the air gap is in contact with the interconnects via a diffusion prevention film.

Abstract: A method of manufacturing a semiconductor device includes preparing a semiconductor element including a main surface over which a wiring layer is formed, forming a seed layer over the main surface, forming a resist layer over the main surface such that the resist layer covers the seed layer, removing a part of the resist layer by exposing and developing the resist layer, in which a part of the wiring layer is exposed from the removed part of the resist layer, forming a plurality of conductive posts electrically connected to the wiring layer at the removed part of the resist layer, forming a solder layer at each top of the plurality of conductive posts, removing a residual resist layer over the main surface, removing an area other than an area which overlaps with the seed layer, and melting the solder layer and forming a surface shape.

Abstract: A three-dimensional semiconductor device includes a semiconductor substrate, a plurality of conductive layers and insulating layers, and a plurality of contacts. The plurality of conductive layers and insulating layers are stacked alternately above the semiconductor substrate. The plurality of contacts extend in a stacking direction of the plurality of conductive layers and insulating layers. The plurality of conductive layers form a stepped portion having positions of ends of the plurality of conductive layers gradually shifted from an upper layer to a lower layer. The plurality of contacts are connected respectively to each of steps of the stepped portion. The stepped portion is formed such that, at least from an uppermost conductive layer to a certain conductive layer, the more upwardly the conductive layer is located, the broader a width of the step is.

Abstract: A metal oxide bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a desired composition and crystal structure. An example is crystalline MoO2 if the dielectric layer is TiO2 in the rutile phase. The other component of the bilayer (i.e. top layer) is a sub-oxide of the same material as the bottom layer. The top layer serves to protect the bottom layer from oxidation during subsequent PMA or other DRAM fabrication steps by reacting with any oxygen species before they can reach the bottom layer of the bilayer second electrode.

Abstract: Provided are methods of depositing N-Metals onto a substrate. Methods include first depositing an initiation layer. The initiation layer may comprise or consist of cobalt, tantalum, nickel, titanium or TaAlC. These initiation layers can be used to deposit TaCx.

Abstract: In one embodiment, a method includes forming a first pad for coupling to a first terminal of a first transistor of a monolithic darlington transistor configuration and forming a second pad for coupling to a first terminal of a second transistor of the monolithic darlington transistor configuration. The method then forms a third pad for coupling to an external component for the monolithic darlington transistor configuration. The third pad is coupled to a second terminal of the first transistor and a second terminal of the second transistor of the monolithic darlington transistor configuration.

Abstract: A layered chip package includes a main body and wiring. The main body has a main part. The main part has a top surface and a bottom surface and includes a plurality of layer portions that are stacked. The wiring includes a plurality of lines passing through all the plurality of layer portions. Each layer portion includes a semiconductor chip and a plurality of electrodes. The semiconductor chip has a first surface, and a second surface opposite thereto. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. The plurality of layer portions include two or more pairs of first and second layer portions in each of which the first and second layer portions are arranged so that the first or second surfaces of the respective semiconductor chips face each other. The plurality of electrodes include a plurality of first connection parts and a plurality of second connection parts.

Abstract: According to one embodiment of the invention, the gate contact is formed by a selective deposition on the gate electrode. One acceptable technique for the selective deposition is by plating. Plating is one process by which a metal structure, such as a gate contact, may be formed directly on the gate electrode. The plating is carried out by immersing the semiconductor die in a plating solution with the gate electrode exposed. The gate contact is plated onto the gate electrode and thus is ensured of being fully aligned exactly to the gate electrode. After this, the appropriate dielectric layers are formed adjacent the gate contact and over the source and drain to ensure that the gate electrode is electrically isolated from other components of the transistor.

Abstract: Contact openings are produced in a semiconductor body by forming a plurality of self-aligned structures on a main surface of a semiconductor body, each self-aligned structure filling a trench formed in the semiconductor body and extending above and onto the main surface. Adjacent ones of the self-aligned structures have spaced apart sidewalls which face each other. A spacer layer is formed on the sidewalls of the self-aligned structures. Openings are formed in the semiconductor body between adjacent ones of the self-aligned structures while the spacer layer is on the sidewalls of the self-aligned structures. Each opening has a width and a distance to the sidewall of an adjacent trench which corresponds to a thickness of the spacer layer. Self-aligned contact structures can also be produced on a semiconductor body, with or without using the spacer layer.

Abstract: Methods and structure are provided for creating and utilizing hard masks to facilitate creation of a grating effect to control an anisotropic etching process for the creation of an opening, and subsequent formation of a interconnect structure (e.g., a via) in a multilayered semiconductor device. A first hard mask can be patterned to control etching in a first dimension, and a second hard mask can be patterned to control etching in a second dimension, wherein the second hard mask is patterned orthogonally opposed to the first hard mask. A resist can be patterned by inverting the pattern of a metal line patterning. Interconnects can be formed with critical dimension(s) and also self-aligned.

Abstract: The invention relates to zinc-containing glass compositions useful in conductive pastes for silicon semiconductor devices and photovoltaic cells.