Abstract: A method of manufacturing a semiconductor device which includes a first gate wiring layer and a second gate wiring layer adjacent to each other; a first diffused layer provided on a side between the wiring layers; a second diffused layer provided on one side external to the side between the wiring layers; and a third diffused layer provided on the other side external to the side between the wiring layers, the method including: forming a first mask including an opening; implanting a channel impurity for threshold voltage control using the first mask; forming a first diffused layer using the first mask by implanting a first impurity; forming a first gate wiring layer and a second gate wiring layer after removing the first mask; and forming a second diffused layer and a third diffused layer using the first gate wiring layer and the second gate wiring layer as a second mask by implanting a second impurity.

Abstract: A memory device able to be produced without requiring high precision alignment, a method of production of the same, and a method of use of a memory device produced in this way, wherein a peripheral circuit portion (first semiconductor portion) formed by a first minimum processing dimension is formed on a substrate, a memory portion (second semiconductor portion) formed by a second minimum processing dimension smaller than the first minimum processing dimension is stacked above it, and the memory portion (second semiconductor portion) is stacked with respect to the peripheral circuit portion (first semiconductor portion) with an alignment precision rougher than the second minimum processing dimension or wherein memory cells configured by 2-terminal devices are formed in regions where word lines and bit lines intersect in the memory portion, and contact portions connecting the word lines and bit lines and the peripheral circuit portions are arranged in at least two columns in directions in which the word lines

Abstract: Capacitors having upper electrodes that include a lower electrode, a dielectric layer and an upper electrode that includes a conductive metal nitride layer and a doped polysilicon germanium layer are provided. At least part of the conductive metal nitride layer is oxidized and/or at least part of the dielectric layer is nitridized.

Abstract: A semiconductor device includes: a semiconductor substrate; a memory cell selection transistor that is formed on the semiconductor substrate and has a source and a drain; a contact plug; a polysilicon interlayer film that is formed above the memory cell selection transistor and has a cylinder-shaped through-hole; and a storage capacity part that is formed in the through-hole and is connected to the source and the drain of the memory cell selection transistor via the contact plug, wherein a boundary between a bottom and a side wall of the through-hole has a curved surface.

Abstract: The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.

Abstract: A semiconductor device able to secure electrical effective thicknesses required for insulating films of electronic circuit elements by using depletion of electrodes of the electronic circuit elements even if the physical thicknesses of the insulating films are not different, where gate electrodes of high withstand voltage use transistors to which high power source voltages are supplied contain an impurity at a relatively low concentration, so the gate electrodes are easily depleted at the time of application of the gate voltage; depletion of the gate electrodes is equivalent to increasing the thickness of the gate insulating films; the electrical effective thicknesses required of the gate insulating films can be made thicker; and the gate electrodes of high performance transistors for which a high speed and large drive current are required do not contain an impurity at a high concentration where depletion of the gate electrodes will not occur, so the electrical effective thickness of the gate insulating films

Abstract: Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.

Abstract: The present invention provides an integrated semiconductor memory device comprising: a semiconductor substrate; a plurality of active area lines formed in said semiconductor substrate, each of which active area lines includes a plurality of memory cell selection transistors having a respective wordline contact, bitline contact, and node contact; a plurality of filled insulation trenches arranged between said active area lines; a plurality of rewiring stripes each of which rewires an associated node contact of a memory cell selection transistor from an active area line to above a neighboring filled insulation trench so as to form a respective rewired node contact; a plurality of bitlines being aligned with and running above said active area lines which bitlines are connected to the bitline contacts of the memory cell selection transistors of the respective active area lines; a plurality of wordlines running perpendicular to said bitlines which are connected to the wordline contacts of the memory cell selection

Abstract: A low voltage coefficient MOS capacitor includes first and second dielectric layers between first and second capacitor plates, with a common plate separating the dielectric layers. First and second terminals are coupled to first and second capacitor plates.

Abstract: The invention relates to a DRAM memory device with a capacity associated with a field effect transistor, in which all or some of the molecules capable of storing the loads comprising a polyoxometallate are incorporated into the capacity, or a flash-type memory using at least one field effect transistor, in which the molecules capable of storing the loads comprising a polyoxometallate are incorporated into the floating grid of the transistor.

Abstract: Dielectric layers containing a lanthanum hafnium oxide layer, where the lanthanum hafnium oxide layer is arranged as a structure of one or more monolayers, provide an insulating layer in a variety of structures for use in a wide range of electronic devices.

Abstract: A DRAM structure on a silicon substrate has an active area, gate conductors, deep trench capacitors, and vertical transistors. The deep trench capacitors are formed at intersections of the active area and the gate conductors, and each deep trench capacitor is coupled electrically to the corresponding vertical transistor to form a memory cell. The transistor includes a gate, a source in a lateral side of the gate, and a drain in another lateral side of the gate The depth of the drain is different from the depth of the source.

Abstract: A storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode including a barrier layer interposed between a conductive plug and an oxidation resistant layer. A layer of titanium silicide is fabricated to lie between the conductive plug and the oxidation resistant layer. An insulative layer protects the sidewalls of the barrier layer during the deposition and anneal of a dielectric layer having a high dielectric constant.

Abstract: A process for fabricating a semiconductor device having deep trench structures includes forming a first portion of the trench in a semiconductor substrate and a second portion of the trench in a selectively-formed upper layer. After etching the substrate to form the first portion of the trench, a protective layer is deposited over the inner surface of the trench in the semiconductor substrate and the upper layer is selectively formed on a principal surface of the semiconductor substrate. During formation of the upper layer, a wall surface is formed in the upper layer that is continuous with the wall surface of the trench in the semiconductor substrate. By forming a second portion of the trench in the selectively-formed upper layer, a deep trench is produced having a high aspect ratio and well defined geometric characteristics.

Abstract: Methods are provided for reducing the aspect ratio of contacts to bit lines in fabricating an IC including logic and memory. The method includes the steps of forming a first group of device regions to be contacted by a first level of metal and a second group of memory bit lines to be contacted by a second level of metal, the first level separated from the second level by at least one layer of dielectric material. Conductive material is plated by electroless plating on the device regions and bit lines and first and second conductive plugs are formed overlying the conductive material. The first conductive plugs are contacted by the first level of metal and the second conductive plugs are contacted by the second level of metal. The thickness of the plated conductive material provides a self aligned process for reducing the aspect ratio of the conductive plugs.

Abstract: A method for forming a capacitor structure for a dynamic random access memory device. The method includes forming a device layer overlying a semiconductor substrate, e.g., silicon wafer. The method includes forming a first interlayer dielectric overlying the device layer and forming a via structure within the first interlayer dielectric layer. The method includes forming a first oxide layer overlying the first interlayer dielectric layer and forming a stop layer overlying the first oxide layer. The method includes forming a second oxide layer overlying the first stop layer and forming a trench region through a portion of the second oxide layer, through a portion of the stop layer, and a portion of the second oxide layer. A bottom electrode structure is formed to line the trench region. The bottom electrode structure includes an inner region. The bottom electrode structure is coupled to the via structure.

Abstract: A semiconductor device capacitor fabrication method that is capable of enabling the simultaneous use of an oxide capacitor and a PIP capacitor of a semiconductor device depending upon whether metal line terminals are used. The semiconductor device capacitor fabrication method can include forming an active region and a first gate electrode over a semiconductor substrate, partially depositing a silicon nitride layer, over which a capacitor will be formed, over the first gate electrode, forming a second gate electrode over the silicon nitride, sequentially forming a first insulation layer and a second insulation layer over the resultant structure and forming line terminals extending through the first insulating layer and the second insulating layer for a transistor and a capacitor.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming an insulating material layer. The method includes forming an interface layer, removing a portion of the interface layer, annealing the interface layer, and forming a dielectric material over the interface layer.

Abstract: A semiconductor device includes a capacitor which has: a lower electrode formed along an opening provided above a semiconductor substrate to have a concave cross section; a capacitor insulating film formed on the inner and top surfaces of the lower electrode; and an upper electrode formed on the capacitor insulating film. The upper electrode includes: a first conductive film formed on the inner surface of the capacitor insulating film and filling the opening; and a second conductive film formed to extend from the top surface of the first conductive film to the top surface of the capacitor insulating film.

Abstract: An electrical circuit comprising a first metal oxide silicon (MOS) n type field effect transistor (NFET) or p type field effect transistor (PFET) and a second MOS NFET or PFET of the same conductivity type as the first NFET or PFET, wherein the drain of the first NFET or PFET is directly connected to the source of the second NFET or PFET, and wherein the gate of the second NFET or PFET is at a voltage value which is equal to or lower than the drain voltage value of the second NFET or PFET in the case of an NFET and equal to or higher than the drain voltage value of the second NFET or PFET in the case of a PFET.

Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device, for example, a semiconductor device using carbon nanotubes or nanowires as lower electrodes of a capacitor, and a method of manufacturing the semiconductor device. The semiconductor device may include a lower electrode including a plurality of tubes or wires on a semiconductor substrate, a dielectric layer on the surface of the lower electrode, and an upper electrode on the surface of the dielectric layer, wherein the plurality of tubes or wires radiate outwardly from each other centering on the lower portion of the plurality of tubes or wires. Thus, the off current of the capacitor may be increased by increasing the surface area of the lower electrodes of the capacitor.

Abstract: Methods of etching into silicon oxide-containing material with an etching ambient having at least 75 volume percent helium. The etching ambient may also include carbon monoxide, O2 and one or more fluorocarbons. The openings formed in the silicon oxide-containing material may be utilized for fabrication of container capacitors, and such capacitors may be incorporated into DRAM.

Abstract: A method for fabricating DRAM cells, e.g., dynamic random access memory cells. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method includes forming a plurality of NMOS transistor gate structures. Each of the NMOS gate structures includes an NMOS source region and an NMOS drain region and a plurality of PMOS gate structures. Each of the PMOS gate structures includes a PMOS source region and a PMOS drain region. The NMOS gate structures are formed on P-type well regions and the PMOS gate structures are formed on N-type well regions. An interlayer dielectric layer is overlying each of the gate structures while filling a gap between two or more of the NMOS gate structures.

Abstract: In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation layer and a gate electrode are formed on a sidewall of the MTJ structure. A word line is connected with the MTJ structure, and a bit line is connected with one of top and bottom surfaces of the MTJ structure. A capacitor is connected with one of top and bottom surfaces of the MTJ structure that is not connected with the bit line. Current leakage in the DRAM device is reduced and a unit cells may be vertically stacked on the substrate, so a smaller surface area of the substrate is required for the DRAM device.

Abstract: The present invention includes devices and methods to form memory cell devices including a spacer comprising a programmable resistive material alloy. Particular aspects of the present invention are described in the claims, specification and drawings.

Abstract: The invention includes methods of forming semiconductor constructions in which a single etch is utilized to penetrate through a titanium-containing layer and partially into a silicon-containing layer beneath the titanium-containing layer. The etch can utilize CH2F2. The silicon-containing layer can contain an n-type doped region and a p-type doped region. In some methods, the silicon-containing layer can contain an n-type doped region laterally adjacent a p-type doped region, and the processing can be utilized to form a transistor gate containing n-type doped silicon simultaneously with the formation of a transistor gate containing p-type doped silicon.

Abstract: A semiconductor device may include a MOS transistor having source and drain regions in a semiconductor substrate, a first inter-layer insulator having first contact holes that reach the source and drain regions over the MOS transistor. Cell contact plugs in the first contact holes contact with the source and drain regions. A second inter-layer insulator over the first inter-layer insulator and the cell contact plugs has second contact holes that reach the cell contact plugs. Contact plugs each have first and second portions. The first portion is in the second contact hole. The second portion extends over the first second inter-layer insulator. Metal barrier layers cover the upper surfaces of the second portions of the contact plugs. Capacitors each have a bottom electrode layer, a capacitive insulating layer and a top electrode layer. The bottom electrode layers each have a contact portion that contacts with the metal barrier layer.

Abstract: A method for fabricating an electron device on a substrate includes the steps of forming a dummy film over the substrate such that the dummy film covers a device region of the substrate and an outer region of the substrate outside the device region, forming a dummy pattern by patterning the dummy film such that the dummy patter has a first height in the device region and a second height smaller than the first height in the outer region, forming another film over the substrate such that the film covers the dummy pattern in the device region and in the outer region with a shape conformal to a cross-sectional shape of the dummy pattern, and applying an anisotropic etching process acting generally perpendicularly to the substrate such that a surface of the substrate is exposed in the device region and in the outer region.

Abstract: A semiconductor device includes a silicon substrate having an active region, a memory transistor having a pair of source/drain regions and a gate electrode layer, a hard mask layer on the gate electrode layer having a plane pattern shape identical with that of the gate electrode layer, and plug conductive layers each electrically connected to each of the pair of source/drain regions. An extending direction of the active region is not perpendicular to that of the gate electrode layer, but is oblique. Upper surfaces of the hard mask layer and each of the plug conductive layers form substantially an identical plane. This can attain a semiconductor device allowing significant enlargement of a margin in a photolithographic process, suppression of an “aperture defect” as well as ensuring of a process tolerance of a “short” by decreasing a microloading effect, and decrease in a contact resistance, and a manufacturing method thereof.

Abstract: A trench device and method for fabricating same are provided. The trench device has a collar with a first portion that is doped and a second portion that is undoped. Fabrication of the partially doped collar can be done by deposition of a doped insulator in the trench, removal of a portion of the doped deposition, deposition of an undoped insulator in the trench and removal of a portion of the doped and undoped insulators.

Abstract: The invention includes methods of incorporating partial SOI into transistor structures. In particular aspects, dielectric material is provided over semiconductor material, and patterned into at least two segments separated by a gap. Additional semiconductor material is then grown over the dielectric material and within the gap. Subsequently, a transistor is formed to comprise source/drain regions within the additional semiconductor material, and to comprise a channel between the source/drain regions. At least one of the source/drain regions is primarily directly over a segment of the dielectric material, and the channel is not primarily directly over any segment of the dielectric material. The invention also includes constructions comprising partial SOI corresponding to segments of dielectric material, and transistors having at least one source/drain region primarily directly over a segment of dielectric material, and a channel that is not primarily directly over any segment of the dielectric material.

Abstract: A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device.

Abstract: A semiconductor device may include a semiconductor substrate and first and second transistors. The first transistor may have a first gate structure on the semiconductor substrate, and the first gate structure may include a first gate insulating layer between a first gate electrode and the semiconductor substrate. The first gate insulating layer may include first and second dielectric materials with the second dielectric material having a greater dielectric constant than the first dielectric material. Moreover, the first gate electrode may be in contact with the second dielectric material. The second transistor may have a second gate structure on the semiconductor substrate, with the second gate structure including a second gate insulating layer between a second gate electrode and the semiconductor substrate. Related methods are also discussed.

Abstract: A memory device comprises an array of memory cells, the memory cells being at least partially formed in a semiconductor substrate having a surface, each of the memory cells including an access transistor and a storage capacitor for storing data, the storage capacitor including a first and a second capacitor electrodes and a capacitor dielectric disposed between the first and second capacitor electrodes. The first capacitor electrode extends to a first electrode height. The memory device also includes a peripheral portion including peripheral circuitry and a wiring layer. The wiring layer includes first lines, wherein a bottom surface of each of the first lines is disposed at a bottom surface height which is greater than 0.25 times the first electrode height, and each of the first lines has a line thickness less than 200 nm.

Abstract: A method of forming a vertical DRAM device. A lower trench is filled with polycrystalline or amorphous semiconductor for a capacitor. An upper trench portion has exposed sidewalls of single-crystal semiconductor. The method then includes etching the single-crystal semiconductor sidewalls to widen the of the upper trench portion beyond the exposed upper surface of the semiconductor fill of the capacitor to form exposed regions of single-crystal semiconductor on a bottom portion of the upper trench adjacent to the exposed upper surface of the semiconductor fill. A trench top insulating layer is deposited on the bottom portion of the upper trench, over the upper surface of the semiconductor fill and over the adjacent regions of single-crystal semiconductor. The method then includes forming a vertical gate dielectric layer, wherein the trench top insulating layer extends below the vertical gate insulating layer.

Abstract: A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/drain electrode in the semiconductor substrate, and a gate electrode, which is arranged along the channel layer and is electrically insulated from the channel layer, a storage capacitor, which has a first capacitor electrode and a second capacitor electrode, insulated from the first capacitor electrode, one of the capacitor electrodes of the storage capacitor being electrically conductively connected to one of the source/drain electrodes of the selection transistor, and a semiconductor substrate electrode on the rear side, the gate electrode enclosing the channel layer at at least two opposite sides.

Abstract: In a semiconductor device and a method of fabricating the same, a vertical channel transistor has a cell occupation area of 4F2.

Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.

Abstract: A single transistor floating-body dynamic random access memory (DRAM) device includes a floating body located on a semiconductor substrate and a gate electrode located on the floating body, the floating body including an excess carrier storage region. The DRAM device further includes source and drain regions respectively located at both sides of the gate electrode, and leakage shielding patterns located between the floating body and the source and drain regions. Each of the source and drain regions contact the floating body, which may be positioned between the source and drain regions. The floating body may also laterally extend under the leakage shielding patterns, which may be arranged at outer sides of the gate electrode.

Abstract: A method for use during fabrication of a semiconductor device comprises the formation of buried digit lines and contacts. During formation, a buried bit line layer may be used as a mask to etch one or more openings in a dielectric layer. A conductive layer is then formed in the one or more openings in the dielectric layer, and is then planarized to form one or more individual contact plugs. Next, the buried bit line layer is etched to recess the buried bit line layer, and a capacitor plate is formed to contact the contact plug.

Abstract: An electronic device may include a substrate, a conductive layer on the substrate, and an insulating spacer. The conductive electrode may have an electrode wall extending away from the substrate. The insulating spacer may be provided on the electrode wall with portions of the electrode wall being free of the insulating spacer between the substrate and the insulating spacer, and portions of the electrode most distant from the substrate may be free of the insulating spacer. Related methods and structures are also discussed.

Abstract: A field effect transistor includes a buried gate pattern that is electrically isolated by being surrounded by a tunneling insulating film. The field effect transistor also includes a channel region that is floated by source and drain regions, a gate insulating film, and the tunneling insulating film. The buried gate pattern and the tunneling insulating film extend into the source and drain regions. Thus, the field effect transistor efficiently stores charge carriers in the buried gate pattern and the floating channel region.

Abstract: The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a first region and at least one gate stack in a second region; forming a sacrificial plug made of a first material surrounded by an isolation layer between two adjacent gate stacks in the first region; depositing a planarisation layer over said plurality of gate stacks in said first region and said at least one gate stack in said second region; backpolishing said planarisation layer such that the upper surface of said sacrificial plug is exposed; forming a structured hardmask layer made of said first material on said backpolished planarisation layer which structured hardmask layer adjoins said sacrificial plug and has at least one opening in said second region; forming at least one contact hole in said second region under said at least one opening in said second region, said at least one contact hole exposing a substra

Abstract: The invention provides a method for fabricating a memory device having memory cells which are formed on a microstructured driving unit (100), in which method a shaping layer (104) is provided and is patterned in such a manner that vertical trench structures (105) are formed perpendicular to the surface of the driving unit (100). Deposition of a seed layer (106) on side walls (105a) of the trench structures (105) allows a crystallization agent (107) which has filled the trench structures (105), during crystallization, to have grain boundaries perpendicular to electrode surfaces that are to be formed. This provides memory cells based on vertical ferroelectric capacitors in a chain FeRAM structure.

Abstract: A semiconductor memory device with a dual storage node structure as well as methods of fabricating and operating such a device are provided. The semiconductor memory device includes a substrate, a first transistor formed on the substrate, a first storage node connected to a source region of the first transistor, a second storage node connected to a drain region of the first transistor, and a plate line commonly contacting the first storage node and the second storage node.

Abstract: A method of manufacturing a memory device that improves electrical characteristics of an MIM capacitor using a zirconium oxide film (ZrO2) as a dielectric film includes: forming a lower metal electrode on a semiconductor substrate; forming a two or more-layered dielectric film including zirconium oxide films on the lower metal electrode; forming an upper metal electrode on the dielectric film; forming an MIM capacitor by patterning the upper metal electrode, the dielectric film, and the lower metal electrode; forming an interlayer insulating film covering the MIM capacitor; forming contacts in the insulating film; and performing heat treatment at a temperature range of 425 to 500° C.

Abstract: An embedded semiconductor device which a logic region and the memory region are planarized with planarization resistance patterns and a method of manufacturing the same are disclosed.

Abstract: A semiconductor device manufacturing method including forming a dummy capacitor in a fuse region to avoid a step height between plate electrodes in a cell region and in a fuse region, is disclosed herein. The method can be used so that only an insulating film at a target thickness may remain on an upper part of the plate electrode in the fuse region during an etching process for forming a fuse open region, and a fuse failure due to laser blowing can be prevented.

Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.

Abstract: Phase change memories may exhibit improved properties and lower cost in some cases by forming the phase change material layers in a planar configuration. A heater may be provided below the phase change material layers to appropriately heat the material to induce the phase changes. The heater may be coupled to an appropriate conductor.