Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.

Abstract: A method is used for forming an SrTiO3 film on a substrate placed and heated inside a process chamber while supplying a gaseous Ti source material, a gaseous Sr source material, and a gaseous oxidizing agent into the process chamber. Sr(C5(CH3)5)2 is used as the Sr source material. The method performs a plurality of cycles to form the SrTiO3 film. Each cycle sequentially includes supplying the gaseous Ti source material into the process chamber and thereby adsorbing it onto the substrate; supplying the gaseous oxidizing agent into the process chamber and thereby decomposing the Ti source material thus adsorbed and forming a Ti-containing oxide film; supplying the gaseous Sr source material into the process chamber and thereby adsorbing it onto the Ti-containing oxide film; and supplying the gaseous oxidizing agent into the process chamber and thereby decomposing the Sr source material thus adsorbed and forming an Sr-containing oxide film.

Abstract: A channel stop region is formed immediately under an STI, and thereafter, an ion implantation is performed with conditions in which an impurity is doped into an upper layer portion of an active region, and at the same time, the impurity is also doped into immediately under another STI, and a channel dose region is formed at the upper layer portion of the active region, and another channel stop region is formed immediately under the STI.

Abstract: A semiconductor device is composed of: an interconnect made of a first conductive film and a second conductive film that are stacked in sequence from the interconnect underside on an insulating film formed on a substrate; and a capacitor composed of a lower capacitor electrode made of the first conductive film, a dielectric film formed on the lower capacitor electrode, and an upper capacitor electrode made of the second conductive film and formed on the dielectric film.

Abstract: The present invention provides a dielectric film having a high permittivity and a high heat resistance. An embodiment of the present invention is a dielectric film (103) including a composite oxynitride containing an element A made of Hf, an element B made of Al or Si, and N and O, wherein mole fractions of the element A, the element B, and N expressed as B/(A+B+N) range from 0.015 to 0.095 and N/(A+B+N) equals or exceeds 0.045, and has a crystalline structure.

Abstract: A capacitor structure includes a plurality of lower electrodes on a substrate, the lower electrodes having planar top surfaces and being arranged in a first direction to define a lower electrode column, a plurality of lower electrode columns being arranged in a second direction perpendicular to the first direction to define a lower electrode matrix, a plurality of supports on upper sidewalls of at least two adjacent lower electrodes, a dielectric layer on the lower electrodes and the supports, and an upper electrode on the dielectric layer.

Abstract: In a method of manufacturing a semiconductor device, a recess is formed in an active region of a substrate. A gate insulation layer is formed in the first recess. A barrier layer is formed on the gate insulation layer. A preliminary nucleation layer having a first resistance is formed on the barrier layer. The preliminary nucleation layer is converted into a nucleation layer having a second resistance substantially smaller than the first resistance. A conductive layer is formed on the nucleation layer. The conductive layer, the nucleation layer, the barrier layer and the gate insulation layer are partially etched to form a buried gate structure including a gate insulation layer pattern, a barrier layer pattern, a nucleation layer pattern and a conductive layer pattern.

Abstract: According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor device including: sequentially forming a first insulating film, a first electrode film, a second insulating film, and a second electrode film on a substrate; forming a groove that separates the second electrode film, the second insulating film and the first electrode film; forming an insulating film inside the groove so that an upper surface thereof is positioned between upper surfaces of the second electrode film and the second insulating film; forming an overhung portion on the second electrode film so as to overhang on the insulating film by performing a selective growth process; and forming a low resistance layer at the overhung portion and the second electrode film by performing an alloying process.

Abstract: The present invention relates to a trench silicon-on-insulator (SOI) dynamic random access memory (DRAM) cell and a method for making the same. A source and a drain are utilized to each connect to one of two semiconductor conductive units on an external side of a main body having a plurality of semiconductor conductive units, and the semiconductor conductive units are utilized to accumulate electric charges generated from the drain so as to decrease a threshold voltage. In addition, the DRAM cell only uses one field effect transistor (FET) device (1T), has characteristics of the conventional 1T-DRAM, and has higher integration density. Moreover, the process of the invention is simple, so the production cost can be reduced.

Abstract: A method for manufacturing a ferroelectric memory device includes the steps of: forming a ferroelectric capacitor on a substrate; forming a hydrogen barrier film that covers the ferroelectric capacitor; forming a dielectric film that covers the hydrogen barrier film; and forming a through hole that penetrates the dielectric film and the hydrogen barrier film by etching that uses a mixed gas containing perfluorocarbon gas and oxygen gas, wherein the flow quantity of the perfluorocarbon gas is 0.77 times or more but 3.8 times or less the flow quantity of the oxygen gas.

Abstract: A method for forming a capacitor in a dynamic random access memory, comprising steps of: providing a semiconductor substrate having at least a transistor, whereon an interlayer dielectric layer having at least a first plug is formed so that the first plug is connected to the drain of the transistor; depositing an etching stop layer on the first plug and the interlayer dielectric layer; depositing a first insulating layer on the etching stop layer; forming at least a second plug on the first insulating layer and the etching stop layer so that the second plug is connected to the first plug; depositing a second insulating layer on the first insulating layer and the second plug; forming at least a mold cavity in the second insulating layer so that the aperture of the mold cavity is larger than the diameter of the second plug and there is a deviation between the mold cavity and the second plug; removing the first insulating layer in the mold cavity until the etching stop layer; depositing a first electrode layer t

Abstract: A method for manufacturing a semiconductor device comprises forming a first layer on an impurity diffusion region in a semiconductor substrate by a selective epitaxial growth method, forming a second layer on the first layer by the selective epitaxial growth method, forming a contact hole penetrating an interlayer insulating film in a thickness direction thereof and reaching the second layer, and filling a conductive material into the contact hole to form a contact plug including the first and second layers and the conductive material.

Abstract: In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation layer and a gate electrode are formed on a sidewall of the MTJ structure. A word line is connected with the MTJ structure, and a bit line is connected with one of top and bottom surfaces of the MTJ structure. A capacitor is connected with one of top and bottom surfaces of the MTJ structure that is not connected with the bit line. Current leakage in the DRAM device is reduced and a unit cells may be vertically stacked on the substrate, so a smaller surface area of the substrate is required for the DRAM device.

Abstract: A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.

Abstract: A wafer-cutting process includes first cutting a semiconductive wafer along a first path at a given first cutting intensity including cutting across an intersection. The process also includes second cutting the semiconductive wafer along a second path at a given second cutting intensity. The second cutting intensity is diminished during crossing the intersection and resumed to the given cutting intensity after crossing the intersection.

Abstract: A dynamic random access memory structure is disclosed, in which, the active area is a donut-type pillar at which a novel vertical transistor is disposed and has a gate filled in the central cavity of the pillar and upper and lower sources/drains located in the upper and the lower portions of the pillar respectively. A buried bit line is formed in the substrate beneath the transistor. A word line is horizontally disposed above the gate. A capacitor is disposed above the word line as well as the gate and electrically connected to the upper source/drain through a node contact. The node contact has a reverse-trench shape with the top surface electrically connected to the capacitor and with the bottom of the sidewalls electrically connected to the upper source/drain. The word line passes through the space confined by the reverse-trench shape.

Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.

Abstract: A semiconductor device includes a ferroelectric capacitor formed above the lower interlevel insulating film covering a MOS transistor formed on a semiconductor substrate, including lamination of a lower electrode, an oxide ferroelectric film, a first upper electrode made of conductive oxide having a stoichiometric composition AOx1 and an actual composition AOx2, a second upper electrode made of conductive oxide having a stoichiometric composition BOy1 and an actual composition BOy2, where y2/y1>x2/x1, and a third upper electrode having a composition containing metal of the platinum group; and a multilayer wiring structure formed above the lower ferroelectric capacitor, and including interlevel insulating films and wirings. Abnormal growth and oxygen vacancies can be prevented which may occur when the upper electrode of the ferroelectric capacitor is made of a conductive oxide film having a low oxidation degree and a conductive oxide film having a high oxidation degree.

Abstract: A semiconductor device with a dielectric structure and a method for fabricating the same are provided. A capacitor in the semiconductor device includes: a bottom electrode formed on a substrate; a first dielectric layer made of titanium dioxide (TiO2) in rutile phase and formed on the bottom electrode; and an upper electrode formed on the first dielectric layer.

Abstract: A DRAM array having trench capacitor cells of potentially 4F2 surface area (F being the photolithographic minimum feature width), and a process for fabricating such an array. The array has a cross-point cell layout in which a memory cell is located at the intersection of each bit line and each word line. Each cell in the array has a vertical device such as a transistor, with the source, drain, and channel regions of the transistor being formed from epitaxially grown single crystal silicon. The vertical transistor is formed above the trench capacitor.

Abstract: Provided is a semiconductor integrated circuit device including a capacitor element with an improved TDDB life. A semiconductor integrated circuit device (1) includes: a first electrode (4) including a first semiconductor layer which protrudes with respect to a plane of a substrate; a side surface insulating film (5) formed on at least a part of a side surface of the first electrode (4); an upper surface insulating film (6) formed on the first electrode (4) and the side surface insulating film (5); and a second electrode (7) which covers the side surface insulating film (5) and the upper surface insulating film (6). The first electrode (4), the side surface insulating film (5), and the second electrode (7) constitute a capacitor element. A thickness of the upper surface insulating film (6) between the first electrode (4) and the second electrode (7) is larger than a thickness of the side surface insulating film (5) between the first electrode (4) and the second electrode (7).

Abstract: A deep trench structure process for forming a deep trench in a silicon on insulator (SOI) substrate. The SOI substrate has a bulk silicon layer, a buried oxide (BOX) layer and an SOI layer. In the process, the trench fill is recessed only to a level within the SOI layer so as to avoid lateral etching of the BOX layer. The buried strap is then formed followed by the STI oxide.

Abstract: A method of forming a silicon-on-insulator (SOI) semiconductor structure in a substrate having a bulk semiconductor layer, a buried oxide (BOX) layer and an SOI layer. During the formation of a trench in the structure, the BOX layer is undercut. The method includes forming a dielectric material on the upper wall of the trench adjacent to the undercutting of the BOX layer and then etching the dielectric material to form a spacer. The spacer fixes the BOX layer undercut and protects it during subsequent steps of forming a bottle-shaped portion of the trench, forming a buried plate in the deep trench; and then forming a trench capacitor. There is also a semiconductor structure, preferably an SOI eDRAM structure, having a spacer which fixes the undercutting in the BOX layer.

Abstract: The present invention provides a semiconductor storage device having a memory cell section and a peripheral circuit section each formed using one or more MOS transistors, comprising: a substrate; a dielectric film on the substrate; and a planar semiconductor layer formed on the on-substrate dielectric layer, wherein: the at least one MOS transistor in the memory cell section comprises a selection transistor, the at least one MOS transistor in the peripheral circuit section comprises a first MOS transistor and a second MOS transistor which are different in conductivity type from each other, the first MOS transistor includes a first lower drain or source region formed in the planar semiconductor layer, a first pillar-shaped semiconductor layer formed on the planar semiconductor layer, a first upper source or drain region formed in an upper portion of the first pillar-shaped semiconductor layer, and a first gate electrode formed such that the first gate electrode surrounds a sidewall of the first pillar-shaped s

Abstract: A semiconductor device includes a semiconductor substrate; a memory cell array including a plurality of memory cells formed on the semiconductor substrate and arranged in a matrix in a first direction and a second direction on the surface of the semiconductor substrate; a plurality of sense amplifiers formed on the semiconductor substrate and including a first sense amplifier and a second sense amplifier; and a plurality of bit lines extending along the first direction above the memory cell array, and arranged side by side in the second direction, wherein the plurality of bit lines include a first bit line pair formed in a first wiring layer and a second bit line pair formed in a second wiring layer located above the first wiring layer.

Abstract: A method of manufacturing a dynamic random access memory cell includes: forming a substrate having an insulating region over a conductive region; forming a fin of a fin-type field effect transistor (FinFET) device over the insulating region; forming a storage capacitor at a first end of the fin; and forming a back-gate at a lateral side of the fin. The back-gate is in electrical contact with the conductive region and is structured and arranged to influence a threshold voltage of the fin.

Abstract: A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming the through substrate via by filling an opening with a first fill material and depositing a first insulating layer over the first fill material, the first insulating layer not being deposited on sidewalls of the fill material in the opening, wherein sidewalls of the first insulating layer form a gap over the opening. The method further includes forming a void by sealing the opening using a second insulating layer.

Abstract: A semiconductor memory device includes diffusion regions formed in an active region; cell contacts connected to the diffusion regions, respectively; pillars connected to the cell contacts, respectively; a bit line connected to the pillar; capacitor contacts connected to the pillars, respectively; and storage capacitors connected to the capacitor contacts, respectively. Accordingly, the pillars exist between the cell contacts and the capacitor contacts, and thus, depths of the capacitor contacts are made correspondingly shorter. Therefore, it becomes possible to prevent occurrence of shorting defects while decreasing resistance values of the capacitor contacts.

Abstract: Methods of forming semiconductor devices that include one or more container capacitors include anchoring an end of a conductive member to a surrounding lattice material using an anchor material, which may be a dielectric. The anchor material may extend over at least a portion of an end surface of the conductive member, at least a portion of the lattice material, and an interface between the conductive member and the lattice material. In some embodiments, the anchor material may be formed without significantly covering an inner sidewall surface of the conductive member. Furthermore, in some embodiments, a barrier material may be provided over at least a portion of the anchor material and over at least a portion of an inner sidewall surface of the conductive member. Novel semiconductor devices and structures are fabricated using such methods.

Abstract: A method for forming a semiconductor device of the present invention solves problems in a process for forming a fin type gate including a recess region, such as, a complicated process, low production margin, and difficulty in forming an accurate fin shape. In a process for forming an isolation dielectric film defining an active region, a nitride film pattern is formed in such a manner that the size of the nitride film is adjusted according to line width of a fin portion in a fin type active region formed in a subsequent process step, and an isolation dielectric film is formed in every region except for the nitride film pattern of a semiconductor substrate. Then, a recess is etched, and the isolation dielectric film is removed from a region where the line width of the nitride film pattern was reduced to a certain degree.

Abstract: A semiconductor device includes an interlayer insulating film having an opening, an adhesion layer formed on at least a side wall of the opening, a lower electrode formed on a bottom surface of the opening and at least a side surface of the adhesion layer, a capacitor insulating film made of a ferroelectric formed on the lower electrode, and an upper electrode formed on the capacitor insulating film. The lower electrode, the capacitor insulating film and the upper electrode constitute a capacitor, and the capacitor has a cross-section having a recessed shape in the opening. The lower electrode has a protruding portion protruding from the opening. The capacitor insulating film is formed, covering at least the protruding portion of the lower electrode, of the lower electrode and the adhesion layer. The upper electrode is formed, covering the capacitor insulating film formed on the protruding portion.

Abstract: A manufacturing method of a semiconductor device disclosed herein, comprises: forming a first member to be patterned on a semiconductor substrate; forming a second member to be patterned on the first member; forming a third member to be patterned on the second member; patterning the third member to form a first line pattern and a first connecting portion in the third member, the first line pattern having a plurality of parallel linear patterns and the first connecting portion connecting the linear patterns on at least one end side of the linear patterns of the first line pattern; etching the second member with the third member as a mask to form a second line pattern and a second connecting portion in the second member, the second line pattern being the same pattern as the first line pattern and the second connecting portion being the same pattern as the first connecting portion; removing the second connecting portion of the second member; and etching the first member with the second member as a mask.

Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.

Abstract: A method for fabricating a semiconductor device includes forming buried bit lines separated from each other by a trench in a substrate, forming a plurality of first pillar holes that expose a top surface of the substrate, forming first active pillars buried in the first pillar holes, forming a gate conductive layer over entire surface of a resultant structure including the first active pillars, forming a gate electrode by etching the gate conducting layer to cover the first active pillars, forming a plurality of second pillar holes that expose the first active pillars by partially etching the gate electrode, and forming second active pillars buried in the second pillar holes and connected to the first active pillars.

Abstract: A semiconductor memory device includes a switching transistor provided on a semiconductor substrate; an interlayer dielectric film on the switching transistor; a contact plug in the interlayer dielectric film; a ferroelectric capacitor above the contact plug and the interlayer dielectric film, the ferroelectric capacitor comprising a lower electrode, a ferroelectric film and an upper electrode; a diffusion layer in the semiconductor substrate, the diffusion layer electrically connecting the contact plug to the switching transistor; a hydrogen barrier film on a side surface of the ferroelectric capacitor; and an interconnection comprising a TiN film or a TiAlxNy film entirely covering up an upper surface of the upper electrode and contacting with the upper surface of the upper electrode.

Abstract: A semiconductor memory device includes a semiconductor layer; a source layer and a drain layer in the semiconductor layer; an electrically floating body region in the semiconductor layer between the source layer and the drain layer, accumulating or discharging charges for storing logical data; a gate dielectric film on the body region; and a first gate electrode and a second gate electrode on one body region via the gate dielectric film, the first and the second gate electrodes separated from each other in a channel length direction of a memory cell comprising the drain layer, the source layer, and the body region.

Abstract: An embedded memory cell includes a semiconducting substrate (110), a transistor (120) having a source/drain region (121) at least partially embedded in the semiconducting substrate, and a capacitor (130) at least partially embedded in the semiconducting substrate. The capacitor includes a first electrode (131) and a second electrode (132) that are electrically isolated from each other by a first electrically insulating material (133). The first electrode is electrically connected to the semiconducting substrate and the second electrode is electrically connected to the source/drain region of the transistor.

Abstract: A first MOS transistor includes, as a first impurity region, a pair of first source/drain regions including first portions formed in a semiconductor substrate and second portions formed so as to project upward from the first portions. A second MOS transistor includes a pair of second source/drain regions including second impurity regions formed in the semiconductor substrate, third impurity regions located in contact with the second impurity regions so as to project upward from the semiconductor substrate, and fourth impurity regions located on the third impurity regions. The concentration of impurities in the third impurity regions is lower than that of impurities in the fourth impurity regions. The concentration of impurities in the first impurity regions is lower than that of impurities in the second impurity regions. The first, the second, the third and the fourth impurity regions are same conductivity type.

Abstract: An integrated circuit includes a semiconducting substrate (110), electrically conductive layers (120) over the semiconducting substrate, and a capacitor (130) at least partially embedded within the semiconducting substrate such that the capacitor is entirely underneath the electrically conductive layers. A storage node voltage is on an outside layer (132) of the capacitor. In the same or another embodiment, the integrated circuit may act as a 1T-1C embedded memory cell including the semiconducting substrate, an electrically insulating stack (160) over the semiconducting substrate, a transistor (140) including a source/drain region (142) within the semiconducting substrate and a gate region (141) above the semiconducting substrate, a trench (111) extending through the electrically insulating layers and into the semiconducting substrate, a first electrically insulating layer (131) located within the trench, and the capacitor located within the trench interior to the first electrically insulating layer.

Abstract: A method of fabricating an integrated circuit device storage cell may include forming a channel region comprising a semiconductor material doped to a first conductivity type; forming a store gate structure comprising a semiconductor material doped to a second conductivity type in contact with the channel region; and forming a control gate terminal from at least a portion of a semiconductor layer deposited on a substrate surface in contact with the channel region, the portion of the semiconductor layer being doped to the second conductivity type.

Abstract: A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.

Abstract: In a semiconductor device according to embodiments of the invention, a capacitor includes a storage electrode having a cylindrical storage conductive layer pattern and connecting members formed on the upper portion of the cylindrical storage conductive layer pattern. The connecting member connects to an adjacent connecting member of another storage electrode. A dielectric layer and a plate electrode are successively formed on the storage electrode. All of the capacitors are connected by one another by forming cylindrical storage electrodes so that the storage electrode does not fall down when the capacitors have an extremely large aspect ratio. Thus, the capacitance of the capacitors may be improved to the desired level. A semiconductor device that includes these capacitors may have improved reliability and the throughput of a semiconductor manufacturing process may be increased.

Abstract: A method of manufacturing a semiconductor device having a first memory cell array region and a second memory cell array region, the method includes forming an active region on a surface layer of a semiconductor substrate, forming a first word line extending in a first direction on the gate insulating film in the first memory cell array region, and forming a second word line extending in a second direction crossing the first direction on the gate insulating film in the second memory cell array region, wherein the ion implantation into the active region is performed from a direction that is inclined from a direction vertical to the surface of the semiconductor substrate and is oblique with respect to both the first direction and the second direction.

Abstract: A method of fabricating a dynamic random access memory is provided. First, a substrate at least having a memory device area and a peripheral device area is provided, wherein an isolation structure and a capacitor are formed in the substrate of the memory device area, and an isolation structure and a well are formed in the substrate of the peripheral device area. A first oxide layer is formed on the substrate of the peripheral device area, and a passing gate isolation structure is formed on the substrate of the memory device area at the same time. A second oxide layer is formed on the substrate of the memory device area. And a first transistor is formed on the substrate of the memory device area, a passing gate is formed on the passing gate isolation structure, and a second transistor is formed on the substrate of the peripheral device area.

Abstract: A capacitor structure comprises a first and a second electrode of conducting material. Between the first and second electrodes, an atomic layer deposited dielectric film is disposed, which comprises zirconium oxide and a dopant oxide. Herein, the dopant comprises an ionic radius that differs by more than 24 pm from an ionic radius of zirconium, while the dielectric film comprises a dopant content of 10 atomic percent or less of the dielectric film material excluding oxygen. A process for fabricating a capacitor comprises a step of forming a bottom electrode of the capacitor. On the bottom electrode, a dielectric film comprising zirconium oxide is deposited, and a step for introducing a dopant oxide into the dielectric film performed. On the dielectric structure, a top electrode is formed.

Abstract: A flash memory device where the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected amount so as to achieve a desirable coupling between the substrate, the floating gate and the control gate incorporating the flash cell.

Abstract: A semiconductor device includes a semiconductor substrate that includes first and second regions; first, second, and third insulating layers; a capacitor dielectric layer that includes first and second dielectric layers; a gate insulating layer formed on the first and second regions; a gate formed on the gate insulating layer of the second region; a first capacitor electrode formed on the capacitor dielectric layer; and impurity regions formed in the semiconductor substrate on sides of the gate. The first and second regions include first and second trenches, respectively. The third insulating layer is formed on the second insulating layer, which is formed on the first insulating layer, which is formed on an inner surface of the second trench. The second dielectric layer is formed on the first dielectric layer, which is formed on an inner surface of the first trench.

Abstract: A semiconductor memory device has a semiconductor substrate, an impurity diffusion layer that is formed at a surface portion of the semiconductor substrate, an interlayer insulating film that is formed on the semiconductor substrate, a contact plug that penetrates the interlayer insulating film, has a top surface formed higher than a top surface of the interlayer insulating film, a region having a convex shape formed higher than the top surface of the interlayer insulating film, and contacts the impurity diffusion layer, a lower capacitor electrode film that is formed on the contact plug and a predetermined region of the interlayer insulating film, a ferroelectric film that is formed on the lower capacitor electrode film, and an upper capacitor electrode film that is formed on the ferroelectric film.

Abstract: A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in a way so that film deposition occurs from the bottom of the trench upwards, with step coverage well in excess of 100%. In a second fill step, deposition conditions are changed to reduce the impact of dopant on deposition rate, and deposition proceeds at a rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.

Abstract: Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact selected ones of the active regions. Bit line structures are formed on the first interlayer dielectric layer and crossing the word lines that are coupled to the selected ones of the active regions by the direct contact plugs. A second interlayer dielectric layer is formed on the semiconductor substrate including the bit line structures. Barrier patterns are formed extending in parallel with bit line structures and into the second interlayer dielectric layer. Mask patterns are formed overlying an entirety of top surfaces of the direct contact plugs on the second interlayer dielectric layer and the bit line structures.