Abstract: A junction field effect transistor (JFET) can include a top gate structure and an active semiconductor region. The active semiconductor region can include a side surface and a top surface formed below the top gate structure. The active semiconductor region can also include a channel region formed below the top gate structure, a bottom gate region formed below the channel region, and a gate tie region formed on the side surface that makes an electrical connection between the top gate structure and the bottom gate region.

Abstract: Disclosed is a method of manufacturing a semiconductor device. The method includes forming an oxide-nitride-oxide (ONO) layer over a semiconductor substrate, and forming a recess over the semiconductor substrate by etching the ONO layer, forming a vertical structure pattern being higher than the ONO layer over the recess, sequentially forming a spacer oxide film and a first gate poly over the side wall of the vertical structure pattern, and forming a nitride film spacer at a partial region of the side wall of the first gate poly, removing the nitride film spacer, and forming a second gate poly in a spacer shape over the side wall of the first gate poly, and forming a first split gate and a second split gate, symmetrically divided from each other, by removing the vertical structure pattern.

Abstract: A semiconductor device is provided with a conductor wire and a fuse wire formed in an insulating film over a semiconductor substrate, a first under-pad-wire insulating film formed above the insulating film, a second under-pad-wire insulating film formed on the first under-pad-wire insulating film, a pad wire formed in an area above the conductive wire, in the first and second under-pad-wire insulating films and an opening formed by leaving a part of the first under-pad-wire insulating film in an area above the fuse wire, in the first and second under-pad-wire insulating films, wherein the second under-pad-wire insulating film comprises an element different from that of the first under-pad-wire insulating film.

Abstract: A method of fabricating a semiconductor device forms a micro-sized gate, and mitigates short channel effects. The method includes a pull-back process to form the gate on a substrate. The method also includes forming inner and outer spacers on the gate that are asymmetric to one another with respect to the gate, and using the spacers in forming junction regions in the substrate on opposite sides of the gate. In particular, the inner and outer spacers are formed on opposite sides of the gate so as to have different thicknesses at the bottom of the gate. The inner and outer junction regions are formed by doping the substrate before and after the spacers are formed. Thus, the inner and outer junction regions have extension regions under the inner and outer spacers, respectively, and the extension regions have different lengths.

Abstract: A conductive strap spacer is formed within a buried strap cavity above an inner electrode recessed below a top surface of a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A portion of the conductive strap spacer is metallized by reacting with a metal to form a strap metal semiconductor alloy region, which is contiguous over the conductive strap spacer and a source region, and may extend to a top surface of the buried insulator layer along a substantially vertical sidewall of the conductive strap spacer. The conductive strap spacer and the strap metal semiconductor alloy region provide a stable electrical connection between the inner electrode of the deep trench capacitor and the source region of the access transistor.

Abstract: A method of forming a field effect transistor includes forming trench isolation material within a semiconductor substrate and on opposing sides of a semiconductor material channel region along a length of the channel region. The trench isolation material is formed to comprise opposing insulative projections extending toward one another partially under the channel region along the channel length and with semiconductor material being received over the projections. The trench isolation material is etched to expose opposing sides of the semiconductor material along the channel length. The exposed opposing sides of the semiconductor material are etched along the channel length to form a channel fin projecting upwardly relative to the projections. A gate is formed over a top and opposing sides of the fin along the channel length. Other methods and structures are disclosed.

Abstract: A semiconductor device and a method for fabricating a semiconductor device are provided. The method for fabricating a semiconductor device includes forming an isolation layer over a semiconductor substrate defining first and second regions, etching the isolation layer at an edge of the first region to form a guard ring pattern, forming a buried guard ring filling the guard ring pattern, selectively etching the isolation layer of the first region to form a plurality of patterns, forming a plurality of conductive patterns in the respective patterns, and completely removing the isolation layer of the first region through a dip-out process.

Abstract: An apparatus having low resistance contacts in both the memory cell array and peripheral logic circuitry areas of a semiconductor device, for example, a DRAM memory device, is disclosed. In a buried bit line connection process flow, the present invention utilizes chemical vapor deposition of titanium to form titanium silicide in contact structures of the peripheral logic circuitry areas and physical vapor deposition to provide a metal mode (metallic) titanium layer in contact with the poly plugs in the memory cell array area of a semiconductor device, for example, a DRAM memory device according to the present invention. In this manner, the present invention avoids the potential drawbacks such as voiding in the poly plugs of the memory cell array due to the present of titanium silicide, which can cause significant reduction of device drain current and in extreme cases cause electrical discontinuity.

Abstract: A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are defined by a first pitch, with one word line located between each drain and the source. Digit lines are defined by a second pitch, one of the digit lines being coupled to the source and forming a second axis. The active areas of the memory array are tilted at 45° to the grid defined by the word lines and digit lines. The word line pitch is about 1.5F, while the digit line pitch is about 3F.

Abstract: The following discloses and describes a zero capacitor RAM as well as a method for manufacturing the same. The zero capacitor RAM includes an SOI substrate. This SOI substrate is composed of a stacked structure of a silicon substrate, an embedded insulation film and a silicon layer. This layer is patterned into line types to constitute active patterns. Moreover, a first insulation layer forms between the active patterns and gates form on the active patterns as well as the first insulation layer to extend perpendicularly to the active patterns. In addition, a source forms in the active pattern on one side of each gate, a drain forms in the active pattern on the other side of each gate which is achieved by filling a metal layer. Continuing, a contact plug forms between the gates on the source and an interlayer dielectric forms on the contact plug in addition to the gates Finally, a bit line forms on the interlayer dielectric to extend perpendicularly to the gates and come into contact with the drain.

Abstract: A semiconductor device includes a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a Ti/TiN layer as a top conductive layer thus constituting a single polysilicon layer metal-insulator-polysilicon (MIP) structure. While the high sheet rho resistor is also formed on the same single polysilicon layer with differential doping of the polysilicon layer.

Abstract: A transistor structure includes a semiconductor substrate having a top surface and sidewalls extending downward from the top surface, wherein each of the sidewall comprises a vertical upper sidewall surface and a lower sidewall recess laterally etched into the semiconductor substrate. A trench fill dielectric region is inlaid into the top surface of the semiconductor substrate. Two source/drain regions are formed into the top surface of the semiconductor substrate and are sandwiched about the trench fill region. A buried gate electrode is embedded in the lower sidewall recess. A gate dielectric layer is formed on surface of the lower sidewall recess between the semiconductor substrate and the buried gate electrode.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes forming a portion of the unidirectional transistor and a portion of a bidirectional transistor in or over a semiconductor material simultaneously. Other embodiments are described and claimed.

Abstract: A semiconductor device with reduced resistance of a buried bit line, and a method for fabricating the same. The method for fabricating a semiconductor device includes etching a semiconductor substrate to form a plurality of active regions which are separated from one another by trenches formed in between, forming a side contact on a sidewall of each active region, and forming metal bit lines, each filling a portion of a respective trench and connected to the side contact.

Abstract: Dielectric layers containing a dielectric layer including lanthanum and hafnium and methods of fabricating such dielectric layers provide an insulating layer in a variety of structures for use in a wide range of electronic devices.

Abstract: It is disclosed a semiconductor device including a silicon substrate, provided with a plurality of cell active regions in a call region, an element isolation groove, formed in a portion, between any two of the plurality of cell active region, of the silicon substrate, a capacitor dielectric film, formed in the element isolation groove, a capacitor upper electrode, formed on the capacitor dielectric film, and configuring a capacitor together with the silicon substrate and the capacitor dielectric film. The semiconductor device is characterized in that a dummy active region is provided next to the cell region in the silicon substrate.

Abstract: A memory includes a U-shape layer on a substrate; a first diffusion layer provided at an upper part of the U-shaped layer; a second diffusion layer provided at a lower part of the U-shaped layer; a body formed at an intermediate portion of the U-shaped layer between the first and the second diffusion layers; a first gate dielectric film provided on an outer side surface of the U-shaped layer; a first gate electrode provided on the first gate dielectric film; a second gate dielectric film provided on an inner side surface of the U-shaped layer; a second gate electrode provided on the second gate dielectric film; a bit line contact connecting the bit line to the first diffusion layer; a source line contact connecting the source line to the second diffusion layer, wherein cells adjacent in the first direction alternately share the bit line contact and the source line contact.

Abstract: In one aspect of the present invention, a programmable element, may include a semiconductor substrate, source/drain layers formed apart from each other in the upper surface of the semiconductor substrate, a gate insulating film including a charge-trapping film containing Hf and formed on a portion between the source/drain layers of the semiconductor substrate, and a gate electrode formed on the gate insulating film with a program voltage applied to the gate electrode.

Abstract: A semiconductor device having a DRAM region and a logic region embedded together therein, including a first transistor formed in a DRAM region, and having a first source/drain region containing arsenic and phosphorus as impurities; and a second transistor formed in a logic region, and having a second source/drain region containing at least arsenic as an impurity, wherein each of the first source/drain region and the second source/drain region has a silicide layer respectively formed in the surficial portion thereof, and the first source/drain region has a junction depth which is determined by phosphorus and is deeper than the junction depth of the second source/drain region.

Abstract: Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon growth. The method includes providing a silicon layer on a substrate. A dielectric layer is provided on the silicon layer. A trench is formed in the dielectric layer to expose the silicon layer, the trench having trench walls in the <100> direction. The method includes epitaxially growing silicon between trench walls formed in the dielectric layer.

Abstract: A method for forming a memory cell transistor is disclosed which includes providing a substrate, forming a trench structure in the substrate, depositing a conductive substance on the surface of the substrate to form a conductive member inside the trench structure, forming one or more dielectric layers on the surface of the substrate, forming one or more first conductive layers on top of the dielectric layers, and etching the first conductive layers and the dielectric layers to form a hole structure extending through the first conductive and the dielectric layers, reaching to the substrate surface. The formed memory cell transistor thus comprises a hole structure which is formed from the surface of the top first conductive layer, extending downwards through the first conductive layers and the dielectric layers, and reaching the substrate surface. One or more second conductive layers may be formed on top of the first conductive layers, with the second conductive layer material filling the hole structure.

Abstract: A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures.

Abstract: A dynamic random access memory cell including a bottom oxide layer, a first semiconductor layer, a second semiconductor layer, an insulation layer, a gate and a doping layer is provided. The bottom oxide layer is disposed on a substrate. The first semiconductor layer disposed on the bottom oxide layer has a first doping concentration. The second semiconductor layer disposed on the first semiconductor layer has a second doping concentration lower than the first doping concentration. The insulation layer disposed on the bottom oxide layer at least situates at the two sides of the first semiconductor layer. The height of the insulation layer is greater than that of the first semiconductor layer. The gate is disposed on the second semiconductor layer. The doping layer disposed correspondingly to the two sides of the gate substantially contacts the second semiconductor layer and the insulation layer.

Abstract: The invention relates to a semiconductor device and a method of fabricating the same, wherein a storage node contact hole is made large to solve any problem caused during etching a storage node contact hole with a small CD, a landing plug is formed to lower plug resistance, and the SAC process is eliminated at the time of the bit line formation. A method of fabricating a semiconductor device according to the invention comprises: forming a device isolation film for defining a multiplicity of active regions in a semiconductor substrate; forming a multiplicity of buried word lines in the semiconductor substrate; forming a storage node contact hole for exposing a storage node contact region of two adjoining active regions; filling the storage node contact hole with a storage node contact plug material; forming a bit-line groove for exposing a bit-line contact region of the active region and splitting the storage node contact plug material into two; and burying the bit line into the bit-line groove.

Abstract: A method for forming a semiconductor device is provided. The method comprises providing a semiconductor structure comprising a semiconductor substrate and a dielectric layer on the semiconductor substrate, wherein the dielectric layer has an opening through which the semiconductor substrate is exposed; forming a semiconductor strip on the dielectric layer and adjacent the opening, wherein the semiconductor strip is electrically isolated from the semiconductor substrate; forming a gate dielectric over a portion of the semiconductor strip that is over the dielectric layer; forming a gate electrode over the gate dielectric; and forming a source/drain region in the semiconductor strip.

Abstract: A method for manufacturing a capacitor of a semiconductor device includes: forming an interlayer insulating film including a contact plug over a semiconductor substrate; forming a first stack film including a capacitor oxide film and a nitride film over the interlayer insulating film; etching the first stack film to form a first stack pattern and a contact hole that exposes the contact plug; forming a lower electrode in the contact hole; forming a capping oxide film continuously over the first stack pattern to form a bridge connecting the neighboring first stack patterns; forming an etching barrier film including cavities over the capping oxide film; performing a blanket etching process onto the etching barrier film including cavities until the capacitor oxide film is exposed to form a nitride film pattern; and removing the exposed capacitor oxide film.

Abstract: Some embodiments include memory cells that contain floating bodies and diodes. The diodes may be gated diodes having sections doped to a same conductivity type as the floating bodies, and such sections of the gated diodes may be electrically connected to the floating bodies. The floating bodies may be adjacent channel regions, and spaced from the channel regions by a dielectric structure. The dielectric structure of a memory cell may have a first portion between the floating body and the diode, and may have a second portion between the floating body and the channel region. The first portion may be more leaky to charge carriers than the second portion. The diodes may be formed in semiconductor material that is different from a semiconductor material that the channel regions are in. The floating bodies may have bulbous lower regions. Some embodiments include methods of making memory cells.

Abstract: The present invention provides a dielectric film having a high permittivity and a high heat resistance. An embodiment of the present invention is a dielectric film (103) including a composite oxynitride containing an element A made of Hf, an element B made of Al or Si, and N and O, wherein mole fractions of the element A, the element B, and N expressed as B/(A+B+N) range from 0.015 to 0.095 and N/(A+B+N) equals or exceeds 0.045, and has a crystalline structure.

Abstract: A method of manufacturing a semiconductor device may include forming a first interlayer insulation layer on a substrate including at least one gate structure formed thereon, the substrate having a plurality of source/drain regions formed on both sides of the at least one gate structure, forming at least one buried contact plug on at least one of the plurality of source/drain regions and in the first interlayer insulation layer, forming a second interlayer insulation layer on the first interlayer insulation layer and the at least one buried contact plug, exposing the at least one buried contact plug in the second interlayer insulation layer by forming at least one contact hole, implanting ions in the at least one contact hole in order to create an amorphous upper portion of the at least one buried contact plug, depositing a lower electrode layer on the second interlayer insulation layer and the at least one contact hole, and forming a metal silicide layer in the amorphous upper portion of the at least one buri

Abstract: A semiconductor manufacturing method includes forming a word line crossing with an active region on a semiconductor substrate; forming a diffusion layer region; forming a first insulating film as high as a bit line to be formed; etching the first insulating film, while using, as a mask, a pattern having a linear aperture extending to the active region on the first insulating film so as to form a groove pattern for exposing the surface of the semiconductor substrate; embedding a conductive film in the groove pattern; forming a mask pattern passing over a portion, in which a bit contact is formed, on the first insulating film; and removing the first insulating film and the conductive layer until the upper layer insulating film of the word line is exposed, while using the mask pattern as a mask so as to isolate a bit contact from another contact.

Abstract: A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.

Abstract: The present invention relates to a memory cell with a memory capacitor (110) on an active semiconductor region (104), the memory capacitor having a first capacitor-electrode layer, which, in a cross-sectional view of the memory cell, has first (218.1) and second (218.2) electrode-layer sections that extend on the active semiconductor region in parallel to the surface of the active semiconductor region at a vertical distance to each other and that are electrically connected by a third electrode-layer section extending vertically, that is, perpendicular to the surface of the active semiconductor region. A control transistor (112) is connected with a conductive second capacitor electrode layer that extends between the first and second electrode-layer sections and is electrically isolated from them by an isolation layer (116). Achieved advantages comprise a high manufacturing yield can, reduced fabrication cost and reduced risk of junction leakage by a small area required for the memory cell.

Abstract: In one embodiment, a semiconductor device has a topmost or highest conductive layer with at least one opening. The semiconductor device includes a semiconductor substrate having a cell array region and an interlayer insulating layer covering the substrate having the cell array region. The topmost conductive layer is disposed on the interlayer insulating layer in the cell array region. The topmost conductive layer has at least one opening. A method of fabricating the semiconductor device is also provided. The openings penetrating the topmost metal layer help hydrogen atoms reach the interfaces of gate insulating layers of cell MOS transistors and/or peripheral MOS transistors during a metal alloy process, thereby improve a performance (production yield and/or refresh characteristics) of a memory device.

Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device including: a semiconductor substrate; memory cell transistors that are series-connected; and a select transistor that includes: a first diffusion region that is formed in the semiconductor substrate at one end of the memory cell transistors; a first insulating film that is formed on the semiconductor substrate at a side of the first diffusion region; a select gate electrode that is formed on the first insulating film; a semiconductor pillar that is formed to extend upward from the semiconductor substrate and to be separated from the select gate electrode; a second insulating film that is formed between the select gate electrode and the semiconductor pillar; and a second diffusion region that is formed on the semiconductor pillar.

Abstract: A device manufacturing method includes forming a first insulation film on a semiconductor substrate. A first mask is formed on the first insulation film to extend in a first direction and have a linear pattern. The first insulation film is etched using the first mask as mask to process the insulation film into a linear body. A second mask is formed on the linear body to extend in a second direction different from the first direction and have a linear pattern. The linear body is etched using the second mask as mask to process the linear body into a pillar element. A first conductive film is formed to cover the pillar body. The first conductive film is etched to form a first electrode of the first conductive film on side surfaces of the pillar body.

Abstract: A DRAM array having trench capacitor cells of potentially 4F2 surface area (F being the photolithographic minimum feature width), and a process for fabricating such an array. The array has a cross-point cell layout in which a memory cell is located at the intersection of each bit line and each word line. Each cell in the array has a vertical device such as a transistor, with the source, drain, and channel regions of the transistor being formed from epitaxially grown single crystal silicon. The vertical transistor is formed above the trench capacitor.

Abstract: In a phase change memory, electric property of a diode used as a selection device is extremely important. However, since crystal grain boundaries are present in the film of a diode using polysilicon, it involves a problem that the off leak property varies greatly making it difficult to prevent erroneous reading. For overcoming the problem, the present invention provides a method of controlling the temperature profile of an amorphous silicon in the laser annealing for crystallizing and activating the amorphous silicon thereby controlling the crystal grain boundaries. According to the invention, variation in the electric property of the diode can be decreased and the yield of the phase-change memory can be improved.

Abstract: A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate.

Abstract: The method of manufacturing a semiconductor device includes a first conductor over a semiconductor substrate; forming a first insulator over the first conductor; forming a second insulator, having an etching characteristic different from an etching characteristic of the first insulator, over the first insulator; forming a second conductor on the second insulator, the second conductor being in contact with the second insulator; forming a third insulator, having an etching characteristic different from the etching characteristic of the second insulator, over the second conductor; forming a first contact hole though the third insulator and the second conductor, the first contact hole exposing the second insulator; forming a second contact hole through the third insulator and the first insulator, the second contact hole exposing the first conductor; forming a third conductor in the first contact hole, wherein a side wall of the third conductor is electrically connected to a side wall of the second conductor; form

Abstract: A semiconductor device includes a substrate, a gate insulation layer, a gate structure, a gate spacer, and first and second impurity regions. The substrate has an active region defined by an isolation layer. The active region has a gate trench thereon. The gate insulation layer is formed on an inner wall of the gate trench. The gate structure is formed on the gate insulation layer to fill the gate trench. The gate structure has a width smaller than that of the gate trench, and has a recess at a first portion thereof. The gate spacer is formed on sidewalls of the gate structure. The first and second impurity regions are formed at upper portions of the active region adjacent to the gate structure. The first impurity region is closer to the recess than the second impurity region. Related methods are also provided.

Abstract: The invention relates to a DRAM memory device with a capacity associated with a field effect transistor, in which all or some of the molecules capable of storing the loads comprising a polyoxometallate are incorporated into the capacity, or a flash-type memory using at least one field effect transistor, in which the molecules capable of storing the loads comprising a polyoxometallate are incorporated into the floating grid of the transistor. The invention also relates to a method for producing on such device and to an electronic appliance comprising one such memory device.

Abstract: A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer.

Abstract: An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at least two opposite sides.

Abstract: In a conventional semiconductor device, an excessive etching occurs in a section where an opening for contact plug is formed, causing a damage to a diffusion layer located under the opening. A semiconductor device 1 includes a region D1 for forming an electric circuit, and a seal ring 30 (guard ring) that surrounds the region D1 for forming the electric circuit. A DRAM 40 is formed in the region D1 for forming the electric circuit. Interlayer insulating films 22, 24, 26 and 28 are formed on a semiconductor substrate 10. The seal ring 30 is formed in the interlayer insulating films 22, 24, 26 and 28, and at least a portion there of is located spaced apart from the semiconductor substrate 10.

Abstract: A method for fabricating a semiconductor device includes forming a pattern including a first layer including tungsten, performing a gas flowing process on the pattern in a gas ambience including nitrogen, and forming a second layer over the pattern using a source gas including nitrogen, wherein the purge is performed at a given temperature for a given period of time in a manner that a reaction between the first layer and the nitrogen used when forming the second layer is controlled.

Abstract: A semiconductor memory device and a method for manufacturing the same are disclosed, which reduce parasitic capacitance generated between a storage node contact and a bit line of a high-integration semiconductor device. A method for manufacturing a semiconductor memory device includes forming a buried word line in an active region of a cell region, forming an insulation layer in the cell region and a lower electrode layer of a gate in a peripheral region so that a height of the insulation layer is substantially equal to that of the lower electrode layer, and providing a first conductive layer over the cell region and the peripheral region to form a bit line layer and an upper electrode layer.

Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory including: a columnar semiconductor; a charge storage insulating film including: a first insulating film formed around the columnar semiconductor, a charge storage film formed around the first insulating film, and a second insulating film formed around the charge storage film; an electrode extending two-dimensionally to surround the charge storage insulating film, the electrode having a groove; and a metal silicide formed on a sidewall of the groove.

Abstract: In a method for manufacturing a nonvolatile memory device, an etch mask layer formed on a dielectric layer to define contact holes in the dielectric layer is slope-etched to form an etch mask pattern having an opening wider at the upper end thereof than the lower end thereof. Thus, the contact holes are defined in the dielectric layer to have a finer size than the upper end of the opening of the etch mask pattern. The method for manufacturing a nonvolatile memory device includes forming an etch mask pattern on a dielectric layer such that a width of a lower end of each opening defined in the etch mask pattern is less than a width of an upper end thereof; and defining contact holes by removing portions of the dielectric layer using the etch mask pattern.

Abstract: A method for use during fabrication of a semiconductor device comprises the formation of buried digit lines and contacts. During formation, a buried bit line layer may be used as a mask to etch one or more openings in a dielectric layer. A conductive layer is then formed in the one or more openings in the dielectric layer, and is then planarized to form one or more individual contact plugs. Next, the buried bit line layer is etched to recess the buried bit line layer, and a capacitor plate is formed to contact the contact plug.

Abstract: A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.