Abstract: Provided is a package structure includes a die having a first connector, a RDL structure disposed on the die, and a second connector. The RDL structure includes at least one elongated via located on and connected to the first connector. The second connector is disposed on and connected to the RDL structure.

Abstract: An electronic device includes: a semiconductor body; a front metallization region; a top buffer region, arranged between the front metallization region and the semiconductor body; and a conductive wire, electrically connected to the front metallization region. The top buffer region is at least partially sintered.

Abstract: A filament type light emitting bulb including a base, a light transmitting globe coupled to a front opening of the base, a pair of leads, and a plurality of light emitting devices, said one of the light emitting devices includes a non-conductive substrate; a first light emitting diode chip, a second light emitting diode chip and nth, where n?1, light emitting diode chip mounted on the upper surface of the non-conductive substrate and each comprising input and output ends; two connection means including a first connection mean adjacent to the first light emitting diode chip connected an input terminal and a second connection mean adjacent to the nth light emitting diode chip connected an output terminal; two extending terminals connected the first connection mean and the second connection mean respectively; and a light transmitting encapsulant covered the non-conductive substrate, the two connection means and partially covered the two extending terminals, wherein the nth light emitting diode chip formed a firs

Abstract: In a general aspect, a method for producing a packaged semiconductor device can include coupling a semiconductor device to a leadframe structure having a signal lead that is electrically coupled with the semiconductor device. The method can also include encapsulating at least a portion of the semiconductor device and at least a portion of the leadframe structure in a molding compound. At least a segment of the signal lead can be exposed outside the molding compound. A surface of the molding compound can define a primary plane of the packaged semiconductor device. The method can further include forming, with a laser, a groove in the segment, applying solder plating to the segment, including the groove, and separating, at the groove, the segment into a first portion and a second portion, such that the second portion of the segment is separated from the leadframe structure.

Abstract: A semiconductor device includes a first to a third wiring-line. The first wiring-line is provided on a first layer in a first direction. The second wiring-line is provided on the first layer in the first direction. A first side surface of the second wiring-line faces the first wiring-line. A second side surface of the second wiring-line is opposite to the first side surface. The third wiring-line is provided on the first layer in the first direction, and faces the second side surface of the second wiring-line. An end portion of the first wiring-line projects further from an end portion of the second wiring-line in the first direction. The end portion of the second wiring-line projects further from an end portion of the third wiring-line in the first direction, and curves toward the third wiring-line. Alternatively, the end portion of the second wiring-line increases in width toward its edge portion.

Abstract: A power conversion apparatus mounted in a vehicle includes a semiconductor stack in which a plurality of semiconductor modules and a plurality of coolants including coolant passages are disposed by being alternately stacked, and a retaining unit which presses the semiconductor stack in a stacking direction to retain the semiconductor stack. The semiconductor modules and the coolants are attached to each other by a plate-shaped insulating resin adhesive member, and a roughened area on which a roughening treatment has been performed is formed in at least a part of the outer surface of the coolants to which the resin adhesive member is attached.

Abstract: A semiconductor package includes a first semiconductor chip on a first substrate, a first mold layer provided on the first substrate to cover a side surface of the first semiconductor chip, a solder structure provided on the first substrate, and a second substrate provided on the solder structure. A guide receptacle is formed at one of a top surface of the first mold layer and a bottom surface of the second substrate, a first alignment protrusion is formed at the other of the top surface of the first mold layer and the bottom surface of the second substrate, and at least a portion of the first alignment protrusion is provided in the guide receptacle.

Abstract: A method of manufacturing a wafer level fan-out package includes preparing a base substrate having a protrusion, providing a chip on a surface of the base substrate adjacent to and spaced from the protrusion, forming an encapsulation layer on the base substrate to encapsulate the chip and the protrusion, removing the base substrate to expose a surface of the chip and to form a recess corresponding to the protrusion in the encapsulation layer, and providing a passive element in the recession. The method obviates a problem of displacement of the passive element by thermal expansion of the encapsulation layer while it is being formed because the passive element is incorporated into the package after the encapsulation layer is formed.

Abstract: A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.

Abstract: The disclosure relates to a dual-interface integrated circuit (IC) card module for use in a dual-interface IC card. Embodiments disclosed include a dual-interface integrated circuit card module (150), the module comprising: a substrate (104) having first and second opposing surfaces; a contact pad (102) on the first surface of the substrate; an integrated circuit (110) on the second surface of the substrate (104), the integrated circuit (110) having electrical connections to the contact pad (102) through the substrate (104); and a pair of antenna pads (108) disposed in recesses (103) in the second surface of the substrate (104) and electrically connected to corresponding antenna connections on the integrated circuit (110).

Abstract: Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a stack of semiconductor dies and a thermally conductive casing at least partially enclosing the stack of semiconductor dies within an enclosure. A package substrate carries the thermally conductive casing, and an interposer is disposed between the thermally conductive casing and the stack of semiconductor dies. A peripheral portion of the interposer extends laterally beyond the stack of semiconductor dies and is coupled to a plurality of conductive members interposed between the peripheral portion and the package substrate.

Abstract: A method of producing an optoelectronic component includes providing a carrier including a top side; creating at the top side of the carrier a region that is recessed with respect to a mounting region of the top side to form a step between the mounting region and the recessed region; arranging at the top side of the carrier a metallization extending over the mounting region and the recessed region; creating a separating track in the metallization, wherein the metallization is completely severed at least in sections in the mounting region and is at least not completely severed in the recessed region; and arranging an optoelectronic semiconductor chip above the mounting region of the top side, wherein the optoelectronic semiconductor chip is aligned at the separating track.

Abstract: A driver assembly comprises a predetermined number of semiconductor switches, wherein one of the semiconductor switches is arranged inside of a circular curve and the remaining semiconductor switches are arranged on the circular curve.

Abstract: A semiconductor package structure includes a substrate, at least one first semiconductor element, a heat dissipation structure and an insulation layer. The at least one first semiconductor element is attached to the substrate, and has a first surface and a second surface opposite to the first surface. The first surface of the at least one first semiconductor element faces the substrate. The heat dissipation structure is disposed on the second surface of the at least one first semiconductor element. The insulation layer is disposed on the heat dissipation structure, and defines a plurality of openings extending through the insulation layer and exposing a plurality of exposed portions of the heat dissipation structure.

Abstract: An electronic device includes a first wiring substrate and a semiconductor device mounted on the first wiring substrate. A plurality of first semiconductor chips and a second semiconductor chip which controls each of the plurality of first semiconductor chips are mounted side by side on a second wiring substrate of the semiconductor device. Further, the plurality of first semiconductor chips are mounted between a first substrate side of the wiring substrate and an extension line of a first chip side of the second semiconductor chip. Furthermore, the first wiring substrate includes a first power line which supplies a first power potential to each of the plurality of first semiconductor chips and a second power line which supplies a second power potential to the second semiconductor chip and has a width larger than that of the first power line.

Abstract: A hearing aid comprising a microphone, a receiver, hearing aid electronics coupled to the microphone and the receiver, and conductive traces overlaying an insulator, the conductive traces configured to interconnect the hearing aid electronics and to follow non-planar contours of the insulator. Examples are provided wherein the insulator includes a hearing aid housing.

Abstract: A semiconductor package includes a first semiconductor chip including a first through-silicon via (TSV), a second semiconductor chip stacked on the first semiconductor chip and including a second TSV, and a non-conductive film formed between the first semiconductor chip and the second semiconductor chip. The non-conductive film includes two layers having different viscosities.

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The semiconductor structure includes a substrate; a pad disposed over the substrate; a first passivation disposed over the substrate, partially covering the pad, and including a protrusion protruded from the first passivation and away from the substrate; a conductive layer disposed over the first passivation and a portion of the pad exposed from the first passivation; and a second passivation disposed over the conductive layer, wherein the conductive layer disposed over the protrusion is exposed from the second passivation.

Abstract: A semiconductor device is provided with a semiconductor element, a main lead on which the semiconductor element is disposed, and a resin package that covers the semiconductor element and the main lead. A notch that is recessed toward the center of the main lead in plan view as seen in the thickness direction of the semiconductor element is formed in the main lead.

Abstract: A circuit board includes a substrate, a first dielectric layer, an adhesive layer, a second dielectric layer, and a first conductive line. The first dielectric layer is disposed on the substrate. The adhesive layer is bonded to the first dielectric layer and has a top surface opposite to the substrate. The second dielectric layer is disposed on the adhesive layer and has at least one first through hole. The first conductive line is located in the first through hole of the second dielectric layer and is in contact with the top surface of the adhesive layer.

Abstract: An electrical package may comprise a first substrate with a first substrate surface, and a microprocessor chip connected to the first substrate surface. The microprocessor chip may comprise a first chip surface that electrically connects to the first substrate surface, and a second chip surface located opposite the first chip surface. The electrical package may comprise a heat spreader assembly that comprises a lid section and a contact surface thermally connected to the second-chip surface. The electrical package may also comprise a pedestal between the contact surface and the lid section. The pedestal may comprise a first end that is located near the contact surface and a second end that is located near the lid section. The second end may be wider than the first end.

Abstract: An optoelectronic semiconductor component includes a semiconductor chip having a semiconductor layer sequence including an active region that generates radiation; a radiation exit surface running parallel to the active region; a mounting side surface that fixes the semiconductor component and runs obliquely or perpendicularly to the radiation exit surface and at which at least one contact area for external electrical contacting is accessible; a molded body molded onto the semiconductor chip in places and forming the mounting side surface at least in regions; and a contact track arranged on the molded body and electrically conductively connecting the semiconductor chip to the at least one contact area.

Abstract: A fan-out semiconductor package module includes: a structure including a wiring member including wiring patterns, one or more first passive components disposed on the wiring member and electrically connected to the wiring pattern, and a first encapsulant encapsulating at least portions of each of the one or more first passive components, and having a first through-hole penetrating through the wiring member and the first encapsulant; a semiconductor chip disposed in the first through-hole of the structure and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; a second encapsulant encapsulating at least portions of the semiconductor chip and filling at least portions of the first through-hole; and a connection member disposed on the structure and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads and the wiring patterns.

Abstract: An electronic device includes an vibration element including an vibration body provided with an adjustment section, an electrode disposed on the vibration body, and a connection electrode electrically connected to the electrode, an IC so disposed that the IC faces the vibration element, terminals disposed on the side facing the upper surface of the IC and electrically connected to the connection electrode via a fixing member, wiring sections electrically connected to the terminals and located below the terminals, and a protective layer located above the wiring sections and disposed in a portion where the adjustment section overlaps with the wiring sections in a plan view.

Abstract: To realize a reduction in the number of parts in a system including a driver IC (semiconductor device). A high potential side power supply voltage is applied to a power supply application area. A high side area is formed with a circuit which includes a driver driving a high side transistor and is operated at a boot power supply voltage with a floating voltage as a reference. A low side area is formed with a circuit operated at a power supply voltage with a low potential side power supply voltage as a reference. A first termination area is disposed in a ring form so as to surround the power supply application area. A second termination area is disposed in a ring form so as to surround the high side area.

Abstract: It is an object to provide a technique where a snubber capacitor having an appropriate capacitance is usable. A power module includes: a third lead having one end electrically connected to a first connection point and the other end exposed from a package, where the third lead is shorter than a first lead; and a fourth lead having one end electrically connected to a second connection point and the other end exposed from the package, where the fourth lead is shorter than a second lead. A snubber capacitor is attachable to and detachable from the other ends of the third lead and fourth lead.

Abstract: Methods of fabricating electronic circuits and electronic packages are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board.

Abstract: Electronic circuits, electronic packages, and methods of fabrication are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board.

Abstract: An integrated circuit includes a plurality of vertically-stacked layers including a front end of line (FEOL) layer and a back end of line (BEOL) layer. The FEOL layer includes individual transistors that are not interconnected. The BEOL layer includes transistor interconnections and no transistors. The transistors are electrically connected to the transistor interconnections by vias within the FEOL ad BEOL layers. The FEOL and BEOL layers each have contact pads on the top and bottom surfaces thereof that are each in alignment with vias, are arranged in a checkerboard pattern, and occupy about fifty percent of the surface area of the FEOL and BEOL layers. The contact pads on a top surface of the FEOL layer are in electrical communication with contact pads on a bottom surface of the BEOL layer to facilitate vertical current flow between the transistors and the transistor interconnections through the vias.

Abstract: The present invention provides a bonding wire which can satisfy bonding reliability, spring performance, and chip damage performance required in high-density packaging. A bonding wire contains one or more of In, Ga, and Cd for a total of 0.05 to 5 at %, and a balance being made up of Ag and incidental impurities.

Abstract: The present disclosure relates to an apparatus comprising a substrate, wherein a MEMS module is arranged on a first side of the substrate, the output signal from said MEMS module changing in the event of a change in temperature. Furthermore, the apparatus has a housing structure which is arranged on a first side of the substrate and has a recess in which the MEMS module is arranged. The apparatus also has a layer which is applied to the housing structure and increases the heat capacity of the apparatus. The present disclosure also relates to a method for producing an apparatus of this kind.

Abstract: An apparatus in accordance with one example includes a battery module in a dual in-line memory module (DIMM) form factor. The battery module is insertable in a DIMM slot of a host device to provide backup power to a plurality of loads of the host device.

Abstract: A semiconductor device package includes a substrate, a package body, a via and an interconnect. The substrate includes a surface and a pad on the first surface. The package body covers at least a portion of the surface of the substrate. The via is disposed in the package body and includes a conductive layer and a first intermediate layer. The conductive layer is electrically connected with the pad. The first intermediate layer is adjacent to the conductive layer. The interconnect is disposed on the first intermediate layer.

Abstract: An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device further comprises a metal pillar over and electrically coupled to the metal pad, and a passive device comprising a first portion at a same level as the metal pillar, wherein the first portion of the passive device is formed of a same material as the metal pillar.

Abstract: A printed-wiring board has a land group with which a terminal group of a semiconductor package has been joined, a first conductor pattern arranged in a mounting area where the semiconductor package is mounted and joined with a heat radiation plate of the semiconductor package, a second conductor pattern, at least a part of which is arranged on the outside of the mounting area, and a third conductor pattern which connects the first and second conductor patterns. The land group includes a first land adjacent to the third conductor pattern and a second land which is not adjacent to the third conductor pattern, and the first land is formed in a shape different from that of the second land so as to be away from the third conductor pattern.

Abstract: A tactile sensor includes: a first sheet having at least either flexibility or elasticity; and a second sheet having at least either flexibility or elasticity and having a first surface facing the first sheet and a second surface opposite to the first surface. The second surface includes a plurality of protruding shapes. Each of the plurality of protruding shapes includes an enclosed space inside, the enclosed space being defined by the first surface of the second sheet and the first sheet. At least one first electrode pattern is disposed on the first sheet in the enclosed space of each of the plurality of protruding shapes. At least one second electrode pattern is disposed on the first surface in the enclosed space of each of the plurality of protruding shapes.

Abstract: A micro-concentrator module includes a cover glass provided with solar cells on one side thereof. The cover glass is adapted to hover above a substrate containing an array of MEMS based reflectors. Springs between the cover glass and the substrate displace the cover glass from a stowed position during transport to a deployed operational position above the substrate. Tethers connecting the cover glass with the substrate limit the displacement of the cover glass to a distance corresponding to the focal length of the reflectors.

Abstract: Disclosed is a method of manufacturing a flexible conductive track arrangement for a neurostimulation system such as a cochlear implant device. The method allows for the arrangement to be manufactured without the need for a transfer substrate by embedding the metal structures of the arrangement in a ceramic dielectric material formed in an atomic layer deposition process, which can be performed at a temperature that is compatible with the polymer processing steps of such an arrangement. A flexible conductive track arrangement and a neurostimulation system are also disclosed.

Abstract: A livestock pasture display tag of a type used under harsh agricultural conditions, the tag comprising: (i) a thin, substantially, flat planar flexible display having a thickness, a front planar surface and a back planar surface, both surfaces are substantially parallel to a longitudinal axis positioned between surfaces; at least one of said surfaces is having a display section in which the livestock animal indicia is displayed; (ii) an anchoring section for fixedly securing the improved livestock pasture display tag to a body part surface of the livestock animal; and (iii) a permanent pressure sensitive encapsulation zone.

Abstract: A fan-out semiconductor package includes a redistribution layer, an interconnection member, a semiconductor chip, and a protective layer. The interconnection member has a through hole disposed on the redistribution layer. The semiconductor chip is disposed on the redistribution layer exposed within the through hole. The protective layer is formed between the redistribution layer and the interconnection member, and coupled to the interconnection member to protect the interconnection member.

Abstract: An electronic apparatus and a circuit board thereof are provided. The electronic apparatus operates in cooperation with a packaged electronic component. The electronic apparatus includes a circuit board and a control device disposed on the circuit board. The circuit board includes a plurality of conductive vias passing therethrough, and the conductive vias includes a plurality of first conductive vias arranged respectively corresponding to the first contact pads of the packaged electronic component. The control device includes a signal contact array including a plurality of first signal contacts. When the packaged electronic component and the control device are respectively disposed on two opposite sides of the circuit board, the packaged electronic component and the control device at least partially overlap in a thickness direction of the circuit board, and the first signal contacts are respectively electrically connected to the first contact pads via the corresponding conductive vias.

Abstract: Embodiments of the disclosure provide a bearing substrate and a fabrication method for a flexible display device, which relate to the field of display technology and may achieve a uniform separation between a flexible substrate and bearing substrate, and not cause damage to the flexible substrate and the display element. The bearing substrate comprises a first sub-bearing substrate and a second sub-bearing substrate. The first sub-bearing substrate has a plurality of through holes, and the second sub-bearing substrate has a plurality of protrusions that are in one-to-one correspondence with the protrusions. The protrusions and the through holes are configured such that the protrusions are capable of passing through the through holes when assembling the first sub-bearing substrate with the second sub-bearing substrate, so that the protrusions are flush with a surface of the first sub-bearing substrate and spliced together with the surface.

Abstract: The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna, each of the five sections or segments forming a pair of angles with each adjacent segment or section, wherein the smaller angle of each of the four pairs of angles between sections or segments is less than 180° (i.e.

Abstract: The power circuit includes: a main substrate; a first electrode pattern disposed on the main substrate and connected to a positive-side power terminal P; a second electrode pattern disposed on a main substrate and connected to a negative-side power terminal N; a third electrode pattern disposed on the main substrate and connected to an output terminal O; a first MISFET Q1 of which a first drain is disposed on the first electrode pattern; a second MISFET Q4 of which a second drain is disposed on the third electrode pattern; a first control circuit (DG1) connected between a first gate G1 and a first source S1 of the first MISFET, and configured to control a current path conducted from the first source towards the first gate.

Abstract: An RFID tag device is disclosed that is designed to operate on difficult substrates, such as dielectric surfaces with high loss, organic material surfaces, or metallic surfaces. The RFID tag device comprises an RFID antenna structure formed on one side of a thermoplastic substrate component with an RFID chip coupled to it in a roll to roll process. The substrate component is then deformed into a series of cavities with the RFID antenna structure within the cavities. Specifically, the RFID antenna structure is positioned fully on a top surface of the cavity, or positioned partially in a top and partially on an edge/bottom of the cavity.

Abstract: A package includes a redistribution portion, a first portion, and a second portion. The first portion is coupled to the redistribution portion. The first portion includes a first switch comprising a plurality of switch interconnects, and a first encapsulation layer that at least partially encapsulates the first switch. The second portion is coupled to the first portion. The second portion includes a first plurality of filters. Each filter includes a plurality of filter interconnects. The second portion also includes a second encapsulation layer that at least partially encapsulates the first plurality of filters. The first portion includes a second switch positioned next to the first switch, where the first encapsulation layer at least partially encapsulates the second switch. The second portion includes a second plurality of filters positioned next to the first plurality of filters, where the secod encapsulation layer at least partially encapsulates the second plurality of filters.

Abstract: Apparatuses, systems and methods associated with hermetic encapsulation for package assemblies are disclosed herein. In embodiments, a package assembly may include a package substrate that includes a guard ring, wherein the guard ring extends from a surface of the package substrate and around a circumference of a cavity. The package assembly may further include a component coupled to the guard ring by a solder joint along an entirety of the guard ring, wherein the cavity is located between the package substrate and the component and the cavity is hermetically-sealed via the guard ring and the solder joint. Other embodiments may be described and/or claimed.

Abstract: An integrated circuit which enables lower cost and improved features compared to standard crystalline silicon integrated circuits by utilizing thin film transistors (TFTs) in 2D and 3D memory and logic devices, including NAND flash memory and other nonvolatile memories such as RRAM, NRAM, MRAM, FeRAM or PCRAM. By utilizing TFTs, density is improved and die area and costs are reduced. Volumetric memory arrays of several layers may be fabricated with greatly reduced area requirements for periphery circuits and routing. Under 5% area requirements are possible. Ultra-wide I/O may be implemented without die area penalty. Vertical TFTs and logic gates provide better density and high speed approaching or exceeding that of crystalline silicon.

Abstract: An apparatus is described. The apparatus includes a package on package structure. The package on package structure includes an upper package and a lower package. One of the packages contain memory devices of a first type and the other of the packages contain memory devices of a second type. I/O connections on the underside of the upper package's substrate are vertically aligned with their corresponding, first I/O connections on the underside of the lower package's substrate. The first I/O connections are located outside second I/O connections on the underside of the lower package's substrate for the lower package.

Abstract: Embodiments of the present invention provides an array substrate. The array substrate includes a display region and a packaging region. The packaging region includes a plurality of functional layers. And the packaging region further includes: a plurality of through holes running through at least one of the plurality of functional layers and configured to allow a packaging adhesive to enter therein; and a groove formed above at least some of the through holes, wherein, projection areas of the at least some of the through holes onto a base substrate of the array substrate are located within a projection area of the groove onto the base substrate. Embodiments of the present invention further provides a display panel and a display apparatus including the abovementioned array substrate, and a method of manufacturing the abovementioned array substrate.