Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a first semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a first encapsulant encapsulating at least portions of the first interconnection member and the first semiconductor chip; a second interconnection member disposed on the first interconnection member and the first semiconductor chip; a second semiconductor chip disposed on the first encapsulant and having an active surface having connection pads disposed thereon; and a second encapsulant encapsulating at least portions of the second semiconductor chip.

Abstract: A lead frame constitutes a product unit in a multi-row lead frame and has a dam bar and a lead connected together. The dam bar has a first site where connection is made with the lead and a second site adjoining the first site without connection with the lead. A predetermined range in the lead near a connecting portion with the dam bar and the second site in the dam bar have a plate thickness smaller than that of the first site having a same plate thickness as a metal plate as a material from which the dam bar and the lead are made.

Abstract: A semiconductor device includes a semiconductor die. An encapsulant is formed around the semiconductor die. A build-up interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A first supporting layer is formed over a second surface of the semiconductor die as a supporting substrate or silicon wafer disposed opposite the build-up interconnect structure. A second supporting layer is formed over the first supporting layer and includes a fiber enhanced polymer composite material comprising a footprint including an area greater than or equal to an area of a footprint of the semiconductor die. The semiconductor die comprises a thickness less than 450 micrometers (?m). The thickness of the semiconductor die is at least 1 ?m less than a difference between a total thickness of the semiconductor device and a thickness of the build-up interconnect structure and the second supporting layer.

Abstract: A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate. First and second encapsulants are deposited over the first semiconductor die and substrate. A first build-up interconnect structure is formed over the substrate after depositing the second encapsulant. The top package is disposed over the bottom package. The bottom package has a second semiconductor die and modular interconnect units disposed around the second semiconductor die. A second build-up interconnect structure is formed over the second semiconductor die and modular interconnect unit. The modular interconnect units include a plurality of conductive vias and a plurality of contact pads electrically connected to the conductive vias. The I/O pattern of the build-up interconnect structure on the top semiconductor package is designed to coincide with the I/O pattern of the modular interconnect units.

Abstract: Described is an apparatus which comprises: a backside of a first die having a redistribution layer (RDL); and one or more passive planar devices disposed on the backside, the one or more passive planar devices formed in the RDL.

Abstract: A three-dimensional semiconductor wafer relates to a semiconductor wafer, including a raw semiconductor wafer, at least one connection layer, a conduction layer and a protection layer, wherein the protection layer is arranged on the conduction layer; the connection layer is inserted into a bottom surface or/and a top surface of the raw semiconductor wafer; and the conduction layer is arranged on the bottom surface of the raw semiconductor wafer.

Abstract: A method for producing a display device includes locating a substrate, including a plurality of pixels, on a jig including a magnet; locating a plate formed of a magnetic material on the substrate to secure the substrate; and folding back an end portion of the substrate in a state where the substrate is held between the jig and the plate.

Abstract: A manufacturing method of a package structure having an embedded bonding film comprises the following steps: forming a bonding film, forming a redistribution substrate and forming a core on a bottom side of the redistribution substrate opposite to the top side. The bonding film comprises the following steps: forming a plurality of dielectric layers and metal circuit layers sequentially and alternatively in a plurality of bonding areas; exposing a plurality of top metal pads of a topmost metal circuit layer among the metal circuit layers in the plurality of bonding areas; and etching to form a bonding film. The bonding film has a left longitudinal branch and a lower latitudinal branch. A lower end of the left longitudinal branch is connected to a left end of the lower latitudinal branch. The left longitudinal branch and the lower latitudinal branch form an L shape.

Abstract: Package structures and methods of forming the same are disclosed. A package structure includes at least one first integrated circuit, at least one second integrated circuit, at least one dummy substrate and an encapsulant. The at least one second integrated circuit is disposed on the at least one dummy substrate in a first direction, and the at least one first integrated circuit and the at least one dummy substrate are separated by a distance in a second direction perpendicular to the first direction. The encapsulant is aside the at least one first integrated circuit, the at least one second integrated circuit and the at least one dummy substrate.

Abstract: A semiconductor device package includes an electronic device and a redistribution stack. The redistribution stack includes a dielectric layer disposed over an active surface of the electronic device and defining an opening exposing at least a portion of a contact pad of the electronic device. The redistribution stack also includes a redistribution layer disposed over the dielectric layer and including a trace. A first portion of the trace extends over the dielectric layer along a longitudinal direction adjacent to the opening, and a second portion of the trace is disposed in the opening and extends between the first portion of the trace and the exposed portion of the contact pad. The second portion of the trace has a maximum width along a transverse direction orthogonal to the longitudinal direction, and the maximum width of the second portion of the trace is no greater than about 3 times of a width of the first portion of the trace.

Abstract: A power electronics system is provided. The system includes at least one outer wall defining an outer zone including a plurality of first electronic components having a first normal operating maximum temperature and capable of generating electromagnetic fields. The system further includes at least one inner wall defining an inner zone disposed within the outer zone and including a plurality of second electronic components having a second normal operating maximum temperature, the first normal operating maximum temperature higher than the second normal operating maximum temperature, the inner zone substantially electromagnetically sealed against electromagnetic interference generated by the plurality of first electronic components.

Abstract: This invention provides a system which integrates motor vehicle component operation into actuators located in the rim of a vehicle steering wheel. The two system actuators are located in the steering wheel at the three o'clock and 12 o'clock positions for the right-hand actuator and the nine o'clock and 12 o'clock positions for the left-hand actuator. The actuators may operate in parallel with a conventional stalk switch or controls associated with an onboard computer and only operate a vehicle component when activated and subsequently depressed. The invention further provides for vehicle component operation which does not require a driver to remove his or her hands from the steering wheel. Furthermore, the system and apparatus of the invention when integrated with steering wheel and vehicle position detection systems provides a means to disengage an activated turn signal depending on the position of the steering wheel and/or the vehicle.

Abstract: A manufacturing method of a package structure including the following steps is provided. A plurality of first conductive connectors and a second conductive connector on an active surface of a die are formed. The first conductive connectors are electrically connected to the die. The second conductive connector is formed aside the first conductive connectors and electrically insulated to the die. A redistribution layer is formed on the die. The redistribution layer is electrically connected to the first conductive connectors and the second conductive connector. A conductive shield is formed on the redistribution layer to surround the second conductive connector and at least a portion of a sidewall of the die coupled the active surface. The die is electrically insulated from the conductive shield. Another manufacturing method of a package structure is also provided.

Abstract: A semiconductor package including a chip stack, at least one conductive wire, a first insulating encapsulant, a second insulating encapsulant, and a redistribution layer is provided, and a manufacturing method thereof is also provided. The chip stack includes semiconductor chips stacked on top of each other. Each semiconductor chip has an active surface that has at least one bonding region, and each bonding region is exposed by the chip stack. The conductive wire is correspondingly disposed on the bonding region. The first insulating encapsulant encapsulates the bonding region and the conductive wire. At least a portion of each conductive wire is exposed from the first insulating encapsulant. The second insulating encapsulant encapsulates the chip stack and the first insulating encapsulant. The first insulating encapsulant is exposed from the second insulating encapsulant. The redistribution layer is disposed on the first and second insulating encapsulant and electrically coupled to the conductive wire.

Abstract: A semiconductor package includes a substrate, an integrated circuit die, a lid and an adhesive. The integrated circuit die is disposed over the substrate. The lid is disposed over the substrate. The lid includes a cap portion and a foot portion extending from a bottom surface of the cap portion. The cap portion and the foot portion define a recess, and the integrated circuit die is accommodated in the recess. The adhesive includes a sidewall portion and a bottom portion. The sidewall portion contacts a sidewall of the foot portion. The bottom portion extends from the sidewall portion to between a bottom surface of the foot portion and the substrate.

Abstract: A semiconductor device includes: a wiring board including an insulating board and a wiring layer, the insulating board having an element mounting surface, which is a first main surface, and a back surface, which is a second main surface on the opposite side of the element mounting surface, the wiring layer being formed on the back surface and including a wiring portion and a heat dissipation portion; a power element that is a semiconductor element, is mounted on the element mounting surface of the wiring board, and is connected to the wiring portion; a spacer that is interposed between the power element and the element mounting surface of the wiring board and is connected to the back-surface-side heat dissipation portion; and a heatsink that sandwiches, together with the spacer, the power element and is secured to the spacer.

Abstract: A method to manufacture a semiconductor package includes: preparing a metal substrate; attaching semiconductor dies to the metal substrate at an interval; attaching a bonding film to the semiconductor dies; applying a mold material on the semiconductor dies and the metal substrate, and curing the mold material to form a mold member; grinding the mold member and the metal substrate to a thickness; removing the bonding film; attaching a redistribution layer to the semiconductor dies; and cutting between the semiconductor dies.

Abstract: A semiconductor device 1 includes a first drain terminal 4, connected to a drain electrode of a first semiconductor chip, a first gate terminal 5, connected to a gate electrode of the first semiconductor chip, a second drain terminal 6, connected to a drain electrode of a second semiconductor chip, a second gate terminal 7, connected to a gate electrode of the second semiconductor chip, a common source terminal 8, connected to a source electrode of the first semiconductor chip and a source electrode of the second semiconductor chip, and a sealing resin 9, sealing the respective semiconductor chips and the respective terminals. The respective terminals have exposed surfaces (lower surfaces) 43, 53, 63, 73, and 83 substantially flush with an outer surface (lower surface) 9b of the sealing resin 9 and exposed from the outer surface 9b.

Abstract: In a semiconductor device, a first skirt portion molded from a first mold resin and a second skirt portion molded from a second mold resin are provided on a heat dissipating surface of a lead frame. Also, a thinly-molded portion is molded integrally with the second skirt portion from the second mold resin. According to this kind of configuration, adhesion between the thinly-molded portion and lead frame is high, and the semiconductor device with excellent heat dissipation and insulation is obtained.

Abstract: An electro-optic device includes a chip provided with a mirror and a drive element adapted to drive the mirror, a light-transmitting cover adapted to cover the mirror in a planar view, and a spacer having contact with one surface of the chip between the cover and the chip. The entire part of one surface of the chip having contact with the spacer is made of a first material such as silicon oxide film having first thermal conductivity, and the spacer is made of a second material such as a quartz crystal having second thermal conductivity higher than the first thermal conductivity. The cover is made of a third material such as sapphire having third thermal conductivity higher than the second thermal conductivity.

Abstract: Disclosed herein are integrated circuit (IC) packages with temperature sensor traces, and related systems, devices, and methods. In some embodiments, an IC package may include a package substrate and an IC die disposed on the package substrate, wherein the package substrate includes a temperature sensor trace, and an electrical resistance of the temperature sensor trace is representative of an equivalent temperature of the temperature sensor trace.

Abstract: A semiconductor package includes a substrate, a first semiconductor chip and a second semiconductor chip adjacent to each other on the substrate, and a plurality of bumps on lower surfaces of the first and second semiconductor chips. The first and second semiconductor chips have facing first side surfaces and second side surfaces opposite to the first side surfaces. The bumps are arranged at a higher density in first regions adjacent to the first side surfaces than in second regions adjacent to the second side surfaces.

Abstract: An object is to provide a semiconductor device that is capable of wireless communication, such as an RFID tag, which can transmit and receive individual information without checking remaining capacity of a battery or changing batteries due to deterioration with time in the battery for a drive power supply voltage, and maintain a favorable a transmission/reception state even when electric power of an electromagnetic wave from a reader/writer is not sufficient. The semiconductor device includes a signal processing circuit, a first antenna circuit connected to the signal processing circuit, an antenna circuit group, a rectifier circuit-group and a battery connected to the signal processing circuit.

Abstract: A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.

Abstract: A phase leg in an inverter bridge has an upper transistor with upper gate, collector, and emitter terminals, wherein the upper gate and emitter terminals are arranged to create an upper common source inductance. A lower transistor has lower gate, collector, and emitter terminals, wherein the lower gate and emitter terminals are arranged to create a lower common source inductance. An upper diode is coupled across the upper collector and emitter terminals and substantially in parallel with the upper common source inductance. A lower diode is coupled across the lower collector and emitter terminals and substantially in parallel with the lower common source inductance. Thus, the diodes substantially bypass the common source inductances when carrying commutation current when one of the transistors is switching off. This allows the phase leg to possess significant common source inductance at the gate terminals while avoiding “shoot-through” issues.

Abstract: The present invention provides a degradable and recyclable epoxy conductive adhesive, which comprises the following raw materials in percentage by weight: 15% to 30% of epoxy resin, 1% to 10% of a curing agent, 0.1% to 2% of a reaction diluent and 15% to 85% of a conductive filler, wherein the curing agent comprises a breakable molecular structure. According to the epoxy conductive adhesive of the present invention, after the epoxy resin in the conductive adhesive is cured by using the recyclable and degradable epoxy resin curing agent of a specific molecular structure, the conductive adhesive can be degraded in normal pressure, mild and specific conditions, the process is simple and the operation is convenient, no contamination is brought to the environment, the recycling cost is largely reduced, and the recycling of the conductive adhesive has enormous economic and environmental advantages.

Abstract: A fan-out semiconductor package includes a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposite the active surface; an encapsulant encapsulating at least some portions of the first interconnection member and the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the semiconductor chip. The first interconnection member and the second interconnection member respectively include a plurality of redistribution layers electrically connected to the connection pads of the semiconductor chip, and the semiconductor chip has a groove defined in the active surface and between a peripheral edge of the semiconductor chip and the connection pads of the semiconductor chip.

Abstract: Tamper-respondent assemblies and methods of fabrication are provided which include a multi-layer stack having multiple discrete component layers stacked and electrically connected together via a plurality of electrical contacts in between the component layers. Further, the tamper-respondent assembly includes a tamper-respondent electronic circuit structure embedded within the multi-layer stack. The tamper-respondent electronic circuit structure includes at least one tamper-respondent sensor embedded, at least in part, within at least one component layer of the multiple discrete component layers of the multi-layer stack. The tamper-respondent electronic circuit structure defines a secure volume within the multi-layer stack. For instance, the tamper-respondent electronic circuit structure may be fully embedded within the multi-layer stack, with monitor circuitry of the tamper-respondent electronic circuit structure residing within the secure volume within the multi-layer stack.

Abstract: Embodiments of a method for packaging Integrated Circuit (IC) dies and an IC device are described. In an embodiment, a method for packaging IC dies involves creating openings on a substrate, where side surfaces of the openings on the substrate are covered by metal layers, placing the IC dies into the openings on the substrate, applying a second metal layer to the substrate, where the IC dies are electrically connected to at least a portion of the second metal layer, and cutting the substrate into IC devices.

Abstract: A microelectronic assembly can be made by forming a redistribution structure supported on a carrier, the structure including two or more layers of deposited dielectric material and two or more electrically conductive layers and including conductive features such as pads and traces electrically interconnected by vias. Electrical connectors may project above a second surface of the structure opposite an interconnection surface of the redistribution structure adjacent to the carrier. A microelectronic element may be attached and electrically connected with conductive features at the second surface, and a dielectric encapsulation can be formed contacting the second surface and surfaces of the microelectronic element. Electrically conductive features at the interconnection surface can be configured for connection with corresponding features of a first external component, and the electrical connectors can be configured for connection with corresponding features of a second external component.

Abstract: A semiconductor device includes semiconductor chips fixed to a board, an insulating plate having a through-hole formed therein, a first lower conductor including a lower main body formed on the lower surface of the insulating plate and soldered to any of the semiconductor chips, and a lower protrusion portion that connects with the lower main body, and extends to the outside of the insulating plate, a second lower conductor formed on a lower surface of the insulating plate and soldered to any of the semiconductor chips, an upper conductor including an upper main body formed on the upper surface of the insulating plate, and an upper protrusion portion that connects with the upper main body and extends to the outside of the insulating plate, and a connection portion provided in the through-hole and connects the upper main body and the second lower conductor.

Abstract: The semiconductor device of the present invention is a semiconductor device in which a first semiconductor chip including a first field effect transistor for a high-side switch, a second semiconductor chip including a second field effect transistor for a low-side switch, and a third semiconductor chip including a circuit that controls each of the first and second semiconductor chips are sealed with a sealing portion. A lead electrically connected to a pad of the first semiconductor chip for a source of the first field effect transistor and a lead electrically connected to a back-surface electrode of the second semiconductor chip for a drain of the second field effect transistor are disposed on the same side of the sealing portion in a plan view.

Abstract: The present disclosure provides an array substrate, a display panel and a display device. The array substrate includes a first conductive pattern and a second conductive pattern forming a ground (GND) protection circuit. The first conductive pattern includes a plurality of first conductive segments spaced apart from each other, and adjacent first conductive segments are connected to each other by the second conductive pattern, an insulating layer is arranged between the first conductive segments and the second conductive pattern, and the first conductive segments are connected to the second conductive pattern through via holes penetrating through the insulating layer. In addition, the present disclosure provides a display panel including the above array substrate. Furthermore, the present disclosure provides a display device including the above array substrate.

Abstract: A wired rubber contact including a lower film, an upper film, a plurality of conductive wires, a rubber layer, and a film guide. The lower film includes a plurality of lower electrode parts formed in openings. A periphery of the upper film is disposed within an interface between the central area and the peripheral area. The conductive wires are disposed between the lower film and the upper film, and connect between the lower electrode parts and the upper electrode parts. The rubber layer includes elastic material. A periphery of the rubber layer is protruded toward an outer side from the periphery of the upper film. The rubber layer maintains a constant distance between the lower film and the upper film. The film guide is disposed in the peripheral area of the lower film along a side surface of the rubber layer and integrally formed with the lower film.

Abstract: A method of making an electronic device may include forming at least one circuit layer that includes solder pads on a substrate and forming at least one liquid crystal polymer (LCP) solder mask having mask openings therein. The method may also include forming at least one thin film resistor on the LCP solder mask and coupling the at least one LCP solder mask to the substrate so that the at least one thin film resistor is coupled to the at least one circuit layer and so that the solder pads are aligned with the mask openings.

Abstract: Methods for depositing nanolaminate protective layers over a core layer to enable deposition of high quality conformal films over the core layer for use in advanced multiple patterning schemes are provided. In certain embodiments, the methods involve depositing a thin silicon oxide or titanium oxide film using plasma-based atomic layer deposition techniques with a low high frequency radio frequency (HFRF) plasma power, followed by depositing a conformal titanium oxide film or spacer with a high HFRF plasma power.

Abstract: A surgical stapling instrument includes a handle assembly, an elongate shaft extending distally from the handle assembly, and a tool assembly coupled to a distal end of the elongate shaft. The tool assembly includes a cartridge assembly including a plurality of surgical staples each including a code embedded portion and a first sensor for detecting the position of the surgical staples prior to and during a formation of the staples. The tool assembly further includes an anvil assembly including a second sensor that detects the position of the surgical staples after the formation of the surgical staples.

Abstract: A device includes a semiconductor chip, a plurality of planar metallization layers arranged over a main surface of the semiconductor chip, and a passive component including windings, wherein each of the windings is formed in one of the plurality of planar metallization layers.

Abstract: Implementations of semiconductor packages may include: a substrate coupled to one or more die and to one or more connectors, a glass lid coupled over one or more die by an adhesive and a housing comprising one or more sides and a bottom opening and a top opening. The substrate may be coupled to the housing at the bottom opening and the glass lid may be coupled under the housing at the top opening.

Abstract: Electronic circuits, electronic packages, and methods of fabrication are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board.

Abstract: A solar cell can include a substrate and a semiconductor region disposed in or above the substrate. The solar cell can also include a conductive contact disposed on the semiconductor region with the conductive contact including a conductive foil bonded to the semiconductor region.

Abstract: A mounting substrate that includes external connection electrodes on a rear surface of a base material, and mounting electrodes on a front surface of the base material. In-hole electrodes connect the external connection electrodes and the mounting electrodes. A reflective film containing Al is located between the base material and the mounting electrodes. The reflective film is covered with an insulating film layer.

Abstract: Tamper-respondent assemblies and methods of fabrication are provided which include a multi-layer stack having multiple discrete component layers stacked and electrically connected together via a plurality of electrical contacts in between the component layers. Further, the tamper-respondent assembly includes a tamper-respondent electronic circuit structure embedded within the multi-layer stack. The tamper-respondent electronic circuit structure includes at least one tamper-respondent sensor embedded, at least in part, within at least one component layer of the multiple discrete component layers of the multi-layer stack. The tamper-respondent electronic circuit structure defines a secure volume within the multi-layer stack. For instance, the tamper-respondent electronic circuit structure may be fully embedded within the multi-layer stack, with monitor circuitry of the tamper-respondent electronic circuit structure residing within the secure volume within the multi-layer stack.

Abstract: A micro-optic module couples a pair of substrates to opposing sides of a fast-axis collimating lens and a beam twister. The arrangement of optical elements is oriented substantially parallel to a neutral plane defined by propagation paths of the light from each emitter of an array of laser emitters. The pair of substrates may have substantially the same coefficient of thermal expansion and coefficient of thermal conductivity, and the micro-optic module may be configured to exhibit symmetry of thermal loading about the neutral plane when the array of laser emitters emits light at an operational power level. The micro-optic module may be coupled with an array of laser emitters, for example a laser diode bar. The module exhibits thermal properties that facilitate a consistently focused light beam with minimal positional drift, which may enable efficient and reliable coupling of the light beam to optical fibers and other high-tolerance applications.

Abstract: Tamper-respondent assemblies and methods of fabrication are provided which include a multi-layer stack having multiple discrete component layers stacked and electrically connected together via a plurality of electrical contacts in between the component layers. Further, the tamper-respondent assembly includes a tamper-respondent electronic circuit structure embedded within the multi-layer stack. The tamper-respondent electronic circuit structure includes at least one tamper-respondent sensor embedded, at least in part, within at least one component layer of the multiple discrete component layers of the multi-layer stack. The tamper-respondent electronic circuit structure defines a secure volume within the multi-layer stack. For instance, the tamper-respondent electronic circuit structure may be fully embedded within the multi-layer stack, with monitor circuitry of the tamper-respondent electronic circuit structure residing within the secure volume within the multi-layer stack.

Abstract: Methods of fabricating electronic circuits and electronic packages are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board.

Abstract: Semiconductor packages and manufacturing methods thereof are provided. One of the semiconductor packages includes a first chip, a second chip and a molding compound. The first chip has at least one first via and a protection layer thereon, and the at least one first via is formed in the protection layer. The second chip has at least one second via thereon. The molding layer encapsulates the first and second chips. The at least one second via is disposed in and contact with the molding layer, and top surfaces of the protection layer, the at least one first via and the at least one second via are substantially coplanar with a top surface of the molding layer.

Abstract: A trenched device wafer includes a device substrate layer having a top surface; a plurality of devices in the device substrate layer, and a trench in the top surface. The trench extends into the device substrate layer, and is located between a pair of adjacent devices of the plurality of devices. A method for forming a device die from a device wafer includes forming a trench in a top surface of the device wafer between two adjacent devices of the device wafer. The trench has a bottom surface located (a) at a first depth beneath the top surface and (b) at a first height above a wafer bottom surface. The method also includes, after forming the trench, decreasing a thickness of the device wafer, between the two adjacent devices, to a thickness less than the first height.

Abstract: A semiconductor package structure includes an encapsulant, a first chip, a second chip, a first redistribution layer and a second redistribution layer. The encapsulant has a first surface and a second surface opposite to each other. The first chip is in the encapsulant, wherein the first chip includes a plurality of contact pads exposed from the first surface of the encapsulant. The second chip is in the encapsulant, wherein second chip includes a plurality of contact pads exposed from the second surface of the encapsulant. The first redistribution layer is over the first surface of the encapsulant and electrically connected to the contact pads of the first chip. The second redistribution layer is over the second surface of the encapsulant and electrically connected to the contact pads of the second chip.

Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.