Abstract: Disclosed herein are nanoscale devices comprising one or more ferroelectric nanoshells characterized as having an extreme curvature in at least one spatial dimension. Also disclosed are ferroelectric field effect transistors and metal ferroelectric metal capacitors comprising one or more ferroelectric nanoshells. Methods for controlling spontaneous ferroelectric polarization in nanoshell devices are also disclosed.

Abstract: A semiconductor structure is disclosed. In one embodiment, the trench is formed in a substrate, including an upper portion and a lower portion, the upper portion including a lateral dimension larger than a lateral dimension of the lower portion. The lower portion is lined with a first insulating layer and is at least partially filled with a semiconductor material. The first insulating layer extends into the upper portion. A second insulating layer covers, at least partially, the substrate, a portion of the first insulating layer extending into the upper portion and the semiconducting material in the lower portion.

Abstract: A semiconductor package includes a substrate having an upper surface and a lower surface which faces away from the upper surface, and possessing a recess which is defined on the upper surface; and a semiconductor chip mounted to the upper surface of the substrate, having one surface which faces the upper surface and the other surface which faces away from the one surface, and warped in a smile shape such that a warped edge portion of the semiconductor chip is inserted into the recess.

Abstract: An apparatus and a method of manufacturing the apparatus. The apparatus includes a main nanowire and branch nanowires emanating from the main nanowire. The main nanowire may have a first portion and a second portion. The first portion may have a first carrier concentration and the second portion may have a second carrier concentration, different to the first carrier concentration. Each branch nanowire may emanate from the first portion of the main nanowire. Each branch nanowire may emanate from the main nanowire at a substantially fixed distance along a length of the main nanowire.

Abstract: Provided are a heterogeneous substrate, a nitride-based semiconductor device using the same, and a manufacturing method thereof to form a high-quality non-polar or semi-polar nitride layer on a non-polar or semi-polar plane of the heterogeneous substrate by adjusting a crystal growth mode. A base substrate having one of a non-polar plane and a semi-polar plane is prepared, and a nitride-based nucleation layer is formed on the plane of the base substrate. A first buffer layer is grown faster in the vertical direction than in the lateral direction on the nucleation layer. A lateral growth layer is grown faster in the lateral direction than in the vertical direction on the first buffer layer. A second buffer layer is formed on the lateral growth layer. A silicon nitride layer having a plurality of holes may be formed between the lateral growth layer on the first buffer layer and the second buffer layer.

Abstract: To provide a semiconductor device in which an interval between first wells can be shortened by improving a separation breakdown voltage between the first wells and a method for manufacturing the same.

Abstract: The present disclosure relates to the field of epitaxial structures for microelectronic device formation, particularly to heavily doped, substrates having a compensation component embedded along the dopant to prevent bowing of the substrate during deposition of an epitaxial layer.

Abstract: The integrated circuit comprises a support substrate having opposite first and second main surfaces. A cavity passes through the support substrate and connects the first and second main surfaces. The integrated circuit comprises a device with a mobile element, the mobile element and a pair of associated electrodes of which are included in a cavity. An anchoring node of the mobile element is located at the level of the first main surface. The integrated circuit comprises a first elementary chip arranged at the level of the first main surface and electrically connected to the device with a mobile element.

Abstract: An impurity doping system is disclosed, which includes an impurity doping device for doping an impurity into a surface of a solid state base body, a measuring device for measuring an optical characteristic of an area into which the impurity is doped, and an annealing device for annealing the area into which the impurity is doped. The impurity doping system realizes an impurity doping not to bring about a rise of a substrate temperature, and measures optically physical properties of a lattice defect generated by the impurity doping step to control such that subsequent steps are optimized.

Abstract: According to an embodiment, an active layer is formed on a first surface of a semiconductor substrate, a wiring layer is formed on the active layer, and an insulating layer is formed covering the wiring layer. The first surface of the semiconductor substrate is bonded to a support substrate via the insulating layer, and the semiconductor substrate bonded to the support substrate is thinned leaving the semiconductor substrate having a predetermined thickness which covers the active layer from a second surface. At least a part of area of the thinned semiconductor substrate is removed to expose the active layer.

Abstract: A semiconductor device may include, but is not limited to: a semiconductor substrate; a first insulating film; and a first semiconductor film. The semiconductor substrate has a groove defining a first portion of the semiconductor substrate. The first portion extends upward. The first insulating film fills the groove. The first insulating film has a recess adjacent to a side surface of the first portion. The first semiconductor film contacts an upper surface and the side surface of the first portion.

Abstract: The present disclosure is directed to a thin film resistor having a first resistor layer having a first temperature coefficient of resistance and a second resistor layer on the first resistor layer, the second resistor layer having a second temperature coefficient of resistance different from the first temperature coefficient of resistance. The first temperature coefficient of resistance may be positive while the second temperature coefficient of resistance is negative. The first resistor layer may have a thickness in the range of 50 and 150 angstroms and the second resistor layer may have a thickness in the range of 20 and 50 angstroms.

Abstract: A memory device including a first electrode; a second electrode; and a memory cell positioned between the first electrode and the second electrode, the memory cell including a core of a first phase change material and a cladding of a second phase change material, wherein the first phase change material has a lower crystallization temperature than the second phase change material.

Abstract: The present invention relates to a method for molecular adhesion bonding between at least a first wafer and a second wafer involving aligning the first and second wafers, placing the first and second wafers in an environment having a first pressure (P1) greater than a predetermined threshold pressure; bringing the first wafer and the second wafer into alignment and contact; and initiating the propagation of a bonding wave between the first and second wafer after the wafers are aligned and in contact by reducing the pressure within the environment to a second pressure (P2) below the threshold pressure. The invention also relates to the three-dimensional composite structure that is obtained by the described method of adhesion bonding.

Abstract: A semiconductor device in which damages to an element such as a transistor are reduced even when external force such as bending is applied and stress is generated in the semiconductor device. The semiconductor device includes a first island-like reinforcement film over a substrate having flexibility; a semiconductor film including a channel formation region and an impurity region over the first island-like reinforcement film; a first conductive film over the channel formation region with a gate insulating film interposed therebetween; a second island-like reinforcement film covering the first conductive film and the gate insulating film.

Abstract: A method is described for filling cavities in wafers, the cavities being open to a predetermined surface of the wafer, including the following steps: applying a lacquer-like filling material to the predetermined surface of the wafer; heating the wafer at a first temperature; driving out gas bubbles enclosed in the filling material by heating the wafer under vacuum at a second temperature which is equal to or higher than the first temperature; and curing the filling material by heating the wafer at a third temperature which is higher than the second temperature. Furthermore, also described is a blind hole filled using such a method and general 3D cavities as well as a wafer having insulation trenches of a silicon via filled using such a method.

Abstract: Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.

Abstract: In a CSP type semiconductor device, the invention prevents a second wiring from forming a narrowed portion on a lower surface of a step portion at the time of forming the second wiring that is connected to the back surface of a first wiring formed near a side surface portion of a semiconductor die on the front surface and extends onto the back surface of the semiconductor die over the step portion of a window that is formed from the back surface side of the semiconductor die so as to expose the back surface of the first wiring. A glass substrate is bonded on a semiconductor substrate on which a first wiring is formed on the front surface near a dicing line with an adhesive resin being interposed therebetween. The semiconductor substrate is then etched from the back surface to form a window having step portions with inclined sidewalls around the dicing line as a center.

Abstract: A semiconductor device and a manufacturing method thereof is disclosed in which the semiconductor device includes a p-type anode layer formed by a transition metal acceptor transition, and the manufacturing process is significantly simplified without the breakdown voltage characteristics deteriorating. An inversion advancement region inverted to a p-type by a transition metal acceptor transition, and in which the acceptor transition is advanced by point defect layers, is formed on the upper surface of an n-type drift layer. The inversion advancement region configures a p-type anode layer of a semiconductor device of the invention. The transition metal is, for example, platinum or gold. An n-type semiconductor substrate with a concentration higher than that of the n-type drift layer is adjacent to the lower surface of the n-type drift layer.

Abstract: The semiconductor device of the present invention includes: a gate insulating film formed on a semiconductor region of a first conductivity type; a gate electrode formed on the gate insulating film; and a channel doped layer of the first conductivity type formed in the semiconductor region beneath the gate electrode. The channel doped layer contains carbon as an impurity.

Abstract: A structure consisting of well-ordered semiconductor structures embedded in a binder material which maintains the ordering and orientation of the semiconductor structures. Methods for forming such a structure include forming the semiconductor structures on a substrate, casting a binder material onto the substrate to embed the semiconductor structures in the binder material, and separating the binder material from the substrate at the substrate. These methods provide for the retention of the orientation and order of highly ordered semiconductor structures in the separated binder material.

Abstract: A fabricating process of circuit substrate sequently includes: providing a substrate with a pad and a dielectric stack layer disposed at the substrate and overlaying the pad, in which the stack layer includes two dielectric layers and a third dielectric layer located between the two dielectric layers, and the etching rate of the third dielectric layer is greater than the etching rate of the two dielectric layers; forming an opening corresponding to the pad at the stack layer; performing a wet etching process on the stack layer to remove the portion of the third dielectric layer surrounding the opening to form a gap between the portions of the two dielectric layers surrounding the opening; performing a plating process on the stack layer and the pad to respectively form two plating layers at the stack layer and the pad, in which the gap isolates the two plating layers from each other.

Abstract: Nanosized filamentary carbon structures (CNTs) nucleating over a catalyzed surface may be grown in an up-right direction reaching a second surface, spaced from the first surface, without the need of applying any external voltage source bias. The growth process may be inherently self-stopping, upon reaching a significant population of grown CNTs on the second surface. A gap between the two surfaces may be defined for CNT devices being simultaneously fabricated by common integrated circuit integration techniques. The process includes finding that for separation gaps of up to a hundred or more nanometers, a difference between the respective work functions of the materials delimiting the gap space, for example, different metallic materials or a doped semiconductor of different dopant concentration or type, may produce an electric field intensity orienting the growth of nucleated CNTs from the surface of one of the materials toward the surface of the other material.

Abstract: An embodiment of a method for producing traceable integrated circuits includes forming on a wafer of semiconductor material functional regions for implementing specific functionalities of corresponding integrated circuits, forming at least one seal ring around each functional region of the corresponding integrated circuit, and forming on each integrated circuit at least one marker indicative of information of the integrated circuit. Forming on each integrated circuit at least one marker may include forming the at least one marker on at least a portion of the respective seal ring that is visible.

Abstract: In a semiconductor device having an enlarged contact area between a contact structure and a substrate, the substrate may include a first region on which a conductive structure is arranged and a second region defining the first region. The first region may include a multi-faced polyhedral recess of which at least one of the sidewalls is slanted with respect to a surface of the substrate. An insulation layer may be formed on the substrate to a thickness that is sufficient to cover the conductive structure. The insulation layer has a contact hole that may be communicated with the recess. The active region of the substrate is exposed through the contact hole. A conductive pattern is positioned in the recess and the contact hole. Accordingly, the contact resistance at the active region of the substrate may be kept to a relatively low value even though the gap distances and line width of pattern lines are reduced.

Abstract: A conventional laser processing method has a problem that the number of scanning lines is large, and it is difficult to shorten the time needed for the marking. In a laser processing method of the present invention, a first laser processing is performed in accordance with the outer border of, for example, an English letter “A,” and thereafter, second and subsequent laser processings are performed on an inner region inside the outer border. In this event, for the second and subsequent laser processings, the respective processing lines (scanning lines) are set up in a longitudinal direction of a processing region. Thus, the number of processing lines is greatly reduced. As a result, the time needed for the marking is greatly shortened, and the laser marking workability is improved.

Abstract: Sapphire substrates are used chiefly for epitaxial growth of nitride semiconductor layers, to provide a sapphire substrate of which the shape and/or amount of warping can be controlled efficiently and precisely and of which substrate warping that occurs during layer formation can be suppressed and substrate warping behavior can be minimized, to provide nitride semiconductor layer growth bodies, nitride semiconductor devices, and nitride semiconductor bulk substrates using such substrates, and to provide a method of manufacturing these products. Reformed domain patterns are formed within a sapphire substrate and the warp shape and/or amount of warping of the sapphire substrate are controlled by means of multiphoton absorption by condensing and scanning a pulsed laser through a polished surface of the sapphire substrate.

Abstract: Compound semiconductor devices and methods of doping compound semiconductors are provided. Embodiments of the invention provide post-deposition (or post-growth) doping of compound semiconductors, enabling nanoscale compound semiconductor devices including diodes and transistors. In one method, a self-limiting monolayer technique with an annealing step is used to form shallow junctions. By forming a sulfur monolayer on a surface of an InAs substrate and performing a thermal annealing to drive the sulfur into the InAs substrate, n-type doping for InAs-based devices can be achieved. The monolayer can be formed by surface chemistry reactions or a gas phase deposition of the dopant. In another method, a gas-phase technique with surface diffusion is used to form doped regions. By performing gas-phase surface diffusion of Zn into InAs, p-type doping for InAs-based devices can be achieved.

Abstract: A method for producing micromechanical patterns having a relief-like sidewall outline shape or an angle of inclination that is able to be set, the micromechanical patterns being etched out of a SiGe mixed semiconductor layer that is present on or deposited on a silicon semiconductor substrate, by dry chemical etching of the SiGe mixed semiconductor layer; the sidewall outline shape of the micromechanical pattern being developed by varying the germanium proportion in the SiGe mixed semiconductor layer that is to be etched; a greater germanium proportion being present in regions that are to be etched more strongly; the variation in the germanium proportion in the SiGe mixed semiconductor layer being set by a method selected from the group including depositing a SiGe mixed semiconductor layer having varying germanium content, introducing germanium into a silicon semiconductor layer or a SiGe mixed semiconductor layer, introducing silicon into a germanium layer or an SiGe mixed semiconductor layer and/or by therm

Abstract: Disclosed is a method of forming a semiconductor device with drift regions of a first doping type and compensation regions of a second doping type, and a semiconductor device with drift regions of a first doping type and compensation regions of a second doping type.

Abstract: A gallium nitride-based semiconductor device includes a composite substrate and a gallium nitride layer. The composite substrate includes a silicon substrate and a filler. The silicon substrate includes a first surface and a second surface opposite to the first surface, and the first surface defines a number of grooves therein. The filler is filled into the number of grooves on the first surface of the silicon substrate. A thermal expansion coefficient of the filler is bigger than that of the silicon substrate. The gallium nitride layer is formed on the second surface of the silicon substrate.

Abstract: A semiconductor device for electrostatic discharge (ESD) protection includes a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.

Abstract: A method is demonstrated to form an SOI substrate having a silicon layer with reduced surface roughness in a high yield. The method includes the step of bonding a base substrate such as a glass substrate and a bond substrate such as a single crystal semiconductor substrate to each other, where a region in which bonding of the base substrate with the bond substrate cannot be performed is provided at the interface therebetween. Specifically, the method is exemplified by the combination of: irradiating the bond substrate with accelerated ions; forming an insulating layer over the bond substrate; forming a region in which bonding cannot be performed in part of the surface of the bond substrate; bonding the bond substrate and the base substrate to each other with the insulating layer therebetween; and separating the bond substrate from the base substrate, leaving a semiconductor layer over the base substrate.

Abstract: Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side.

Abstract: A semiconductor device of the present invention is arranged in such a manner that a MOS non-single-crystal silicon thin-film transistor including a non-single-crystal silicon thin film made of polycrystalline silicon, a MOS single-crystal silicon thin-film transistor including a single-crystal silicon thin film, and a metal wiring are provided on an insulating substrate. With this arrangement, (i) a semiconductor device in which a non-single-crystal silicon thin film and a single-crystal silicon thin-film device are formed and high-performance systems are integrated, (ii) a method of manufacturing the semiconductor device, and (iii) a single-crystal silicon substrate for forming the single-crystal silicon thin-film device of the semiconductor device are obtained.

Abstract: A semiconductor device comprises an Si substrate 10 and a compound layer 11 of Si1-XGeX disposed on the substrate 10. X is varied from 0 to 0.2 away from the substrate 10 towards the upper surface of the compound layer 11, with the rate of change of X increasing through the layer. The increasing rate of change of X significantly improves the defectivity levels and the surface roughness at the surface of layer 11.

Abstract: A method for fabricating an encapsulant cavity integrated circuit package system includes: providing an interposer; forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and the interposer; and attaching a component on the interposer in the encapsulant cavity.

Abstract: A semiconductor component includes a semiconductor body having a first side, a second side, an edge delimiting the semiconductor body in a lateral direction, an inner region and an edge region. A first semiconductor zone of a first conduction type is arranged in the inner region and in the edge region. A second semiconductor zone of a second conduction type is arranged in the inner region and adjacent to the first semiconductor zone. A trench is arranged in the edge region and has first and second sidewalls and a bottom, and extends into the semiconductor body. A doped first sidewall zone of the second conduction type is adjacent to the first sidewall of the trench. A doped second sidewall zone of the second conduction type is adjacent to the second sidewall of the trench. A doped bottom zone of the second conduction type is adjacent to the bottom of the trench. Doping concentrations of the sidewall zones are lower than a doping concentration of the bottom zone.

Abstract: The present invention relates to a carbon ribbon for covering in a thin layer of semiconductor material, and to a method of deposited such a layer on a substrate constituted by a carbon ribbon. At least one of the two faces of the carbon ribbon is for covering in a layer of semiconductor material by causing the ribbon to pass substantially vertically upwards through a bath of molten semiconductor material. According to the invention, the two edges of at least one of the two faces of the carbon ribbon project so as to form respective rims.

Abstract: Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice mismatch between an epitaxial material and the substrate. Devices formed by the methods described exhibit better interfacial adhesion and lower defect density than devices formed without texture. Silicon substrates are shown with gallium nitride epitaxial growth and devices such as LEDs are formed within the gallium nitride.

Abstract: A wafer laser-marking method is provided. First, a wafer having a first surface (an active surface) and a second surface (a back surface) opposite to each other is provided. Next, the wafer is thinned. Then, the thinned wafer is fixed on a non-UV tape such that the second surface of the wafer is attached to the tape. Finally, the laser marking step is performed, such that a laser light penetrates the non-UV tape and marks a pattern on the second surface of the wafer. According to the laser-marking method of the embodiment, the pattern is formed by the non-UV residuals left on the second surface of the wafer, and the components of the glue residuals at least include elements of silicon and carbon.

Abstract: According to one embodiment, a nitride semiconductor device includes a substrate, an Alx1Ga1-x1N first buried layer, an InyAlzGa1-y-zN buried layer and an Alx2Ga1-x2N second buried layer. The substrate has protrusions formed in an in-plane direction on a first major surface, and a depression between adjacent ones of the protrusions. The first buried layer is formed on the depression and one of the protrusions. The InyAlzGa1-y-zN buried layer is formed on the first buried layer. The second buried layer is formed on the InyAlzGa1-y-zN buried layer. A portion of the first buried layer formed on the depression and a portion of the first buried layer formed on the one of the protrusions are not connected to each other. A portion of the InyAlzGa1-y-zN buried layer formed above the depression and a portion of the InyAlzGa1-y-zN buried layer formed above the one of the protrusions are connected to each other.

Abstract: According to a process for manufacturing an integrated power device, projections and depressions are formed in a semiconductor body that extend in a first direction and are arranged alternated in succession in a second direction, transversely to the first direction. Further provided are a first conduction region and a second conduction region. The first conduction region and the second conduction region define a current flow direction parallel to the first direction, along the projections and the depressions. To form the projections and the depressions, portions of the semiconductor body that extend in the first direction and correspond to the depressions, are selectively oxidized.

Abstract: An epitaxial wafer comprises a silicon substrate, a gettering epitaxial film formed thereon and containing silicon and carbon, and a main silicon epitaxial film formed on the gettering epitaxial film, in which the gettering epitaxial film has a given carbon atom concentration and carbon atoms are existent between its silicon lattices.

Abstract: A semiconductor device includes a semiconductor substrate, a surface electrode formed on the semiconductor substrate, an ineffective region formed to surround the surface electrode, and an ID-indicating portion made of a different material than the surface electrode and formed on the surface electrode to indicate an ID. The area of the ineffective region is smaller than the area of the surface electrode.

Abstract: A microstructure has at least one bonding substrate and a reactive multilayer system. The reactive multilayer system has at least one surface layer of the bonding substrate with vertically oriented nanostructures spaced apart from one another. Regions between the nanostructures are filled with at least one material constituting a reaction partner with respect to the material of the nanostructures. A method for producing at least one bonding substrate and a reactive multilayer system, includes, for forming the reactive multilayer system, at least one surface layer of the bonding substrate is patterned or deposited in patterned fashion with the formation of vertically oriented nanostructures spaced apart from one another, and regions between the nanostructures are filled with at least one material constituting a reaction partner with respect to the material of the nanostructures.

Abstract: A semiconductor device which is designed based on RDR, suppresses the occurrence of a trouble at the boundary between an active region and a power wire and therearound and is small in size and highly integrated. The semiconductor device includes a first conductive impurity region for functional elements which is formed over the main surface of a semiconductor substrate and a second conductive impurity region for power potential to which power potential is applied in at least one standard cell. It also includes insulating layers which are formed over the main surface of the semiconductor substrate and have throughholes reaching the main surface of the semiconductor substrate, and a conductive layer for contact formed in the throughholes of the insulating layers.

Abstract: Disclosed are a variety of porous and non-porous wire-like structures of microscopic and nanoscopic scale. For instance, disclosed are structures that comprise a porous object that comprises: (i) a first region; and (ii) a second region adjacent to the first region along an axis of the object, where the first region has at least one porous property different from that of the second region. Also disclosed are structures that include: (i) a high resistivity silicon; and (ii) a cross-section that is substantially perpendicular to an axis of the object. Also disclosed are methods of making and using such structures.

Abstract: A method for producing a semiconductor wafer having a multilayer film, in production of a semiconductor device by the steps of forming a porous layer on a surface of a semiconductor wafer by changing a surface portion into the porous layer, forming a semiconductor film on a surface of the porous layer to produce a semiconductor wafer having a multilayer film, fabricating a device on the semiconductor film, and producing the semiconductor device by delaminating the semiconductor film along the porous layer, the semiconductor film having the device formed thereon, including flattening the semiconductor wafer after delaminating and reusing the flattened semiconductor wafer, the method further including a thickness adjusting step of adjusting a whole thickness of the semiconductor wafer having a multilayer film to be produced by reusing the semiconductor wafer so as to satisfy a predetermined standard.

Abstract: A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer has a first main surface and a second main surface. The second main surface of the device layer is disposed on a surface of the dielectric layer opposite to the semiconductor substrate. A plurality of intended die areas are defined on the first main surface of the device layer. The plurality of intended die areas are separated from one another. A plurality of die access trenches are formed in the semiconductor substrate from the second main surface. Each of the plurality of die access trenches are disposed generally beneath at least a respective one of the plurality of intended die areas.