Abstract: A method of making a package is disclosed. The method may include forming bond pads on a first surface of a substrate, forming leads in the substrate by etching recesses in a second surface of the substrate, the second surface being opposite the first surface, and plating at least a portion of a top surface of the leads with a layer of finish plating. The method may also include thermosonically bonding the leads to a die by thermosonically bonding the finish plating to the die and encapsulating the die and the leads in an encapsulant.

Abstract: A planar lighting device includes: a light guide plate; a plurality of light sources arranged in line along a longitudinal direction of a side end surface of the light guide plate, each of light sources including a pair of electrode terminals; and a mounting substrate on which the light sources are mounted, the mounting substrate including a conductive pattern including a plurality of pairs of lands to which the respective pairs of electrode terminals of the light sources are connected. The light sources are mounted such that, in a longitudinal direction of the light sources, a gap between an outer side of each of the pairs of electrode terminals and an outer side of corresponding one of the pairs of lands is smaller than a gap between an inner side of the pair of electrode terminals and an inner side of the corresponding pair of lands.

Abstract: The present disclosure relates to a wafer level chip scale package (WLCSP) with a stress absorbing cap substrate. The cap substrate is bonded to a die through a bond ring and a bond pad arranged on an upper surface of the cap substrate. A through substrate via (TSV) extends from the bond pad, through the cap substrate, to a lower surface of the cap substrate. Further, recesses in the upper surface extend around the bond pad and along sidewalls of the bond ring. The recesses absorb induced stress, thereby mitigating any device offset in the die.

Abstract: An electronic device includes a first accommodation portion to accommodate a first card, a second accommodation portion to accommodate a second card, and a holding member capable of holding the first card and the second card. The first accommodation portion and the second accommodation portion are arranged so that an ejection path of the first card and an ejection path of the second card overlap. The holding member is located in an area where the ejection path of the first card and the ejection path of the second card overlap.

Abstract: A semiconductor structure comprising a carrier wafer and a device wafer. The carrier wafer comprises trenches sized and configured to receive conductive pillars of the device wafer. The carrier wafer and the device wafer are fusion bonded together and back side processing effected on the device wafer. The device wafer may be released from the carrier wafer by one or more of mechanically cleaving, thermally cleaving, and mechanically separating. Methods of forming the semiconductor structure including the carrier wafer and the device wafer are disclosed.

Abstract: A semiconductor device includes: a base plate including a metallic base plate and an insulating film provided on the metallic base plate; a semiconductor chip provided on the base plate; a control board disposed above the semiconductor chip; and a relay terminal connected to a signal electrode of the semiconductor chip through a signal line wire, extending to the control board, and connected to the control board, wherein the relay terminal is directly fixed to the insulating film of the base plate.

Abstract: A semiconductor device includes a semiconductor chip having an active surface and a non-active surface opposite to the active surface, an upper insulating layer provided on the non-active surface of semiconductor chip, and a via and a connection pad penetrating the semiconductor chip and the upper insulating layer, respectively. The connection pad has a first surface exposed outside the upper insulating layer and a second surface opposite to the first surface and facing the semiconductor chip. The first surface of the connection pad is coplanar with an upper surface of the upper insulating layer.

Abstract: A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and at least one deep well within the at least one device layer. A protective layer is disposed over the at least one deep well, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 106 Ohm-cm.

Abstract: A fan-out semiconductor package and an electronic device including the same are provided. The fan-out semiconductor package includes a semiconductor chip; an interconnection member electrically connected to the semiconductor chip and having a connection terminal pad; and a passivation layer disposed at one side of the interconnection member and having an opening part opening a portion of the connection terminal pad. Distances from a center of the connection terminal pad to at least two points of an edge thereof are different from each other.

Abstract: Described herein is a surge protection device for protecting luminaires from high surge voltages. The surge protection device comprises shunt impedance elements positioned in connections between a driver and a light-emitting diode module to direct current generated by differential mode surges and/or common mode surges to ground so that light-emitting diode elements in the light-emitting diode module are not destroyed. Series impedance elements may also be provided between the driver and the shunt impedance elements.

Abstract: Tamper-respondent assemblies and methods of fabrication are provided which include a multi-layer stack having multiple discrete component layers stacked and electrically connected together via a plurality of electrical contacts in between the component layers. Further, the tamper-respondent assembly includes a tamper-respondent electronic circuit structure embedded within the multi-layer stack. The tamper-respondent electronic circuit structure includes at least one tamper-respondent sensor embedded, at least in part, within at least one component layer of the multiple discrete component layers of the multi-layer stack. The tamper-respondent electronic circuit structure defines a secure volume within the multi-layer stack. For instance, the tamper-respondent electronic circuit structure may be fully embedded within the multi-layer stack, with monitor circuitry of the tamper-respondent electronic circuit structure residing within the secure volume within the multi-layer stack.

Abstract: A light emitting device includes a substrate, a light emitting element, a first resin member, and a second resin member. The substrate includes a base member, a plurality of wiring portions disposed on a first surface and a second surface of the base member, and a covering layer that covers the wiring portions disposed on the first surface and has an opening formed in a part of the covering layer. The light emitting element is arranged on the wiring portions disposed on the first surface in the opening of the covering layer and having an upper surface at a position higher than the covering layer. The first resin member is arranged at least in the opening of the covering layer and at periphery of the light emitting element. The second resin member seals the substrate and the light emitting element and has an outer border that is arranged above the covering layer. The covering layer is exposed at an outer side of the second resin member.

Abstract: A wireless identification system and method used for identifying medical vials having a metallic crimp includes an RFID tag having a first antenna element located at the crimp so as to be capacitively coupled to the crimp to increase the effective surface area of the RFID antenna, and a second antenna element mounted to the side of the vial between the ends of the labeling mounted on the vial so as to not mask any visually readable information of the labeling. Dielectric adhesive is used in one embodiment to couple the antenna element to the crimp. The invention is particularly useful for small vials. A manufacturing method in which the wireless tag is an integral part of the container is disclosed.

Abstract: The semiconductor device has a semiconductor chip having a first-signal-output circuit operating at a first-power-supply voltage, a second-signal-output circuit operating at a second power supply voltage, and a plurality of bump electrodes; and a wiring board including a first main surface facing the main surface of the semiconductor chip, a second main surface opposite to the first main surface with a wiring layer therebetween, first external terminals on the first main surface, and second ones on the second main surface; the former being mounted on the latter to couple the bump electrodes to the first external terminals. When viewed from the second main surface, second external terminals to be supplied with the first signal and the second signal are arranged closer to the semiconductor chip than second external terminals to be supplied with the first power supply voltage and the second power supply voltage.

Abstract: A process of manufacturing component with a composite film including a matrix made of thermoplastic polymer and particles inside this matrix. This process includes heating the composite film in order for its temperature to exceed the glass transition temperature of its matrix, then when the composite film is softened, flattening an external face of the composite film by a smooth face resting directly over the whole of this external face, this smooth face forming part of the front face of a flexible membrane, the whole of the rear face of which, located on the side opposite the front face, is pushed against the composite film by a fluid, then cooling the composite film below the glass transition temperature, then withdrawing the membrane in order to mechanically separate its front face from the external face of the composite film.

Abstract: The present invention provides a structure. In an exemplary embodiment, the structure includes a base material, at least one metal pad, where a first surface of the metal pad is in contact with the base material, and a metal pedestal, where the metal pedestal is in contact with the metal pad, where a radial alignment of the metal pad is shifted by an offset distance, with respect to the metal pedestal, such that the metal pad is shifted towards a center axis of the base material, where a first dimension of the metal pad is smaller than a second dimension of the metal pad, where the second dimension is orthogonal to a line running from a center of the metal pad to the center axis of the base material, where the first dimension is parallel to the line.

Abstract: A bumpless fan-out chip stacking structure includes a first die disposed on the substrate, a first dielectric layer conformally covering on the first die, a first RDL disposed on the first dielectric layer, a first via plug electrically connecting the first die to the first RDL, a first capping layer conformally covering on the first RDL, a second die attached on the first capping layer, a second dielectric layer conformally covering on the second die, a second RDL disposed on the second dielectric layer, a second via plug electrically connecting the second die to the second RDL, a second capping layer conformally covering on the second RDL, a patterned conductive layer disposed on the second capping layer and an interlayer connection structure electrically connecting the patterned conductive layer to the first RDL and the second RDL respectively.

Abstract: Solid-state radiation transducer (SSRT) devices and methods of manufacturing and using SSRT devices are disclosed herein. One embodiment of the SSRT device includes a radiation transducer (e.g., a light-emitting diode) and a transmissive support assembly including a transmissive support member, such as a transmissive support member including a converter material. A lead can be positioned at a back side of the transmissive support member. The radiation transducer can be flip-chip mounted to the transmissive support assembly. For example, a solder connection can be present between a contact of the radiation transducer and the lead of the transmissive support assembly.

Abstract: A semiconductor structure includes at least two substrate layers, each of the at least two substrate layers having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The semiconductor structure also includes a substrate joining layer disposed between and coupled to the second surface of a first one of the at least two substrate layers and the first surface of a second one of the at least two substrate layers. The substrate joining layer includes at least one integrated circuit (IC) structure disposed between the first and second surfaces of said substrate joining layer. A corresponding method for fabricating a semiconductor structure is also provided.

Abstract: An electronic structure is provided. The electronic structure includes a first board structure, a first contact pad, a first joint member, and a second joint member. The first contact pad is disposed on the first board structure. The first joint member is disposed on the first contact pad, in which the first joint member has a first Young's modulus. The second joint member is disposed on the first joint member, in which the second Young's modulus has a second Young's modulus, and the second Young's modulus is greater than the first Young's modulus.

Abstract: An electrical interconnect assembly for use in an integrated circuit package includes a mounting substrate having a thickness defined between a first surface and a second surface thereof and at least one electrically conductive pad formed on the first surface of the mounting substrate. A metallization layer coats a surface of the at least one electrically conductive pad and is electrically coupled thereto. The metallization layer also coats portion of the first surface of the mounting substrate and extends through at least one via formed through the thickness of the mounting substrate. A method of manufacturing an electrical interconnect assembly includes forming at least one top side contact pad on a top surface of a mounting substrate and depositing a metallization layer on the top side contact pad(s), on an exposed portion of the top surface, and into via(s) formed through a thickness of the mounting substrate.

Abstract: A flexible display panel including: a flexible panel including a first region including a display region and oriented on a first plane and a second region including a non-display region and oriented on a second plane different from the first plane; and a flexible encapsulation member disposed on the flexible panel so as to encapsulate at least the display region.

Abstract: A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.

Abstract: A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and at least one deep well within the at least one device layer. A protective layer is disposed over the at least one deep well, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 106 Ohm-cm.

Abstract: A semiconductor device includes a base plate, a case, a power semiconductor element, and a control semiconductor element. Case is provided on base plate. Power semiconductor element is disposed over base plate in case. Control semiconductor element is disposed in case. Case has an opening formed therein opposite to base plate. The semiconductor device further includes a cover to close opening in case. Cover has a hole formed in at least a portion of a region overlapping control semiconductor element in plan view.

Abstract: A probe card is adapted for testing at least one integrated circuit that integrated on a corresponding at least one die of a semiconductor material wafer. The probe card includes a board adapted for the coupling to a tester apparatus. Several probes are coupled to the board. The probe card includes replaceable elementary units, wherein each unit includes at least one probe for contacting externally-accessible terminals of an integrated circuit under test. The replaceable elementary units are arranged so as to correspond to an arrangement of at least one die on the semiconductor material wafer containing integrated circuits to be tested.

Abstract: Multilayer structure, including a substrate film having a first and second opposite side, said substrate film including electrically insulating material, conductive traces on the first side of the substrate film for establishing a predetermined circuit design, a connector element laid upon the first side of, said substrate film, one side of the connector element facing the structure internals and the other, opposite side facing the environment on the second side of the substrate film including a number of electrically conductive contact members electrically connected to the circuit on the first side of the substrate film and configured to contact one or more electrical contact members of an external element responsive to mating the external element with the connector element, and a plastic layer molded onto the substrate film and the connector element so as to cover said one side of the connector element and the circuit.

Abstract: A bonding film has at least a left longitudinal branch, and a lower latitudinal branch; a first bonding area is configured in a first branch, and a second bonding area is configured in a second branch. A plurality of outer top metal pads and a plurality of inner top metal pads are exposed on a top surface within each bonding area. A central chip is configured in a central area of the bonding film and is electrically coupled to the inner top metal pad, and at least two peripheral chips are configured neighboring to the central chip and electrically coupled to the outer top metal pads. Each of the inner top metal pads is electrically coupled to a corresponding outer top metal pad through an embedded circuitry. The central chip communicates with the peripheral chips through the inner top metal pad, embedded circuitry, and outer top metal pad of the bonding film.

Abstract: A hearing aid comprising a microphone, a receiver, hearing aid electronics coupled to the microphone and the receiver, and conductive traces overlaying an insulator, the conductive traces configured to interconnect the hearing aid electronics and to follow non-planar contours of the insulator. Examples are provided wherein the insulator includes a hearing aid housing.

Abstract: Provided are a display substrate and a manufacturing method therefor, and a display device. The display substrate includes: a base substrate, a pixel defining layer (40, 40?) formed on the base substrate, and a light emitting layer located in a sub-pixel region (P) defined by the pixel defining layer (40, 40?), wherein, the pixel defining layer (40, 40?) includes: a reflecting layer (41, 41?), configured such that light emitted from the light emitting layer to the reflective layer (41, 41?) is reflected to a light outgoing side of the display substrate. The display device adopting the display substrate not only can effectively solve the problems of light leakage and light color interference, but also can effectively improve light out-coupling efficiency and color purity.

Abstract: A semiconductor package is disclosed. The semiconductor package comprises a lower package including a first substrate and a semiconductor chip on the first substrate, a second substrate on the lower package, interconnect terminals between the first substrate and the second substrate, and an adhesive pattern between a top surface of the semiconductor chip and a bottom surface of the second substrate. The adhesive pattern extends along an edge of the semiconductor chip. The adhesive pattern exposes a top surface of a central zone of the semiconductor chip.

Abstract: A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line. The semiconductor further comprises an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area and a first interconnect located in the first opening and in contact with the first redistribution line.

Abstract: An object of the present invention is to provide a power semiconductor module that can secure a satisfactory cooling without expanding the size of a case component. In the power semiconductor module according to the present invention, a frame case includes a front surface, a back surface, and a pair of side surfaces and formed with an opening part in at least one of the front surface and the back surface. A metal base is inserted into the opening part of the frame case. A frame case is provided with a joining part FW to which the peripheral part of the metal base and the peripheral part of the opening part of the frame case are joined. A first concaved part and a second concaved part are formed respectively in each of a pair of side surfaces of the frame case.

Abstract: A micro-electromechanical pressure transducer formed from a silicon die centers itself on a pedestal, formed from either a metal or a dielectric, by applying a predetermined amount of liquid epoxy adhesive to the square, top surface of the pedestal and allowing the liquid adhesive to distribute itself over the top surface. A MEMS die placed atop the liquid adhesive is centered on the top surface by surface tension between sides of the die and the top surface.

Abstract: An IC package having a semiconductor body that includes a monolithically integrated circuit and at least two metallic contact surfaces. The integrated circuit being connected to the two electrical contact surfaces via printed conductors, and being disposed on a carrier substrate and connected to the carrier substrate in a force-fitting manner. The carrier substrate including at least two terminal contacts that are connected to the two contact surfaces. The semiconductor body and the carrier substrate being covered by a casting compound forming one part of the IC package. A section of each of the two terminal contacts penetrating the IC package. The two terminal contacts being disposed on the carrier substrate, and each terminal contact and the carrier substrate disposed beneath the particular terminal contacts having a hole-like formation. The particular hole-like formation being designed as a through-connection for providing an electrical connection to another electrical component.

Abstract: A power semiconductor module includes a module housing and a circuit carrier having a dielectric insulation carrier and an upper metallization layer applied onto an upper side of the dielectric insulation carrier. A semiconductor component is arranged on the circuit carrier. The power semiconductor module also has an electrically conductive terminal block connected firmly and electrically conductively to the circuit carrier and/or to the semiconductor component. The terminal block has a screw thread that is accessible from an outer side of the module housing. A method for producing such a power semiconductor module is also provided.

Abstract: A touch panel includes a display region and conductive pad parts in which a portion thereof is exposed to a display region, wherein the conductive pad parts have a plurality of holes formed in at least a region including the exposed portion thereof. The touch panel is capable of significantly reducing an area of a non-display region, has excellent visibility of an image to be displayed by reducing visibility of a conductive pad part exposed in a display region, and has significantly reduced damage in a manufacturing process by preventing an occurrence or propagation of cracks.

Abstract: One aspect of the invention relates to a method for producing a chip assemblage. Two or more chip assemblies are produced in each case by cohesively and electrically conductively connecting an electrically conductive first compensation lamina to a first main electrode of a semiconductor chip. A control electrode interconnection structure is arranged in a free space between the chip assemblies. Electrically conductive connections are produced between the control electrode interconnection structure and control electrodes of the semiconductor chips of the individual chip assemblies. The chip assemblies are cohesively connected by means of a dielectric embedding compound.

Abstract: A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and at least one deep well within the at least one device layer. A protective layer is disposed over the at least one deep well, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 106 Ohm-cm.

Abstract: In one implementation, a semiconductor package assembly includes a semiconductor die, a first molding compound covering a back surface of the semiconductor die, a redistribution layer (RDL) structure disposed on a front surface of the semiconductor die, wherein the semiconductor die is coupled to the RDL structure, and a passive device, embedded in the redistribution layer (RDL) structure and coupled to the semiconductor die.

Abstract: A packaging process of a semiconductor device includes following steps. A patterned conductive layer and a solder resist layer that covers the patterned conductive layer are formed through 3D-printing over a carrier having a cavity. The patterned conductive layer and the solder resist layer extend to the outside of the cavity from the inside of the cavity. One portion of the patterned conductive layer is exposed by the solder resist layer. At least one semiconductor device is mounted on the patterned conductive layer in the cavity, such that the at least one semiconductor device is electrically connected to the patterned conductive layer.

Abstract: An LED panel is disclosed. The LED panel includes LED chips and a mount substrate on which the LED chips are mounted by flip bonding. Each of the LED chips includes a sapphire substrate, a plurality of light emitting cells disposed below the sapphire substrate, and an etched portion formed between the plurality of light emitting cells. Each of the LED chips includes a plurality of color cells formed corresponding to the plurality of light emitting cells on the sapphire substrate to change or maintain the color of light from the corresponding light emitting cells and a plurality of light collecting portions formed corresponding to the plurality of light emitting cells and the plurality of color cells on the bottom surface of the substrate and adapted to collect light from the corresponding light emitting cells on the corresponding color cells.

Abstract: A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post electrode component connected together by a support portion thereof are simultaneously fixed to and electrically connected to connection regions formed on an LSI chip. On the front face side, after resin sealing, the support portion is separated so as to expose front face wiring traces. On the back face side, the semiconductor substrate is grounded so as to expose tip ends of the through electrodes. The front face wiring traces exposed to the front face side and the tip ends of the through electrodes exposed to the back face side are used as wiring for external connection.

Abstract: A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and at least one deep well within the at least one device layer. A protective layer is disposed over the at least one deep well, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 106 Ohm-cm.

Abstract: In a general aspect, a packaged semiconductor device can include a semiconductor device and a metal leadframe structure having a signal lead that is electrically coupled with the semiconductor device. The device can also include a molding compound encapsulating at least a portion of the metal leadframe structure. At least a portion of the signal lead can be exposed outside the molding compound. The device can further include a solder plating disposed on exposed portions of the metal leadframe structure. In the device, a flank of the signal lead can have a surface area. At first portion of the surface area of the flank can be defined by the solder plating, and a second portion of the surface area of the flank can be defined by exposed metal of the metal leadframe structure. A perimeter of a surface of the exposed metal can have at least one curved edge.

Abstract: The present invention provides a heat dissipation device including a baseplate, one or more heat pipes in thermal communication with the baseplate, where the one or more heat pipes has one or more internal cavities, one or more vapor chambers coupled to the one or more heat pipes, where the one or more vapor chambers has one or more internal cavities, where the one or more internal cavities of the one or more heat pipes and the one or more internal cavities of the one or more the vapor chambers are contiguous, where the one or more vapor chambers extends from the one or more heat pipes, and heat conducting fins coupled to the one or more vapor chambers, where the one or more heat conducting fins extends from the one or more vapor chambers.

Abstract: An apparatus and method of producing a dual overmolded camera module. The dual overmolded camera module including a dual overmolded image sensor module having a first image sensor device and a second image sensor device spaced from one another in an x-direction at a predetermined alignment distance, and wherein at least one of the first image sensor device and the second image sensor device have a conductive via formed therethrough and a redistribution layer along at least one side. The dual overmolded camera module further including a first lens assembly and a second lens assembly mounted over respective ones of the first image sensor device and the second image sensor device, and wherein both the first lens assembly and the second lens assembly are aligned with a common target.

Abstract: The wide band frequency agile MIMO antenna is a 4-element, reconfigurable multi-input multi-output (MIMO) antenna system. Frequency agility in the design is achieved using varactor diodes tuned for various capacitance loadings. The MIMO antennas operate over a wide band, covering several well-known wireless standards between 1610-2710 MHz. The present design is simple in structure with low profile antenna elements. The design is prototyped on commercial plastic material with board dimensions 60×100×0.8 mm3 and is highly suitable to be used in frequency reconfigurable and cognitive radio based wireless handheld devices.

Abstract: Provided are a semiconductor device including an interposer having a relatively thin thickness without a through silicon via and a method of manufacturing the same. The method of manufacturing a semiconductor device includes forming an interposer including a redistribution layer and a dielectric layer on a dummy substrate, connecting a semiconductor die to the redistribution layer facing an upper portion of the interposer, encapsulating the semiconductor die by using an encapsulation, removing the dummy substrate from the interposer, and connecting a bump to the redistribution layer facing a lower portion of the interposer.

Abstract: A method of forming a semiconductor structure is disclosed. The method includes forming a semiconductor wafer having a device layer situated over a handle substrate, the device layer having at least one semiconductor device, forming a front side glass on a front side of the semiconductor wafer, and partially removing the handle substrate from a back side of the semiconductor wafer. The method also includes removing a portion of the semiconductor wafer from an outer perimeter thereof, either by sawing an edge trim trench through the handle substrate, the device layer and into the front side glass to form a ring, and removing the ring on the outer perimeter of the semiconductor wafer, or by edge grinding the outer perimeter of the semiconductor wafer. The method further includes completely removing the handle substrate.