Abstract: An integrated circuit is formed with structures spaced more closely together than a transverse dimension of such structures, such as for making contacts to electronic elements formed at minimum lithographically resolvable dimensions by dark field split pitch techniques. Acceptable overlay accuracy and process efficiency and throughput for the split pitch process that requires etching of a hard mark for each of a plurality of sequentially applied and patterned resist layers is supported by performing the etching of the hard mask entirely within a lithography track through using an acid sensitive hard mark material and an acidic overcoat which contacts areas of the hard mask through patterned apertures in the resist. The contacted areas of the hard mask are activated for development by baking of the acidic overcoat.

Abstract: A field emitter device consistent with certain embodiments has a substantially planar conductor forming a gate electrode. A conductive stripe forms a cathode on the insulating layer. An insulating layer covers at least a portion of the surface between the cathode and the gate. An anode is positioned above the cathode. An emitter structure, for example of carbon nanotubes is disposed on a surface of the cathodes closest to the anode. When an electric field is generated across the insulating layer, the cathode/emitter structure has a combination of work function and aspect ratio that causes electron emission from the emitter structure toward the anode at a field strength that is lower than that which causes emissions from other regions of the cathode. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Abstract: A nano-patterned substrate includes a plurality of nano-particles or nanopillars on an upper surface thereof. A ratio of height to diameter of each of the nano-particles or each of the nanopillars is either greater than or equal to 1. Particularly, a ratio of height to diameter of the nanopillars is greater than or equal to 5. Each of the nano-particles or each of the nanopillars has an arc-shaped top surface. When an epitaxial growth process is applied onto the nano-patterned substrate to form an epitaxial layer, the epitaxial layer has very low defect density. Thus, a production yield of fabricating the subsequent device can be improved.

Abstract: A semiconductor device including a semiconductor die in a die stack under-filled with a film. Once the semiconductor die are formed, they may be stacked and interconnected. The interconnection may leave a small space between semiconductor die in the die stack. This space is advantageously completely filled using a vapor deposition process where a coating is deposited as a vapor which flows over all surfaces of the die stack, including into the spaces between the die in the stack. The vapor then deposits on the surfaces between and around the die and forms a film which completely fills the spaces between the die in the die stack. The material used in the vapor deposition under-fill process may for example be a member of the parylene family of polymers, and in embodiments, may be parylene-N.

Abstract: Surface modification of individual nitride semiconductor layers occurs between growth stages to enhance the performance of the resulting multiple layer semiconductor structure device formed from multiple growth stages. Surface modifications may include, but are not limited, to laser patterning, lithographic patterning (with the scale ranging from 10 microns to a few angstroms), actinic radiation modifications, implantation, diffusional doping and combinations of these methods. The semiconductor structure device has enhanced crystal quality, reduced phonon reflections, improved light extraction, and an increased emission area. The ability to create these modifications is enabled by the thickness of the HVPE growth of the GaN semiconductor layer.

Abstract: Aspects of the present invention include a semiconductor device and method. In a transition region of a semiconductor material region, a near-surface compensation doping area with a conductivity type, which is different than the conductivity type of a transition doping area of the semiconductor material region, is provided in the surface region of the semiconductor material region. The doping of the near-surface compensation doping area of the semiconductor device at least partially compensates for the doping in the transition doping area.

Abstract: A nanorod is disclosed. It includes a linear body including three or less alternating regions including a first region and a second region, wherein the first region comprises a first material comprising a first ionic material and the second region comprises a second material comprising a second ionic material.

Abstract: An optoelectronic semiconductor body includes an epitaxial semiconductor layer sequence including a tunnel junction including an intermediate layer between an n-type tunnel junction layer and a p-type tunnel junction layer, wherein the intermediate layer has an n-barrier layer facing the n-type tunnel junction layer, a p-barrier layer facing the p-type tunnel junction layer, and a middle layer with a material composition differing from material compositions of the n-barrier layer and the p-barrier layer; and an active layer that emits electromagnetic radiation.

Abstract: A technique is provided which enables quantitative evaluation of an undercutting of deep trench structures in semiconductor wafers and, in particular, SOI wafers, by means of electrical or optical measuring. A specific control structure (100) having a defined ridge width is used which can be routinely measured in the course of the production process. The control structure comprises two adjacent trenches (5) each which are separated by a ridge having a defined ridge width. By undercutting (U) the adjacent trenches, the regions of undercutting of adjacent trenches may intersect each other starting from a specific minimum ridge width which results in a detachment of the ridge from the bottom making the ridge moveable. Mobility is determined by thermal deflection of the ridge. Arranging a plurality of control structures having various ridge widths enables determination of a quantitative amount of the undercutting.

Abstract: A semiconductor device is disclosed which includes active section 100, edge termination section 110 having a voltage blocking structure and disposed around active section 100, and separation section 120 having a device separation structure and disposed around edge termination section 110. A surface device structure is formed on the first major surface of active section 100, trench 23 is formed in separation section 120 from the second major surface side, and p+-type separation region 24 is formed on the side wall of trench 23 such that p+-type separation region 24 is in contact with p-type channel stopper region 21 formed in the surface portion on the first major surface side and p-type collector layer 9 formed in the surface portion on the second major surface side. The semiconductor device and the method for manufacturing the semiconductor device according to the invention facilitate preventing the reverse blocking voltage from decreasing and shorten the manufacturing time of the semiconductor device.

Abstract: A semiconductor material is provided comprising: a composition graded layer, formed on a Si substrate or an interlayer formed thereon, comprising a composition of AlXGa1-XN graded such that a content ratio of Al in the composition decreases continuously or discontinuously in a crystal growing direction; a superlattice composite layer, formed on the composition graded layer, comprising a high Al-containing layer comprising a composition of AlYGa1-YN and a low Al-containing layer comprising a composition of AlZGa1-ZN that are laminated alternately; and a nitride semiconductor layer formed on the superlattice composite layer.

Abstract: A semiconductor wafer and a method for cutting the same are provided, which enable separation of the semiconductor wafer by natural cleavage planes. The cutting method includes preparing a substrate including a semiconductor layer with at least one projection, formed on a predetermined area thereof; forming a post on an upper surface of the semiconductor layer at one or both sides of the projection to be placed on a cleaving line for cutting of the semiconductor layer; and cutting the substrate including the semiconductor layer along the cleaving line by performing a scribing process in a direction from the substrate and a breaking process in a direction from the semiconductor layer.

Abstract: Small feature patterning is accomplished using a multilayer hard mask (HM). Embodiments include sequentially forming a first HM layer and a multilayer HM layer over a substrate, the multilayer HM layer comprising sublayers, etching the multilayer HM layer to form a first opening having an upper first opening with sides converging to a lower second opening and a second opening with substantially parallel sides and an opening substantially corresponding to the lower second opening of the first opening, etching through the second opening to form a corresponding opening in the first HM layer, and etching the substrate through the corresponding opening in the first HM layer.

Abstract: This invention provides a selfsupporting substrate which consists of a n-type conductive aluminum nitride semiconductor crystal and is useful for manufacturing the vertical conductive type AlN semiconductor device. The n-type conductive aluminum nitride semiconductor crystal, by which the selfsupporting substrate is made up, contains Si atom at a concentration of 1×1018 to 5×1020 cm?3, is substantially free from halogen atoms, and substantially does not absorb the light having the energy of not more than 5.9 eV. The selfsupporting substrate can be obtained by a method comprising the steps of forming an AlN crystal layer on a single crystal substrate such as a sapphire by the HVPE method, preheating the obtained substrate having the AlN crystal layer to a temperature of 1,200° C. or more, forming a second layer consisting of the n-type conductive aluminum nitride semiconductor crystal is formed on the AlN crystal layer in high rate by the HVPE method and separating the second layer from the obtained laminate.

Abstract: A high quality Group III-Nitride semiconductor crystal with ultra-low dislocation density is grown epitaxially on a substrate via a particle film with multiple vertically-arranged layers of spheres with innumerable micro- and/or nano-voids formed among the spheres. The spheres can be composed of a variety of materials, and in particular silica or silicon dioxide (SiO2).

Abstract: This invention relates to an electronic semiconductive component comprising at least one layer (2,3) of a p-type or n-type material, wherein the layer of a said p- or n-type material is constituted by a metal hydride having a chosen dopant. The invention also relates to methods for producing the component.

Abstract: The present invention provides a fabrication method of a semiconductor substrate, by which a planar GaN substrate that is easily separated can be fabricated on a heterogeneous substrate, and a semiconductor device which is fabricated using the GaN substrate. The semiconductor substrate comprises a substrate, a first semiconductor layer arranged on the substrate, a metallic material layer arranged on the first semiconductor layer, a second semiconductor layer arranged on the first semiconductor layer and the metallic material layer, and voids formed in the first semiconductor layer under the metallic material layer.

Abstract: Methods are provided for substantially preventing and filling overetched regions in a silicon oxide layer of a semiconductor substrate. The overetched regions may be formed as a result of overetching of the silicon oxide layer during etching of an overlying silicon-comprising material layer to form a silicon-comprising structure. An etch resistant spacer may be formed after the initial or subsequent overetches. The etch resistant spacer may be formed by depositing an etch resistant material into the overetched region and etching the deposited etch resistant material to leave residual etch resistant material forming the etch resistant spacer. The etch resistant spacer may also be formed by exposing the silicon oxide layer in the overetched region to a nitrogen-supplying material to form a silicon oxynitride etch resistant spacer.

Abstract: A transistor includes a channel region with a first portion and a second portion. A length of the first portion is smaller than a length of the second portion. The first portion has a higher threshold voltage than the second portion. The lower threshold voltage of the second portion allows for an increased ON current. Despite the increase attained in the ON current, the higher threshold voltage of the first portion maintains or lowers a relatively low OFF current for the transistor.

Abstract: The present invention provides a method (80) for manufacturing a semiconductor tip. The method comprises obtaining (81) a substrate provided with a layer of tip material, providing (82) a doping profile in the layer of tip material, the doping profile comprising a tapered-shaped region of a first dopant concentration, undoped or lightly doped, e.g. having a dopant concentration of 1017 cm?3 or lower, surrounded by a region of a second dopant concentration, highly doped, e.g. having a dopant concentration above 1017 cm?3 , the first dopant concentration being lower than the second dopant concentration, and isotropically etching (83) the layer of tip material by using an etch chemistry for which the etch rate of tip material with the second dopant concentration is substantially higher than the etch rate of the tip material with the first dopant concentration.

Abstract: In some embodiments, an opening is formed through a first material, and sidewall topography of the opening is utilized to form a pair of separate anistropically etched spacers. The spacers are utilized to pattern lines in material underlying the spacers. Some embodiments include constructions having one or more openings which contain steep sidewalls joining to one another at shallow sidewall regions. The constructions may also contain lines along and directly against the steep sidewalls, and spaced from one another by gaps along the shallow sidewall regions.

Abstract: Circuits including a laterally diffused output driver transistor and a distinct device configured to provide electrostatic discharge (ESD) protection for the laterally diffused output driver transistor are presented. In general, the device configured to provide ESD protection includes a drain extended metal oxide semiconductor transistor (DEMOS) transistor configured to breakdown at a lower voltage than a breakdown voltage of the laterally diffused output driver transistor. The laterally diffused output driver transistor may be a pull-down or a pull-up output driver transistor. The device also includes a silicon controlled rectifier (SCR) configured to inject charge within a semiconductor layer of the circuit upon breakdown of the DEMOS transistor. Moreover, the device includes a region configured to collect the charge injected from the SCR and further includes an ohmic contact region configured to at least partially affect the holding voltage of the SCR.

Abstract: A semiconductor device includes a semiconductor substrate; a first base region of a first conductivity type provided in the semiconductor substrate; a buffer region of the first conductivity type provided on a lower surface of the first base region and having an impurity concentration higher than an impurity concentration of the first base region; an emitter region of a second conductivity type provided on a lower surface of the buffer region; a second base region of the second conductivity type selectively provided on an upper surface of the first base region; a diffusion region of the first conductivity type selectively provided on an upper surface of the second base region; a control electrode; a first main electrode; and a second main electrode. A junction interface between the buffer region and the first base region has a concave portion and a convex portion.

Abstract: The present invention relates to a method for manufacturing a hybrid semiconductor substrate comprising the steps of (a) providing a hybrid semiconductor substrate comprising a semiconductor-on-insulator (SeOI) region, that comprises an insulating layer over a base substrate and a SeOI layer over the insulating layer, and a bulk semiconductor region, wherein the SeOI region and the bulk semiconductor region share the same base substrate; (b) providing a mask layer over the SeOI region; and (c) forming a first impurity level by doping the SeOI region and the bulk semiconductor region simultaneously such that the first impurity level in the SeOI region is contained within the mask. Thereby avoiding higher number of process steps involved in the manufacturing process of hybrid semiconductor substrate.

Abstract: A semiconductor device includes a substrate formed of a first semiconductor material; two insulators on the substrate; and a semiconductor region having a portion between the two insulators and over the substrate. The semiconductor region has a bottom surface contacting the substrate and having sloped sidewalls. The semiconductor region is formed of a second semiconductor material different from the first semiconductor material.

Abstract: A method of producing a layered semiconductor device comprises the steps of: (a) providing a base comprising a plurality of semiconductor nano-structures, (b) growing a semiconductor material onto the nano-structures using an epitaxial 5 growth process, and (c) growing a layer of the semiconductor material using an epitaxial growth process.

Abstract: An optically-controlled power switch for use as an electrical switch is generally provided. The device can include a wide bandgap semiconducting material defining a stack having a p-n junction, a metal mask overlying the top surface of the stack and defining at least one opening to allow light to pass through the metal mask; a first lead wire connected to the metal stack; and a second lead wire connected to the bottom surface of the stack.

Abstract: Methods for forming semiconductor devices include providing a textured template, forming a buffer layer over the textured template, forming a substrate layer over the buffer layer, removing the textured template, thereby exposing a surface of the buffer layer, removing oxide from the exposed surface of the buffer layer, and forming a semiconductor layer over the exposed surface of the buffer layer.

Abstract: There is provided a method of manufacturing an SOI substrate which is practicable even when a supporting substrate having a low allowable temperature limit is used. A separation layer is formed in a region at a certain depth from a surface of a semiconductor substrate, and a first heat treatment is conducted when a semiconductor layer on the separation layer is bonded to the supporting substrate and separated. A second heat treatment is conducted to the supporting substrate to which the semiconductor layer is bonded. The second heat treatment is conducted at a temperature which is equal to or higher than the temperature of the first heat treatment and does not exceed a strain point of the supporting substrate. When the first heat treatment and the second heat treatment are conducted at the same temperature, a treatment time of the second heat treatment may be set to be longer.

Abstract: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips.

Abstract: A semiconductor component includes a semiconductor body and a second semiconductor zone of a first conductivity type that serves as a rear side emitter. The second semiconductor zone is preceded by a plurality of third semiconductor zones of a second conductivity type that is opposite to the first conductivity type. The third semiconductor zones are spaced apart from one another in a lateral direction. In addition, provided within the semiconductor body is a field stop zone spaced apart from the second semiconductor zone, thereby reducing an electric field in the direction toward the second semiconductor zone.

Abstract: A semiconductor includes an N-type impurity region provided in a substrate. A P-type RESURF layer is provided at a top face of the substrate in the N-type impurity region. A P-well has an impurity concentration higher than that of the P-type RESURF layer, and makes contact with the P-type RESURF layer at the top face of the substrate in the N-type impurity region. A first high-voltage-side plate is electrically connected to the N-type impurity region, and a low-voltage-side plate is electrically connected to a P-type impurity region. A lower field plate is capable of generating a lower capacitive coupling with the substrate. An upper field plate is located at a position farther from the substrate than the lower field plate, and is capable of generating an upper capacitive coupling with the lower field plate whose capacitance is greater than the capacitance of the lower capacitive coupling.

Abstract: A group-III nitride structure includes a substrate 102 and a fine wall-shaped structure 110 disposed to stand on the substrate 102 in a vertical direction relative to a surface of the substrate 102 and extending in an in-plane direction of the substrate 102. The fine wall-shaped structure 110 contains a group-III nitride semiconductor crystal, and h is larger than d assuming that the height of the fine wall-shaped structure 110 is h and the width of the fine wall-shaped structure 110 in a direction perpendicular to the height direction and the extending direction is d.

Abstract: A semiconductor structure includes a substrate having a first nitride-based semiconductor layer. A pseudomorphic protective layer is formed on the first nitride-based semiconductor layer and a second nitride-based semiconductor layer is formed on the pseudomorphic protective layer. The pseudomorphic protective layer has a thickness that is less than a critical thickness so that it drives the material quality of the second nitride-based semiconductor layer to correspond with that of the first nitride-based semiconductor layer.

Abstract: Briefly, in accordance with one or more embodiments, a semiconductor structure and method for forming the semiconductor structure are disclosed. The semiconductor structure may comprise a dielectric structure and one or more active areas or one or more field areas, for example, disposed proximate to the dielectric structure along a perimeter thereof. The dielectric structure and the other areas may be separated by one or more trenches or gaps to provide stress relief between the dielectric structure and the other areas. The one or more trenches may include one or more silicon formations formed there between to provide a spring like function and further provide stress relief between the dielectric structure and the other areas. Stress relief of the trenches may be further enhanced via hydrogen annealing to smooth sharp corners or other sharp features of the trenches such as scalloping.

Abstract: A superjunction device that includes a termination region having a transition region adjacent the active region thereof, the transition region including a plurality of spaced columns.

Abstract: A method of fabricating a semiconductor device is provided. First, a first electrode is formed over a first region of a substrate. Then, a dielectric layer covering the first electrode is formed over the substrate. After that, a plurality of openings is formed on the first region of the substrate. Thereafter, a conductive layer covering the dielectric layer and the openings is formed over the substrate. Then, the conductive layer in the bottom of the openings is removed to form second electrodes. After that, the dielectric layer between the second electrode and the first electrode is removed.

Abstract: Methods for fabrication of high aspect ratio micropillars and nanopillars are described. Use of alumina as an etch mask for the fabrication methods is also described. The resulting micropillars and nanopillars are analyzed and a characterization of the etch mask is provided.

Abstract: A phase modulation waveguide structure includes one of a semiconductor and a semiconductor-on-insulator substrate, a doped semiconductor layer formed over the one of a semiconductor and a semiconductor-on-insulator substrate, the doped semiconductor portion including a waveguide rib protruding from a surface thereof not in contact with the one of a semiconductor and a semiconductor-on-insulator substrate, and an electrical contact on top of the waveguide rib. The electrical contact is formed of a material with an optical refractive index close to that of a surrounding oxide layer that surrounds the waveguide rib and the electrical contact and lower than the optical refractive index of the doped semiconductor layer. During propagation of an optical mode within the waveguide structure, the electrical contact isolates the optical mode between the doped semiconductor layer and a metal electrode contact on top of the electrical contact.

Abstract: A semiconductor wafer includes dies to be scored from the semiconductor wafer. The semiconductor wafer also includes scribe-lines between the dies. Each scribe-line includes multiple through silicon vias.

Abstract: A method of manufacturing microstructures is disclosed, the method comprising a applying a mask to substrate; forming a pattern in the mask; processing the substrate according to the pattern; and mechanically removing the mask from the substrate. A polymer mask is disclosed for manufacturing micro scale structure, the polymer mask comprising a thin, preferably ultra thin flexible film. A method of manufacturing an integrated circuit is disclosed, the method comprising forming a plurality of isolated semiconductor devices on a common substrate; and connecting some of the devices. Apparatus for manufacturing microstructures is disclosed comprising: a mechanism for coating a mass substrate to create a structure; a mechanism for removing a mask from the substrate; and processing apparatus.

Abstract: A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include advantages such as reduced lattice mismatch at an epitaxial interface between two different semiconductor materials. One advantageous application of such an interface includes an electrical-optical communication structure. Methods such as deposition of layers at an elevated temperature provide easy formation of semiconductor structures with a modified lattice constant that permits an improved epitaxial interface.

Abstract: Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n± layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer.

Abstract: A method for forming a silicon film may be performed using a microheater including a substrate and a metal pattern spaced apart from the substrate. The silicon film may be formed on the metal pattern by applying a voltage to the metal pattern of the microheater to heat the metal pattern and by exposing the microheater to a source gas containing silicon. The silicon film may be made of polycrystalline silicon. A method for forming a pn junction may be performed using a microheater including a substrate, a conductive layer on the substrate, and a metal pattern spaced apart from the substrate. The pn junction may be formed between the metal pattern and the conductive layer by applying a voltage to the metal pattern of the microheater to heat the metal pattern. The pn junction may be made of polycrystalline silicon.

Abstract: An electrical fuse has a region of a first conductivity type in a continuous type polysilicon of a second conductivity type that is opposite the first conductivity type. In one embodiment of the invention the PN junction between the region and the poly fuse is reverse biased.

Abstract: Provided are a novel method and a novel structure for bringing a Ge or SiGe compound and a metal into ohmic contact with each other. A semiconductor device is provided with a portion composed of only i) Ge or SiGe compound, ii) a metal, and iii) an insulator or a semiconductor arranged between the material i) and the metal ii). In the semiconductor device, A) the material i) and the metal ii) have Schottky junction in the case where the holes of the material i) are majority carriers, and/or B) the material i) and the metal ii) are in an ohmic contact when the electrons of the material i) are majority carriers.

Abstract: Silicon wafers polished on their front sides are individually placed on a susceptor in an epitaxy reactor and firstly pretreated under a hydrogen atmosphere, and secondly with addition of an etching medium with a flow rate of 1.5-5 slm to the hydrogen atmosphere, the hydrogen flow rate being 1-100 slm in both steps, and subsequently epitaxially coated on the polished front side, and then removed from the reactor. In a second method, gas flows introduced into the reactor by injectors are distributed into outer and inner zones of the chamber, such that the inner zone gas flow acts on a wafer central region and the outer zone gas flow acts on a wafer edge region, the inner/outer distribution of the etching medium I/O=0-0.75. Silicon wafers having an epitaxial layer having global flatness value GBIR of 0.02-0.06 ?m, relative to an edge exclusion of 2 mm are produced.

Abstract: The disclosure provides a method for fabricating a semiconductor substrate comprising the steps of: providing a semiconductor on insulator type substrate, providing a diffusion barrier layer and providing a second semiconductor layer. By providing the diffusion barrier layer, it becomes possible to suppress diffusion from the highly doped first semiconductor layer into the second semiconductor layer. The invention also relates to a corresponding semiconductor substrate and opto-electronic devices comprising such a substrate.

Abstract: The present invention describes a method of and an apparatus for providing a wafer, the wafer including Silicon; etching trenches in the wafer to form Silicon fins; filling Silicon Oxide in the trenches; planarizing the Silicon Oxide; recessing the Silicon Oxide to a first thickness to form exposed Silicon pedestals from the Silicon fins; depositing SiGe over the exposed Silicon pedestal; recessing the Silicon Oxide to a second thickness; undercutting the exposed Silicon pedestals to form necked-in Silicon pedestals; oxidizing thermally and annealing the SiGe; and forming Germanium nanowires.

Abstract: This invention discloses a thermoelectric structure for cooling an integrated circuit (IC) chip, the thermoelectric structure comprises a first type superlattice layer formed on top of the IC chip connected to a first voltage, and a second type superlattice layer formed on the bottom of the IC chip connected to a second voltage, the second voltage being different from the first voltage, wherein an power supply current flows through the first and second type superlattice layer for cooling the IC chip.